Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/amd64/amd64/machdep.c
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1 /*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include "opt_atalk.h" 45 #include "opt_atpic.h" 46 #include "opt_compat.h" 47 #include "opt_cpu.h" 48 #include "opt_ddb.h" 49 #include "opt_inet.h" 50 #include "opt_ipx.h" 51 #include "opt_isa.h" 52 #include "opt_kstack_pages.h" 53 #include "opt_maxmem.h" 54 #include "opt_msgbuf.h" 55 #include "opt_perfmon.h" 56 57 #include <sys/param.h> 58 #include <sys/proc.h> 59 #include <sys/systm.h> 60 #include <sys/bio.h> 61 #include <sys/buf.h> 62 #include <sys/bus.h> 63 #include <sys/callout.h> 64 #include <sys/clock.h> 65 #include <sys/cons.h> 66 #include <sys/cpu.h> 67 #include <sys/eventhandler.h> 68 #include <sys/exec.h> 69 #include <sys/imgact.h> 70 #include <sys/kdb.h> 71 #include <sys/kernel.h> 72 #include <sys/ktr.h> 73 #include <sys/linker.h> 74 #include <sys/lock.h> 75 #include <sys/malloc.h> 76 #include <sys/memrange.h> 77 #include <sys/msgbuf.h> 78 #include <sys/mutex.h> 79 #include <sys/pcpu.h> 80 #include <sys/ptrace.h> 81 #include <sys/reboot.h> 82 #include <sys/sched.h> 83 #include <sys/signalvar.h> 84 #include <sys/sysctl.h> 85 #include <sys/sysent.h> 86 #include <sys/sysproto.h> 87 #include <sys/ucontext.h> 88 #include <sys/vmmeter.h> 89 90 #include <vm/vm.h> 91 #include <vm/vm_extern.h> 92 #include <vm/vm_kern.h> 93 #include <vm/vm_page.h> 94 #include <vm/vm_map.h> 95 #include <vm/vm_object.h> 96 #include <vm/vm_pager.h> 97 #include <vm/vm_param.h> 98 99 #ifdef DDB 100 #ifndef KDB 101 #error KDB must be enabled in order for DDB to work! 102 #endif 103 #endif 104 #include <ddb/ddb.h> 105 106 #include <net/netisr.h> 107 108 #include <machine/clock.h> 109 #include <machine/cpu.h> 110 #include <machine/cputypes.h> 111 #include <machine/intr_machdep.h> 112 #include <machine/md_var.h> 113 #include <machine/metadata.h> 114 #include <machine/pc/bios.h> 115 #include <machine/pcb.h> 116 #include <machine/proc.h> 117 #include <machine/reg.h> 118 #include <machine/sigframe.h> 119 #include <machine/specialreg.h> 120 #ifdef PERFMON 121 #include <machine/perfmon.h> 122 #endif 123 #include <machine/tss.h> 124 #ifdef SMP 125 #include <machine/smp.h> 126 #endif 127 128 #ifdef DEV_ATPIC 129 #include <amd64/isa/icu.h> 130 #else 131 #include <machine/apicvar.h> 132 #endif 133 134 #include <isa/isareg.h> 135 #include <isa/rtc.h> 136 137 /* Sanity check for __curthread() */ 138 CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); 139 140 extern u_int64_t hammer_time(u_int64_t, u_int64_t); 141 142 extern void printcpuinfo(void); /* XXX header file */ 143 extern void identify_cpu(void); 144 extern void panicifcpuunsupported(void); 145 146 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 147 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 148 149 static void cpu_startup(void *); 150 static void get_fpcontext(struct thread *td, mcontext_t *mcp); 151 static int set_fpcontext(struct thread *td, const mcontext_t *mcp); 152 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 153 154 #ifdef DDB 155 extern vm_offset_t ksym_start, ksym_end; 156 #endif 157 158 /* Intel ICH registers */ 159 #define ICH_PMBASE 0x400 160 #define ICH_SMI_EN ICH_PMBASE + 0x30 161 162 int _udatasel, _ucodesel, _ucode32sel; 163 164 int cold = 1; 165 166 long Maxmem = 0; 167 long realmem = 0; 168 169 /* 170 * The number of PHYSMAP entries must be one less than the number of 171 * PHYSSEG entries because the PHYSMAP entry that spans the largest 172 * physical address that is accessible by ISA DMA is split into two 173 * PHYSSEG entries. 174 */ 175 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 176 177 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 178 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 179 180 /* must be 2 less so 0 0 can signal end of chunks */ 181 #define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2) 182 #define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2) 183 184 struct kva_md_info kmi; 185 186 static struct trapframe proc0_tf; 187 struct region_descriptor r_gdt, r_idt; 188 189 struct pcpu __pcpu[MAXCPU]; 190 191 struct mtx icu_lock; 192 193 struct mem_range_softc mem_range_softc; 194 195 static void 196 cpu_startup(dummy) 197 void *dummy; 198 { 199 char *sysenv; 200 201 /* 202 * On MacBooks, we need to disallow the legacy USB circuit to 203 * generate an SMI# because this can cause several problems, 204 * namely: incorrect CPU frequency detection and failure to 205 * start the APs. 206 * We do this by disabling a bit in the SMI_EN (SMI Control and 207 * Enable register) of the Intel ICH LPC Interface Bridge. 208 */ 209 sysenv = getenv("smbios.system.product"); 210 if (sysenv != NULL) { 211 if (strncmp(sysenv, "MacBook", 7) == 0) { 212 if (bootverbose) 213 printf("Disabling LEGACY_USB_EN bit on " 214 "Intel ICH.\n"); 215 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8); 216 } 217 freeenv(sysenv); 218 } 219 220 /* 221 * Good {morning,afternoon,evening,night}. 222 */ 223 startrtclock(); 224 printcpuinfo(); 225 panicifcpuunsupported(); 226 #ifdef PERFMON 227 perfmon_init(); 228 #endif 229 printf("usable memory = %ju (%ju MB)\n", ptoa((uintmax_t)physmem), 230 ptoa((uintmax_t)physmem) / 1048576); 231 realmem = Maxmem; 232 /* 233 * Display any holes after the first chunk of extended memory. 234 */ 235 if (bootverbose) { 236 int indx; 237 238 printf("Physical memory chunk(s):\n"); 239 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 240 vm_paddr_t size; 241 242 size = phys_avail[indx + 1] - phys_avail[indx]; 243 printf( 244 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", 245 (uintmax_t)phys_avail[indx], 246 (uintmax_t)phys_avail[indx + 1] - 1, 247 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE); 248 } 249 } 250 251 vm_ksubmap_init(&kmi); 252 253 printf("avail memory = %ju (%ju MB)\n", 254 ptoa((uintmax_t)cnt.v_free_count), 255 ptoa((uintmax_t)cnt.v_free_count) / 1048576); 256 257 /* 258 * Set up buffers, so they can be used to read disk labels. 259 */ 260 bufinit(); 261 vm_pager_bufferinit(); 262 263 cpu_setregs(); 264 } 265 266 /* 267 * Send an interrupt to process. 268 * 269 * Stack is set up to allow sigcode stored 270 * at top to call routine, followed by kcall 271 * to sigreturn routine below. After sigreturn 272 * resets the signal mask, the stack, and the 273 * frame pointer, it returns to the user 274 * specified pc, psl. 275 */ 276 void 277 sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask) 278 { 279 struct sigframe sf, *sfp; 280 struct proc *p; 281 struct thread *td; 282 struct sigacts *psp; 283 char *sp; 284 struct trapframe *regs; 285 int sig; 286 int oonstack; 287 288 td = curthread; 289 p = td->td_proc; 290 PROC_LOCK_ASSERT(p, MA_OWNED); 291 sig = ksi->ksi_signo; 292 psp = p->p_sigacts; 293 mtx_assert(&psp->ps_mtx, MA_OWNED); 294 regs = td->td_frame; 295 oonstack = sigonstack(regs->tf_rsp); 296 297 /* Save user context. */ 298 bzero(&sf, sizeof(sf)); 299 sf.sf_uc.uc_sigmask = *mask; 300 sf.sf_uc.uc_stack = td->td_sigstk; 301 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) 302 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE; 303 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0; 304 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs)); 305 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */ 306 get_fpcontext(td, &sf.sf_uc.uc_mcontext); 307 fpstate_drop(td); 308 309 /* Allocate space for the signal handler context. */ 310 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack && 311 SIGISMEMBER(psp->ps_sigonstack, sig)) { 312 sp = td->td_sigstk.ss_sp + 313 td->td_sigstk.ss_size - sizeof(struct sigframe); 314 #if defined(COMPAT_43) 315 td->td_sigstk.ss_flags |= SS_ONSTACK; 316 #endif 317 } else 318 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 319 /* Align to 16 bytes. */ 320 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul); 321 322 /* Translate the signal if appropriate. */ 323 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize) 324 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 325 326 /* Build the argument list for the signal handler. */ 327 regs->tf_rdi = sig; /* arg 1 in %rdi */ 328 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */ 329 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 330 /* Signal handler installed with SA_SIGINFO. */ 331 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */ 332 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 333 334 /* Fill in POSIX parts */ 335 sf.sf_si = ksi->ksi_info; 336 sf.sf_si.si_signo = sig; /* maybe a translated signal */ 337 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 338 } else { 339 /* Old FreeBSD-style arguments. */ 340 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */ 341 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 342 sf.sf_ahu.sf_handler = catcher; 343 } 344 mtx_unlock(&psp->ps_mtx); 345 PROC_UNLOCK(p); 346 347 /* 348 * Copy the sigframe out to the user's stack. 349 */ 350 if (copyout(&sf, sfp, sizeof(*sfp)) != 0) { 351 #ifdef DEBUG 352 printf("process %ld has trashed its stack\n", (long)p->p_pid); 353 #endif 354 PROC_LOCK(p); 355 sigexit(td, SIGILL); 356 } 357 358 regs->tf_rsp = (long)sfp; 359 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode); 360 regs->tf_rflags &= ~(PSL_T | PSL_D); 361 regs->tf_cs = _ucodesel; 362 PROC_LOCK(p); 363 mtx_lock(&psp->ps_mtx); 364 } 365 366 /* 367 * System call to cleanup state after a signal 368 * has been taken. Reset signal mask and 369 * stack state from context left by sendsig (above). 370 * Return to previous pc and psl as specified by 371 * context left by sendsig. Check carefully to 372 * make sure that the user has not modified the 373 * state to gain improper privileges. 374 * 375 * MPSAFE 376 */ 377 int 378 sigreturn(td, uap) 379 struct thread *td; 380 struct sigreturn_args /* { 381 const struct __ucontext *sigcntxp; 382 } */ *uap; 383 { 384 ucontext_t uc; 385 struct proc *p = td->td_proc; 386 struct trapframe *regs; 387 const ucontext_t *ucp; 388 long rflags; 389 int cs, error, ret; 390 ksiginfo_t ksi; 391 392 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 393 if (error != 0) 394 return (error); 395 ucp = &uc; 396 regs = td->td_frame; 397 rflags = ucp->uc_mcontext.mc_rflags; 398 /* 399 * Don't allow users to change privileged or reserved flags. 400 */ 401 /* 402 * XXX do allow users to change the privileged flag PSL_RF. 403 * The cpu sets PSL_RF in tf_rflags for faults. Debuggers 404 * should sometimes set it there too. tf_rflags is kept in 405 * the signal context during signal handling and there is no 406 * other place to remember it, so the PSL_RF bit may be 407 * corrupted by the signal handler without us knowing. 408 * Corruption of the PSL_RF bit at worst causes one more or 409 * one less debugger trap, so allowing it is fairly harmless. 410 */ 411 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 412 printf("sigreturn: rflags = 0x%lx\n", rflags); 413 return (EINVAL); 414 } 415 416 /* 417 * Don't allow users to load a valid privileged %cs. Let the 418 * hardware check for invalid selectors, excess privilege in 419 * other selectors, invalid %eip's and invalid %esp's. 420 */ 421 cs = ucp->uc_mcontext.mc_cs; 422 if (!CS_SECURE(cs)) { 423 printf("sigreturn: cs = 0x%x\n", cs); 424 ksiginfo_init_trap(&ksi); 425 ksi.ksi_signo = SIGBUS; 426 ksi.ksi_code = BUS_OBJERR; 427 ksi.ksi_trapno = T_PROTFLT; 428 ksi.ksi_addr = (void *)regs->tf_rip; 429 trapsignal(td, &ksi); 430 return (EINVAL); 431 } 432 433 ret = set_fpcontext(td, &ucp->uc_mcontext); 434 if (ret != 0) 435 return (ret); 436 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs)); 437 438 PROC_LOCK(p); 439 #if defined(COMPAT_43) 440 if (ucp->uc_mcontext.mc_onstack & 1) 441 td->td_sigstk.ss_flags |= SS_ONSTACK; 442 else 443 td->td_sigstk.ss_flags &= ~SS_ONSTACK; 444 #endif 445 446 td->td_sigmask = ucp->uc_sigmask; 447 SIG_CANTMASK(td->td_sigmask); 448 signotify(td); 449 PROC_UNLOCK(p); 450 td->td_pcb->pcb_flags |= PCB_FULLCTX; 451 return (EJUSTRETURN); 452 } 453 454 #ifdef COMPAT_FREEBSD4 455 int 456 freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap) 457 { 458 459 return sigreturn(td, (struct sigreturn_args *)uap); 460 } 461 #endif 462 463 464 /* 465 * Machine dependent boot() routine 466 * 467 * I haven't seen anything to put here yet 468 * Possibly some stuff might be grafted back here from boot() 469 */ 470 void 471 cpu_boot(int howto) 472 { 473 } 474 475 /* Get current clock frequency for the given cpu id. */ 476 int 477 cpu_est_clockrate(int cpu_id, uint64_t *rate) 478 { 479 register_t reg; 480 uint64_t tsc1, tsc2; 481 482 if (pcpu_find(cpu_id) == NULL || rate == NULL) 483 return (EINVAL); 484 485 /* If we're booting, trust the rate calibrated moments ago. */ 486 if (cold) { 487 *rate = tsc_freq; 488 return (0); 489 } 490 491 #ifdef SMP 492 /* Schedule ourselves on the indicated cpu. */ 493 thread_lock(curthread); 494 sched_bind(curthread, cpu_id); 495 thread_unlock(curthread); 496 #endif 497 498 /* Calibrate by measuring a short delay. */ 499 reg = intr_disable(); 500 tsc1 = rdtsc(); 501 DELAY(1000); 502 tsc2 = rdtsc(); 503 intr_restore(reg); 504 505 #ifdef SMP 506 thread_lock(curthread); 507 sched_unbind(curthread); 508 thread_unlock(curthread); 509 #endif 510 511 /* 512 * Calculate the difference in readings, convert to Mhz, and 513 * subtract 0.5% of the total. Empirical testing has shown that 514 * overhead in DELAY() works out to approximately this value. 515 */ 516 tsc2 -= tsc1; 517 *rate = tsc2 * 1000 - tsc2 * 5; 518 return (0); 519 } 520 521 /* 522 * Shutdown the CPU as much as possible 523 */ 524 void 525 cpu_halt(void) 526 { 527 for (;;) 528 __asm__ ("hlt"); 529 } 530 531 /* 532 * Hook to idle the CPU when possible. In the SMP case we default to 533 * off because a halted cpu will not currently pick up a new thread in the 534 * run queue until the next timer tick. If turned on this will result in 535 * approximately a 4.2% loss in real time performance in buildworld tests 536 * (but improves user and sys times oddly enough), and saves approximately 537 * 5% in power consumption on an idle machine (tests w/2xCPU 1.1GHz P3). 538 * 539 * XXX we need to have a cpu mask of idle cpus and generate an IPI or 540 * otherwise generate some sort of interrupt to wake up cpus sitting in HLT. 541 * Then we can have our cake and eat it too. 542 * 543 * XXX I'm turning it on for SMP as well by default for now. It seems to 544 * help lock contention somewhat, and this is critical for HTT. -Peter 545 */ 546 static int cpu_idle_hlt = 1; 547 TUNABLE_INT("machdep.cpu_idle_hlt", &cpu_idle_hlt); 548 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW, 549 &cpu_idle_hlt, 0, "Idle loop HLT enable"); 550 551 static void 552 cpu_idle_default(void) 553 { 554 /* 555 * we must absolutely guarentee that hlt is the 556 * absolute next instruction after sti or we 557 * introduce a timing window. 558 */ 559 __asm __volatile("sti; hlt"); 560 } 561 562 /* 563 * Note that we have to be careful here to avoid a race between checking 564 * sched_runnable() and actually halting. If we don't do this, we may waste 565 * the time between calling hlt and the next interrupt even though there 566 * is a runnable process. 567 */ 568 void 569 cpu_idle(void) 570 { 571 572 #ifdef SMP 573 if (mp_grab_cpu_hlt()) 574 return; 575 #endif 576 if (cpu_idle_hlt) { 577 disable_intr(); 578 if (sched_runnable()) 579 enable_intr(); 580 else 581 (*cpu_idle_hook)(); 582 } 583 } 584 585 /* Other subsystems (e.g., ACPI) can hook this later. */ 586 void (*cpu_idle_hook)(void) = cpu_idle_default; 587 588 /* 589 * Reset registers to default values on exec. 590 */ 591 void 592 exec_setregs(td, entry, stack, ps_strings) 593 struct thread *td; 594 u_long entry; 595 u_long stack; 596 u_long ps_strings; 597 { 598 struct trapframe *regs = td->td_frame; 599 struct pcb *pcb = td->td_pcb; 600 601 critical_enter(); 602 wrmsr(MSR_FSBASE, 0); 603 wrmsr(MSR_KGSBASE, 0); /* User value while we're in the kernel */ 604 pcb->pcb_fsbase = 0; 605 pcb->pcb_gsbase = 0; 606 critical_exit(); 607 pcb->pcb_flags &= ~(PCB_32BIT | PCB_GS32BIT); 608 load_ds(_udatasel); 609 load_es(_udatasel); 610 load_fs(_udatasel); 611 load_gs(_udatasel); 612 pcb->pcb_ds = _udatasel; 613 pcb->pcb_es = _udatasel; 614 pcb->pcb_fs = _udatasel; 615 pcb->pcb_gs = _udatasel; 616 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__; 617 618 bzero((char *)regs, sizeof(struct trapframe)); 619 regs->tf_rip = entry; 620 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; 621 regs->tf_rdi = stack; /* argv */ 622 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 623 regs->tf_ss = _udatasel; 624 regs->tf_cs = _ucodesel; 625 626 /* 627 * Reset the hardware debug registers if they were in use. 628 * They won't have any meaning for the newly exec'd process. 629 */ 630 if (pcb->pcb_flags & PCB_DBREGS) { 631 pcb->pcb_dr0 = 0; 632 pcb->pcb_dr1 = 0; 633 pcb->pcb_dr2 = 0; 634 pcb->pcb_dr3 = 0; 635 pcb->pcb_dr6 = 0; 636 pcb->pcb_dr7 = 0; 637 if (pcb == PCPU_GET(curpcb)) { 638 /* 639 * Clear the debug registers on the running 640 * CPU, otherwise they will end up affecting 641 * the next process we switch to. 642 */ 643 reset_dbregs(); 644 } 645 pcb->pcb_flags &= ~PCB_DBREGS; 646 } 647 648 /* 649 * Drop the FP state if we hold it, so that the process gets a 650 * clean FP state if it uses the FPU again. 651 */ 652 fpstate_drop(td); 653 } 654 655 void 656 cpu_setregs(void) 657 { 658 register_t cr0; 659 660 cr0 = rcr0(); 661 /* 662 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the 663 * BSP. See the comments there about why we set them. 664 */ 665 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; 666 load_cr0(cr0); 667 } 668 669 /* 670 * Initialize amd64 and configure to run kernel 671 */ 672 673 /* 674 * Initialize segments & interrupt table 675 */ 676 677 struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */ 678 static struct gate_descriptor idt0[NIDT]; 679 struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ 680 681 static char dblfault_stack[PAGE_SIZE] __aligned(16); 682 683 struct amd64tss common_tss[MAXCPU]; 684 685 /* software prototypes -- in more palatable form */ 686 struct soft_segment_descriptor gdt_segs[] = { 687 /* GNULL_SEL 0 Null Descriptor */ 688 { 0x0, /* segment base address */ 689 0x0, /* length */ 690 0, /* segment type */ 691 0, /* segment descriptor priority level */ 692 0, /* segment descriptor present */ 693 0, /* long */ 694 0, /* default 32 vs 16 bit size */ 695 0 /* limit granularity (byte/page units)*/ }, 696 /* GCODE_SEL 1 Code Descriptor for kernel */ 697 { 0x0, /* segment base address */ 698 0xfffff, /* length - all address space */ 699 SDT_MEMERA, /* segment type */ 700 SEL_KPL, /* segment descriptor priority level */ 701 1, /* segment descriptor present */ 702 1, /* long */ 703 0, /* default 32 vs 16 bit size */ 704 1 /* limit granularity (byte/page units)*/ }, 705 /* GDATA_SEL 2 Data Descriptor for kernel */ 706 { 0x0, /* segment base address */ 707 0xfffff, /* length - all address space */ 708 SDT_MEMRWA, /* segment type */ 709 SEL_KPL, /* segment descriptor priority level */ 710 1, /* segment descriptor present */ 711 1, /* long */ 712 0, /* default 32 vs 16 bit size */ 713 1 /* limit granularity (byte/page units)*/ }, 714 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */ 715 { 0x0, /* segment base address */ 716 0xfffff, /* length - all address space */ 717 SDT_MEMERA, /* segment type */ 718 SEL_UPL, /* segment descriptor priority level */ 719 1, /* segment descriptor present */ 720 0, /* long */ 721 1, /* default 32 vs 16 bit size */ 722 1 /* limit granularity (byte/page units)*/ }, 723 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */ 724 { 0x0, /* segment base address */ 725 0xfffff, /* length - all address space */ 726 SDT_MEMRWA, /* segment type */ 727 SEL_UPL, /* segment descriptor priority level */ 728 1, /* segment descriptor present */ 729 0, /* long */ 730 1, /* default 32 vs 16 bit size */ 731 1 /* limit granularity (byte/page units)*/ }, 732 /* GUCODE_SEL 5 64 bit Code Descriptor for user */ 733 { 0x0, /* segment base address */ 734 0xfffff, /* length - all address space */ 735 SDT_MEMERA, /* segment type */ 736 SEL_UPL, /* segment descriptor priority level */ 737 1, /* segment descriptor present */ 738 1, /* long */ 739 0, /* default 32 vs 16 bit size */ 740 1 /* limit granularity (byte/page units)*/ }, 741 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */ 742 { 743 0x0, /* segment base address */ 744 sizeof(struct amd64tss)-1,/* length */ 745 SDT_SYSTSS, /* segment type */ 746 SEL_KPL, /* segment descriptor priority level */ 747 1, /* segment descriptor present */ 748 0, /* long */ 749 0, /* unused - default 32 vs 16 bit size */ 750 0 /* limit granularity (byte/page units)*/ }, 751 /* Actually, the TSS is a system descriptor which is double size */ 752 { 0x0, /* segment base address */ 753 0x0, /* length */ 754 0, /* segment type */ 755 0, /* segment descriptor priority level */ 756 0, /* segment descriptor present */ 757 0, /* long */ 758 0, /* default 32 vs 16 bit size */ 759 0 /* limit granularity (byte/page units)*/ }, 760 /* GUGS32_SEL 8 32 bit GS Descriptor for user */ 761 { 0x0, /* segment base address */ 762 0xfffff, /* length - all address space */ 763 SDT_MEMRWA, /* segment type */ 764 SEL_UPL, /* segment descriptor priority level */ 765 1, /* segment descriptor present */ 766 0, /* long */ 767 1, /* default 32 vs 16 bit size */ 768 1 /* limit granularity (byte/page units)*/ }, 769 }; 770 771 void 772 setidt(idx, func, typ, dpl, ist) 773 int idx; 774 inthand_t *func; 775 int typ; 776 int dpl; 777 int ist; 778 { 779 struct gate_descriptor *ip; 780 781 ip = idt + idx; 782 ip->gd_looffset = (uintptr_t)func; 783 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 784 ip->gd_ist = ist; 785 ip->gd_xx = 0; 786 ip->gd_type = typ; 787 ip->gd_dpl = dpl; 788 ip->gd_p = 1; 789 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 790 } 791 792 extern inthand_t 793 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 794 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 795 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 796 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 797 IDTVEC(xmm), IDTVEC(dblfault), 798 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 799 800 void 801 sdtossd(sd, ssd) 802 struct user_segment_descriptor *sd; 803 struct soft_segment_descriptor *ssd; 804 { 805 806 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 807 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 808 ssd->ssd_type = sd->sd_type; 809 ssd->ssd_dpl = sd->sd_dpl; 810 ssd->ssd_p = sd->sd_p; 811 ssd->ssd_long = sd->sd_long; 812 ssd->ssd_def32 = sd->sd_def32; 813 ssd->ssd_gran = sd->sd_gran; 814 } 815 816 void 817 ssdtosd(ssd, sd) 818 struct soft_segment_descriptor *ssd; 819 struct user_segment_descriptor *sd; 820 { 821 822 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 823 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 824 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 825 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 826 sd->sd_type = ssd->ssd_type; 827 sd->sd_dpl = ssd->ssd_dpl; 828 sd->sd_p = ssd->ssd_p; 829 sd->sd_long = ssd->ssd_long; 830 sd->sd_def32 = ssd->ssd_def32; 831 sd->sd_gran = ssd->ssd_gran; 832 } 833 834 void 835 ssdtosyssd(ssd, sd) 836 struct soft_segment_descriptor *ssd; 837 struct system_segment_descriptor *sd; 838 { 839 840 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 841 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 842 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 843 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 844 sd->sd_type = ssd->ssd_type; 845 sd->sd_dpl = ssd->ssd_dpl; 846 sd->sd_p = ssd->ssd_p; 847 sd->sd_gran = ssd->ssd_gran; 848 } 849 850 #if !defined(DEV_ATPIC) && defined(DEV_ISA) 851 #include <isa/isavar.h> 852 u_int 853 isa_irq_pending(void) 854 { 855 856 return (0); 857 } 858 #endif 859 860 u_int basemem; 861 862 /* 863 * Populate the (physmap) array with base/bound pairs describing the 864 * available physical memory in the system, then test this memory and 865 * build the phys_avail array describing the actually-available memory. 866 * 867 * If we cannot accurately determine the physical memory map, then use 868 * value from the 0xE801 call, and failing that, the RTC. 869 * 870 * Total memory size may be set by the kernel environment variable 871 * hw.physmem or the compile-time define MAXMEM. 872 * 873 * XXX first should be vm_paddr_t. 874 */ 875 static void 876 getmemsize(caddr_t kmdp, u_int64_t first) 877 { 878 int i, off, physmap_idx, pa_indx, da_indx; 879 vm_paddr_t pa, physmap[PHYSMAP_SIZE]; 880 u_long physmem_tunable; 881 pt_entry_t *pte; 882 struct bios_smap *smapbase, *smap, *smapend; 883 u_int32_t smapsize; 884 quad_t dcons_addr, dcons_size; 885 886 bzero(physmap, sizeof(physmap)); 887 basemem = 0; 888 physmap_idx = 0; 889 890 /* 891 * get memory map from INT 15:E820, kindly supplied by the loader. 892 * 893 * subr_module.c says: 894 * "Consumer may safely assume that size value precedes data." 895 * ie: an int32_t immediately precedes smap. 896 */ 897 smapbase = (struct bios_smap *)preload_search_info(kmdp, 898 MODINFO_METADATA | MODINFOMD_SMAP); 899 if (smapbase == NULL) 900 panic("No BIOS smap info from loader!"); 901 902 smapsize = *((u_int32_t *)smapbase - 1); 903 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 904 905 for (smap = smapbase; smap < smapend; smap++) { 906 if (boothowto & RB_VERBOSE) 907 printf("SMAP type=%02x base=%016lx len=%016lx\n", 908 smap->type, smap->base, smap->length); 909 910 if (smap->type != SMAP_TYPE_MEMORY) 911 continue; 912 913 if (smap->length == 0) 914 continue; 915 916 for (i = 0; i <= physmap_idx; i += 2) { 917 if (smap->base < physmap[i + 1]) { 918 if (boothowto & RB_VERBOSE) 919 printf( 920 "Overlapping or non-monotonic memory region, ignoring second region\n"); 921 continue; 922 } 923 } 924 925 if (smap->base == physmap[physmap_idx + 1]) { 926 physmap[physmap_idx + 1] += smap->length; 927 continue; 928 } 929 930 physmap_idx += 2; 931 if (physmap_idx == PHYSMAP_SIZE) { 932 printf( 933 "Too many segments in the physical address map, giving up\n"); 934 break; 935 } 936 physmap[physmap_idx] = smap->base; 937 physmap[physmap_idx + 1] = smap->base + smap->length; 938 } 939 940 /* 941 * Find the 'base memory' segment for SMP 942 */ 943 basemem = 0; 944 for (i = 0; i <= physmap_idx; i += 2) { 945 if (physmap[i] == 0x00000000) { 946 basemem = physmap[i + 1] / 1024; 947 break; 948 } 949 } 950 if (basemem == 0) 951 panic("BIOS smap did not include a basemem segment!"); 952 953 #ifdef SMP 954 /* make hole for AP bootstrap code */ 955 physmap[1] = mp_bootaddress(physmap[1] / 1024); 956 #endif 957 958 /* 959 * Maxmem isn't the "maximum memory", it's one larger than the 960 * highest page of the physical address space. It should be 961 * called something like "Maxphyspage". We may adjust this 962 * based on ``hw.physmem'' and the results of the memory test. 963 */ 964 Maxmem = atop(physmap[physmap_idx + 1]); 965 966 #ifdef MAXMEM 967 Maxmem = MAXMEM / 4; 968 #endif 969 970 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 971 Maxmem = atop(physmem_tunable); 972 973 /* 974 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 975 * in the system. 976 */ 977 if (Maxmem > atop(physmap[physmap_idx + 1])) 978 Maxmem = atop(physmap[physmap_idx + 1]); 979 980 if (atop(physmap[physmap_idx + 1]) != Maxmem && 981 (boothowto & RB_VERBOSE)) 982 printf("Physical memory use set to %ldK\n", Maxmem * 4); 983 984 /* call pmap initialization to make new kernel address space */ 985 pmap_bootstrap(&first); 986 987 /* 988 * Size up each available chunk of physical memory. 989 */ 990 physmap[0] = PAGE_SIZE; /* mask off page 0 */ 991 pa_indx = 0; 992 da_indx = 1; 993 phys_avail[pa_indx++] = physmap[0]; 994 phys_avail[pa_indx] = physmap[0]; 995 dump_avail[da_indx] = physmap[0]; 996 pte = CMAP1; 997 998 /* 999 * Get dcons buffer address 1000 */ 1001 if (getenv_quad("dcons.addr", &dcons_addr) == 0 || 1002 getenv_quad("dcons.size", &dcons_size) == 0) 1003 dcons_addr = 0; 1004 1005 /* 1006 * physmap is in bytes, so when converting to page boundaries, 1007 * round up the start address and round down the end address. 1008 */ 1009 for (i = 0; i <= physmap_idx; i += 2) { 1010 vm_paddr_t end; 1011 1012 end = ptoa((vm_paddr_t)Maxmem); 1013 if (physmap[i + 1] < end) 1014 end = trunc_page(physmap[i + 1]); 1015 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) { 1016 int tmp, page_bad, full; 1017 int *ptr = (int *)CADDR1; 1018 1019 full = FALSE; 1020 /* 1021 * block out kernel memory as not available. 1022 */ 1023 if (pa >= 0x100000 && pa < first) 1024 goto do_dump_avail; 1025 1026 /* 1027 * block out dcons buffer 1028 */ 1029 if (dcons_addr > 0 1030 && pa >= trunc_page(dcons_addr) 1031 && pa < dcons_addr + dcons_size) 1032 goto do_dump_avail; 1033 1034 page_bad = FALSE; 1035 1036 /* 1037 * map page into kernel: valid, read/write,non-cacheable 1038 */ 1039 *pte = pa | PG_V | PG_RW | PG_N; 1040 invltlb(); 1041 1042 tmp = *(int *)ptr; 1043 /* 1044 * Test for alternating 1's and 0's 1045 */ 1046 *(volatile int *)ptr = 0xaaaaaaaa; 1047 if (*(volatile int *)ptr != 0xaaaaaaaa) 1048 page_bad = TRUE; 1049 /* 1050 * Test for alternating 0's and 1's 1051 */ 1052 *(volatile int *)ptr = 0x55555555; 1053 if (*(volatile int *)ptr != 0x55555555) 1054 page_bad = TRUE; 1055 /* 1056 * Test for all 1's 1057 */ 1058 *(volatile int *)ptr = 0xffffffff; 1059 if (*(volatile int *)ptr != 0xffffffff) 1060 page_bad = TRUE; 1061 /* 1062 * Test for all 0's 1063 */ 1064 *(volatile int *)ptr = 0x0; 1065 if (*(volatile int *)ptr != 0x0) 1066 page_bad = TRUE; 1067 /* 1068 * Restore original value. 1069 */ 1070 *(int *)ptr = tmp; 1071 1072 /* 1073 * Adjust array of valid/good pages. 1074 */ 1075 if (page_bad == TRUE) 1076 continue; 1077 /* 1078 * If this good page is a continuation of the 1079 * previous set of good pages, then just increase 1080 * the end pointer. Otherwise start a new chunk. 1081 * Note that "end" points one higher than end, 1082 * making the range >= start and < end. 1083 * If we're also doing a speculative memory 1084 * test and we at or past the end, bump up Maxmem 1085 * so that we keep going. The first bad page 1086 * will terminate the loop. 1087 */ 1088 if (phys_avail[pa_indx] == pa) { 1089 phys_avail[pa_indx] += PAGE_SIZE; 1090 } else { 1091 pa_indx++; 1092 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1093 printf( 1094 "Too many holes in the physical address space, giving up\n"); 1095 pa_indx--; 1096 full = TRUE; 1097 goto do_dump_avail; 1098 } 1099 phys_avail[pa_indx++] = pa; /* start */ 1100 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */ 1101 } 1102 physmem++; 1103 do_dump_avail: 1104 if (dump_avail[da_indx] == pa) { 1105 dump_avail[da_indx] += PAGE_SIZE; 1106 } else { 1107 da_indx++; 1108 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1109 da_indx--; 1110 goto do_next; 1111 } 1112 dump_avail[da_indx++] = pa; /* start */ 1113 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */ 1114 } 1115 do_next: 1116 if (full) 1117 break; 1118 } 1119 } 1120 *pte = 0; 1121 invltlb(); 1122 1123 /* 1124 * XXX 1125 * The last chunk must contain at least one page plus the message 1126 * buffer to avoid complicating other code (message buffer address 1127 * calculation, etc.). 1128 */ 1129 while (phys_avail[pa_indx - 1] + PAGE_SIZE + 1130 round_page(MSGBUF_SIZE) >= phys_avail[pa_indx]) { 1131 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1132 phys_avail[pa_indx--] = 0; 1133 phys_avail[pa_indx--] = 0; 1134 } 1135 1136 Maxmem = atop(phys_avail[pa_indx]); 1137 1138 /* Trim off space for the message buffer. */ 1139 phys_avail[pa_indx] -= round_page(MSGBUF_SIZE); 1140 1141 /* Map the message buffer. */ 1142 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE) 1143 pmap_kenter((vm_offset_t)msgbufp + off, phys_avail[pa_indx] + 1144 off); 1145 } 1146 1147 u_int64_t 1148 hammer_time(u_int64_t modulep, u_int64_t physfree) 1149 { 1150 caddr_t kmdp; 1151 int gsel_tss, x; 1152 struct pcpu *pc; 1153 u_int64_t msr; 1154 char *env; 1155 1156 thread0.td_kstack = physfree + KERNBASE; 1157 bzero((void *)thread0.td_kstack, KSTACK_PAGES * PAGE_SIZE); 1158 physfree += KSTACK_PAGES * PAGE_SIZE; 1159 thread0.td_pcb = (struct pcb *) 1160 (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1; 1161 1162 /* 1163 * This may be done better later if it gets more high level 1164 * components in it. If so just link td->td_proc here. 1165 */ 1166 proc_linkup0(&proc0, &thread0); 1167 1168 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE); 1169 preload_bootstrap_relocate(KERNBASE); 1170 kmdp = preload_search_by_type("elf kernel"); 1171 if (kmdp == NULL) 1172 kmdp = preload_search_by_type("elf64 kernel"); 1173 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1174 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE; 1175 #ifdef DDB 1176 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1177 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1178 #endif 1179 1180 /* Init basic tunables, hz etc */ 1181 init_param1(); 1182 1183 /* 1184 * make gdt memory segments 1185 */ 1186 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0]; 1187 1188 for (x = 0; x < NGDT; x++) { 1189 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1)) 1190 ssdtosd(&gdt_segs[x], &gdt[x]); 1191 } 1192 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1193 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1194 1195 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1196 r_gdt.rd_base = (long) gdt; 1197 lgdt(&r_gdt); 1198 pc = &__pcpu[0]; 1199 1200 wrmsr(MSR_FSBASE, 0); /* User value */ 1201 wrmsr(MSR_GSBASE, (u_int64_t)pc); 1202 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1203 1204 pcpu_init(pc, 0, sizeof(struct pcpu)); 1205 PCPU_SET(prvspace, pc); 1206 PCPU_SET(curthread, &thread0); 1207 PCPU_SET(curpcb, thread0.td_pcb); 1208 PCPU_SET(tssp, &common_tss[0]); 1209 PCPU_SET(gs32p, &gdt[GUGS32_SEL]); 1210 1211 /* 1212 * Initialize mutexes. 1213 * 1214 * icu_lock: in order to allow an interrupt to occur in a critical 1215 * section, to set pcpu->ipending (etc...) properly, we 1216 * must be able to get the icu lock, so it can't be 1217 * under witness. 1218 */ 1219 mutex_init(); 1220 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS); 1221 1222 /* exceptions */ 1223 for (x = 0; x < NIDT; x++) 1224 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1225 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1226 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1227 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1); 1228 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1229 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1230 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1231 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1232 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1233 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1234 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1235 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1236 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1237 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1238 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1239 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1240 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1241 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1242 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1243 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1244 1245 r_idt.rd_limit = sizeof(idt0) - 1; 1246 r_idt.rd_base = (long) idt; 1247 lidt(&r_idt); 1248 1249 /* 1250 * Initialize the i8254 before the console so that console 1251 * initialization can use DELAY(). 1252 */ 1253 i8254_init(); 1254 1255 /* 1256 * Initialize the console before we print anything out. 1257 */ 1258 cninit(); 1259 1260 #ifdef DEV_ISA 1261 #ifdef DEV_ATPIC 1262 elcr_probe(); 1263 atpic_startup(); 1264 #else 1265 /* Reset and mask the atpics and leave them shut down. */ 1266 atpic_reset(); 1267 1268 /* 1269 * Point the ICU spurious interrupt vectors at the APIC spurious 1270 * interrupt handler. 1271 */ 1272 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1273 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1274 #endif 1275 #else 1276 #error "have you forgotten the isa device?"; 1277 #endif 1278 1279 kdb_init(); 1280 1281 #ifdef KDB 1282 if (boothowto & RB_KDB) 1283 kdb_enter_why(KDB_WHY_BOOTFLAGS, 1284 "Boot flags requested debugger"); 1285 #endif 1286 1287 identify_cpu(); /* Final stage of CPU initialization */ 1288 initializecpu(); /* Initialize CPU registers */ 1289 1290 /* make an initial tss so cpu can get interrupt stack on syscall! */ 1291 common_tss[0].tss_rsp0 = thread0.td_kstack + \ 1292 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb); 1293 /* Ensure the stack is aligned to 16 bytes */ 1294 common_tss[0].tss_rsp0 &= ~0xFul; 1295 PCPU_SET(rsp0, common_tss[0].tss_rsp0); 1296 1297 /* doublefault stack space, runs on ist1 */ 1298 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)]; 1299 1300 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1301 common_tss[0].tss_iobase = sizeof(struct amd64tss); 1302 1303 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1304 ltr(gsel_tss); 1305 1306 /* Set up the fast syscall stuff */ 1307 msr = rdmsr(MSR_EFER) | EFER_SCE; 1308 wrmsr(MSR_EFER, msr); 1309 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1310 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1311 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1312 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1313 wrmsr(MSR_STAR, msr); 1314 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 1315 1316 getmemsize(kmdp, physfree); 1317 init_param2(physmem); 1318 1319 /* now running on new page tables, configured,and u/iom is accessible */ 1320 1321 msgbufinit(msgbufp, MSGBUF_SIZE); 1322 fpuinit(); 1323 1324 /* transfer to user mode */ 1325 1326 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 1327 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 1328 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 1329 1330 /* setup proc 0's pcb */ 1331 thread0.td_pcb->pcb_flags = 0; /* XXXKSE */ 1332 thread0.td_pcb->pcb_cr3 = KPML4phys; 1333 thread0.td_frame = &proc0_tf; 1334 1335 env = getenv("kernelname"); 1336 if (env != NULL) 1337 strlcpy(kernelname, env, sizeof(kernelname)); 1338 1339 /* Location of kernel stack for locore */ 1340 return ((u_int64_t)thread0.td_pcb); 1341 } 1342 1343 void 1344 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 1345 { 1346 1347 pcpu->pc_acpi_id = 0xffffffff; 1348 } 1349 1350 void 1351 spinlock_enter(void) 1352 { 1353 struct thread *td; 1354 1355 td = curthread; 1356 if (td->td_md.md_spinlock_count == 0) 1357 td->td_md.md_saved_flags = intr_disable(); 1358 td->td_md.md_spinlock_count++; 1359 critical_enter(); 1360 } 1361 1362 void 1363 spinlock_exit(void) 1364 { 1365 struct thread *td; 1366 1367 td = curthread; 1368 critical_exit(); 1369 td->td_md.md_spinlock_count--; 1370 if (td->td_md.md_spinlock_count == 0) 1371 intr_restore(td->td_md.md_saved_flags); 1372 } 1373 1374 /* 1375 * Construct a PCB from a trapframe. This is called from kdb_trap() where 1376 * we want to start a backtrace from the function that caused us to enter 1377 * the debugger. We have the context in the trapframe, but base the trace 1378 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 1379 * enough for a backtrace. 1380 */ 1381 void 1382 makectx(struct trapframe *tf, struct pcb *pcb) 1383 { 1384 1385 pcb->pcb_r12 = tf->tf_r12; 1386 pcb->pcb_r13 = tf->tf_r13; 1387 pcb->pcb_r14 = tf->tf_r14; 1388 pcb->pcb_r15 = tf->tf_r15; 1389 pcb->pcb_rbp = tf->tf_rbp; 1390 pcb->pcb_rbx = tf->tf_rbx; 1391 pcb->pcb_rip = tf->tf_rip; 1392 pcb->pcb_rsp = (ISPL(tf->tf_cs)) ? tf->tf_rsp : (long)(tf + 1) - 8; 1393 } 1394 1395 int 1396 ptrace_set_pc(struct thread *td, unsigned long addr) 1397 { 1398 td->td_frame->tf_rip = addr; 1399 return (0); 1400 } 1401 1402 int 1403 ptrace_single_step(struct thread *td) 1404 { 1405 td->td_frame->tf_rflags |= PSL_T; 1406 return (0); 1407 } 1408 1409 int 1410 ptrace_clear_single_step(struct thread *td) 1411 { 1412 td->td_frame->tf_rflags &= ~PSL_T; 1413 return (0); 1414 } 1415 1416 int 1417 fill_regs(struct thread *td, struct reg *regs) 1418 { 1419 struct trapframe *tp; 1420 1421 tp = td->td_frame; 1422 regs->r_r15 = tp->tf_r15; 1423 regs->r_r14 = tp->tf_r14; 1424 regs->r_r13 = tp->tf_r13; 1425 regs->r_r12 = tp->tf_r12; 1426 regs->r_r11 = tp->tf_r11; 1427 regs->r_r10 = tp->tf_r10; 1428 regs->r_r9 = tp->tf_r9; 1429 regs->r_r8 = tp->tf_r8; 1430 regs->r_rdi = tp->tf_rdi; 1431 regs->r_rsi = tp->tf_rsi; 1432 regs->r_rbp = tp->tf_rbp; 1433 regs->r_rbx = tp->tf_rbx; 1434 regs->r_rdx = tp->tf_rdx; 1435 regs->r_rcx = tp->tf_rcx; 1436 regs->r_rax = tp->tf_rax; 1437 regs->r_rip = tp->tf_rip; 1438 regs->r_cs = tp->tf_cs; 1439 regs->r_rflags = tp->tf_rflags; 1440 regs->r_rsp = tp->tf_rsp; 1441 regs->r_ss = tp->tf_ss; 1442 return (0); 1443 } 1444 1445 int 1446 set_regs(struct thread *td, struct reg *regs) 1447 { 1448 struct trapframe *tp; 1449 register_t rflags; 1450 1451 tp = td->td_frame; 1452 rflags = regs->r_rflags & 0xffffffff; 1453 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs)) 1454 return (EINVAL); 1455 tp->tf_r15 = regs->r_r15; 1456 tp->tf_r14 = regs->r_r14; 1457 tp->tf_r13 = regs->r_r13; 1458 tp->tf_r12 = regs->r_r12; 1459 tp->tf_r11 = regs->r_r11; 1460 tp->tf_r10 = regs->r_r10; 1461 tp->tf_r9 = regs->r_r9; 1462 tp->tf_r8 = regs->r_r8; 1463 tp->tf_rdi = regs->r_rdi; 1464 tp->tf_rsi = regs->r_rsi; 1465 tp->tf_rbp = regs->r_rbp; 1466 tp->tf_rbx = regs->r_rbx; 1467 tp->tf_rdx = regs->r_rdx; 1468 tp->tf_rcx = regs->r_rcx; 1469 tp->tf_rax = regs->r_rax; 1470 tp->tf_rip = regs->r_rip; 1471 tp->tf_cs = regs->r_cs; 1472 tp->tf_rflags = rflags; 1473 tp->tf_rsp = regs->r_rsp; 1474 tp->tf_ss = regs->r_ss; 1475 td->td_pcb->pcb_flags |= PCB_FULLCTX; 1476 return (0); 1477 } 1478 1479 /* XXX check all this stuff! */ 1480 /* externalize from sv_xmm */ 1481 static void 1482 fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs) 1483 { 1484 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 1485 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1486 int i; 1487 1488 /* pcb -> fpregs */ 1489 bzero(fpregs, sizeof(*fpregs)); 1490 1491 /* FPU control/status */ 1492 penv_fpreg->en_cw = penv_xmm->en_cw; 1493 penv_fpreg->en_sw = penv_xmm->en_sw; 1494 penv_fpreg->en_tw = penv_xmm->en_tw; 1495 penv_fpreg->en_opcode = penv_xmm->en_opcode; 1496 penv_fpreg->en_rip = penv_xmm->en_rip; 1497 penv_fpreg->en_rdp = penv_xmm->en_rdp; 1498 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr; 1499 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask; 1500 1501 /* FPU registers */ 1502 for (i = 0; i < 8; ++i) 1503 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10); 1504 1505 /* SSE registers */ 1506 for (i = 0; i < 16; ++i) 1507 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16); 1508 } 1509 1510 /* internalize from fpregs into sv_xmm */ 1511 static void 1512 set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm) 1513 { 1514 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1515 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 1516 int i; 1517 1518 /* fpregs -> pcb */ 1519 /* FPU control/status */ 1520 penv_xmm->en_cw = penv_fpreg->en_cw; 1521 penv_xmm->en_sw = penv_fpreg->en_sw; 1522 penv_xmm->en_tw = penv_fpreg->en_tw; 1523 penv_xmm->en_opcode = penv_fpreg->en_opcode; 1524 penv_xmm->en_rip = penv_fpreg->en_rip; 1525 penv_xmm->en_rdp = penv_fpreg->en_rdp; 1526 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr; 1527 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask; 1528 1529 /* FPU registers */ 1530 for (i = 0; i < 8; ++i) 1531 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10); 1532 1533 /* SSE registers */ 1534 for (i = 0; i < 16; ++i) 1535 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16); 1536 } 1537 1538 /* externalize from td->pcb */ 1539 int 1540 fill_fpregs(struct thread *td, struct fpreg *fpregs) 1541 { 1542 1543 fill_fpregs_xmm(&td->td_pcb->pcb_save, fpregs); 1544 return (0); 1545 } 1546 1547 /* internalize to td->pcb */ 1548 int 1549 set_fpregs(struct thread *td, struct fpreg *fpregs) 1550 { 1551 1552 set_fpregs_xmm(fpregs, &td->td_pcb->pcb_save); 1553 return (0); 1554 } 1555 1556 /* 1557 * Get machine context. 1558 */ 1559 int 1560 get_mcontext(struct thread *td, mcontext_t *mcp, int flags) 1561 { 1562 struct trapframe *tp; 1563 1564 tp = td->td_frame; 1565 PROC_LOCK(curthread->td_proc); 1566 mcp->mc_onstack = sigonstack(tp->tf_rsp); 1567 PROC_UNLOCK(curthread->td_proc); 1568 mcp->mc_r15 = tp->tf_r15; 1569 mcp->mc_r14 = tp->tf_r14; 1570 mcp->mc_r13 = tp->tf_r13; 1571 mcp->mc_r12 = tp->tf_r12; 1572 mcp->mc_r11 = tp->tf_r11; 1573 mcp->mc_r10 = tp->tf_r10; 1574 mcp->mc_r9 = tp->tf_r9; 1575 mcp->mc_r8 = tp->tf_r8; 1576 mcp->mc_rdi = tp->tf_rdi; 1577 mcp->mc_rsi = tp->tf_rsi; 1578 mcp->mc_rbp = tp->tf_rbp; 1579 mcp->mc_rbx = tp->tf_rbx; 1580 mcp->mc_rcx = tp->tf_rcx; 1581 mcp->mc_rflags = tp->tf_rflags; 1582 if (flags & GET_MC_CLEAR_RET) { 1583 mcp->mc_rax = 0; 1584 mcp->mc_rdx = 0; 1585 mcp->mc_rflags &= ~PSL_C; 1586 } else { 1587 mcp->mc_rax = tp->tf_rax; 1588 mcp->mc_rdx = tp->tf_rdx; 1589 } 1590 mcp->mc_rip = tp->tf_rip; 1591 mcp->mc_cs = tp->tf_cs; 1592 mcp->mc_rsp = tp->tf_rsp; 1593 mcp->mc_ss = tp->tf_ss; 1594 mcp->mc_len = sizeof(*mcp); 1595 get_fpcontext(td, mcp); 1596 return (0); 1597 } 1598 1599 /* 1600 * Set machine context. 1601 * 1602 * However, we don't set any but the user modifiable flags, and we won't 1603 * touch the cs selector. 1604 */ 1605 int 1606 set_mcontext(struct thread *td, const mcontext_t *mcp) 1607 { 1608 struct trapframe *tp; 1609 long rflags; 1610 int ret; 1611 1612 tp = td->td_frame; 1613 if (mcp->mc_len != sizeof(*mcp)) 1614 return (EINVAL); 1615 rflags = (mcp->mc_rflags & PSL_USERCHANGE) | 1616 (tp->tf_rflags & ~PSL_USERCHANGE); 1617 ret = set_fpcontext(td, mcp); 1618 if (ret != 0) 1619 return (ret); 1620 tp->tf_r15 = mcp->mc_r15; 1621 tp->tf_r14 = mcp->mc_r14; 1622 tp->tf_r13 = mcp->mc_r13; 1623 tp->tf_r12 = mcp->mc_r12; 1624 tp->tf_r11 = mcp->mc_r11; 1625 tp->tf_r10 = mcp->mc_r10; 1626 tp->tf_r9 = mcp->mc_r9; 1627 tp->tf_r8 = mcp->mc_r8; 1628 tp->tf_rdi = mcp->mc_rdi; 1629 tp->tf_rsi = mcp->mc_rsi; 1630 tp->tf_rbp = mcp->mc_rbp; 1631 tp->tf_rbx = mcp->mc_rbx; 1632 tp->tf_rdx = mcp->mc_rdx; 1633 tp->tf_rcx = mcp->mc_rcx; 1634 tp->tf_rax = mcp->mc_rax; 1635 tp->tf_rip = mcp->mc_rip; 1636 tp->tf_rflags = rflags; 1637 tp->tf_rsp = mcp->mc_rsp; 1638 tp->tf_ss = mcp->mc_ss; 1639 td->td_pcb->pcb_flags |= PCB_FULLCTX; 1640 return (0); 1641 } 1642 1643 static void 1644 get_fpcontext(struct thread *td, mcontext_t *mcp) 1645 { 1646 1647 mcp->mc_ownedfp = fpugetregs(td, (struct savefpu *)&mcp->mc_fpstate); 1648 mcp->mc_fpformat = fpuformat(); 1649 } 1650 1651 static int 1652 set_fpcontext(struct thread *td, const mcontext_t *mcp) 1653 { 1654 struct savefpu *fpstate; 1655 1656 if (mcp->mc_fpformat == _MC_FPFMT_NODEV) 1657 return (0); 1658 else if (mcp->mc_fpformat != _MC_FPFMT_XMM) 1659 return (EINVAL); 1660 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) 1661 /* We don't care what state is left in the FPU or PCB. */ 1662 fpstate_drop(td); 1663 else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || 1664 mcp->mc_ownedfp == _MC_FPOWNED_PCB) { 1665 /* 1666 * XXX we violate the dubious requirement that fpusetregs() 1667 * be called with interrupts disabled. 1668 * XXX obsolete on trap-16 systems? 1669 */ 1670 fpstate = (struct savefpu *)&mcp->mc_fpstate; 1671 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask; 1672 fpusetregs(td, fpstate); 1673 } else 1674 return (EINVAL); 1675 return (0); 1676 } 1677 1678 void 1679 fpstate_drop(struct thread *td) 1680 { 1681 register_t s; 1682 1683 s = intr_disable(); 1684 if (PCPU_GET(fpcurthread) == td) 1685 fpudrop(); 1686 /* 1687 * XXX force a full drop of the fpu. The above only drops it if we 1688 * owned it. 1689 * 1690 * XXX I don't much like fpugetregs()'s semantics of doing a full 1691 * drop. Dropping only to the pcb matches fnsave's behaviour. 1692 * We only need to drop to !PCB_INITDONE in sendsig(). But 1693 * sendsig() is the only caller of fpugetregs()... perhaps we just 1694 * have too many layers. 1695 */ 1696 curthread->td_pcb->pcb_flags &= ~PCB_FPUINITDONE; 1697 intr_restore(s); 1698 } 1699 1700 int 1701 fill_dbregs(struct thread *td, struct dbreg *dbregs) 1702 { 1703 struct pcb *pcb; 1704 1705 if (td == NULL) { 1706 dbregs->dr[0] = rdr0(); 1707 dbregs->dr[1] = rdr1(); 1708 dbregs->dr[2] = rdr2(); 1709 dbregs->dr[3] = rdr3(); 1710 dbregs->dr[6] = rdr6(); 1711 dbregs->dr[7] = rdr7(); 1712 } else { 1713 pcb = td->td_pcb; 1714 dbregs->dr[0] = pcb->pcb_dr0; 1715 dbregs->dr[1] = pcb->pcb_dr1; 1716 dbregs->dr[2] = pcb->pcb_dr2; 1717 dbregs->dr[3] = pcb->pcb_dr3; 1718 dbregs->dr[6] = pcb->pcb_dr6; 1719 dbregs->dr[7] = pcb->pcb_dr7; 1720 } 1721 dbregs->dr[4] = 0; 1722 dbregs->dr[5] = 0; 1723 dbregs->dr[8] = 0; 1724 dbregs->dr[9] = 0; 1725 dbregs->dr[10] = 0; 1726 dbregs->dr[11] = 0; 1727 dbregs->dr[12] = 0; 1728 dbregs->dr[13] = 0; 1729 dbregs->dr[14] = 0; 1730 dbregs->dr[15] = 0; 1731 return (0); 1732 } 1733 1734 int 1735 set_dbregs(struct thread *td, struct dbreg *dbregs) 1736 { 1737 struct pcb *pcb; 1738 int i; 1739 1740 if (td == NULL) { 1741 load_dr0(dbregs->dr[0]); 1742 load_dr1(dbregs->dr[1]); 1743 load_dr2(dbregs->dr[2]); 1744 load_dr3(dbregs->dr[3]); 1745 load_dr6(dbregs->dr[6]); 1746 load_dr7(dbregs->dr[7]); 1747 } else { 1748 /* 1749 * Don't let an illegal value for dr7 get set. Specifically, 1750 * check for undefined settings. Setting these bit patterns 1751 * result in undefined behaviour and can lead to an unexpected 1752 * TRCTRAP or a general protection fault right here. 1753 * Upper bits of dr6 and dr7 must not be set 1754 */ 1755 for (i = 0; i < 4; i++) { 1756 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02) 1757 return (EINVAL); 1758 if (td->td_frame->tf_cs == _ucode32sel && 1759 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8) 1760 return (EINVAL); 1761 } 1762 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 || 1763 (dbregs->dr[7] & 0xffffffff00000000ul) != 0) 1764 return (EINVAL); 1765 1766 pcb = td->td_pcb; 1767 1768 /* 1769 * Don't let a process set a breakpoint that is not within the 1770 * process's address space. If a process could do this, it 1771 * could halt the system by setting a breakpoint in the kernel 1772 * (if ddb was enabled). Thus, we need to check to make sure 1773 * that no breakpoints are being enabled for addresses outside 1774 * process's address space. 1775 * 1776 * XXX - what about when the watched area of the user's 1777 * address space is written into from within the kernel 1778 * ... wouldn't that still cause a breakpoint to be generated 1779 * from within kernel mode? 1780 */ 1781 1782 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) { 1783 /* dr0 is enabled */ 1784 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS) 1785 return (EINVAL); 1786 } 1787 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) { 1788 /* dr1 is enabled */ 1789 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS) 1790 return (EINVAL); 1791 } 1792 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) { 1793 /* dr2 is enabled */ 1794 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS) 1795 return (EINVAL); 1796 } 1797 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) { 1798 /* dr3 is enabled */ 1799 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS) 1800 return (EINVAL); 1801 } 1802 1803 pcb->pcb_dr0 = dbregs->dr[0]; 1804 pcb->pcb_dr1 = dbregs->dr[1]; 1805 pcb->pcb_dr2 = dbregs->dr[2]; 1806 pcb->pcb_dr3 = dbregs->dr[3]; 1807 pcb->pcb_dr6 = dbregs->dr[6]; 1808 pcb->pcb_dr7 = dbregs->dr[7]; 1809 1810 pcb->pcb_flags |= PCB_DBREGS; 1811 } 1812 1813 return (0); 1814 } 1815 1816 void 1817 reset_dbregs(void) 1818 { 1819 1820 load_dr7(0); /* Turn off the control bits first */ 1821 load_dr0(0); 1822 load_dr1(0); 1823 load_dr2(0); 1824 load_dr3(0); 1825 load_dr6(0); 1826 } 1827 1828 /* 1829 * Return > 0 if a hardware breakpoint has been hit, and the 1830 * breakpoint was in user space. Return 0, otherwise. 1831 */ 1832 int 1833 user_dbreg_trap(void) 1834 { 1835 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 1836 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 1837 int nbp; /* number of breakpoints that triggered */ 1838 caddr_t addr[4]; /* breakpoint addresses */ 1839 int i; 1840 1841 dr7 = rdr7(); 1842 if ((dr7 & 0x000000ff) == 0) { 1843 /* 1844 * all GE and LE bits in the dr7 register are zero, 1845 * thus the trap couldn't have been caused by the 1846 * hardware debug registers 1847 */ 1848 return 0; 1849 } 1850 1851 nbp = 0; 1852 dr6 = rdr6(); 1853 bp = dr6 & 0x0000000f; 1854 1855 if (!bp) { 1856 /* 1857 * None of the breakpoint bits are set meaning this 1858 * trap was not caused by any of the debug registers 1859 */ 1860 return 0; 1861 } 1862 1863 /* 1864 * at least one of the breakpoints were hit, check to see 1865 * which ones and if any of them are user space addresses 1866 */ 1867 1868 if (bp & 0x01) { 1869 addr[nbp++] = (caddr_t)rdr0(); 1870 } 1871 if (bp & 0x02) { 1872 addr[nbp++] = (caddr_t)rdr1(); 1873 } 1874 if (bp & 0x04) { 1875 addr[nbp++] = (caddr_t)rdr2(); 1876 } 1877 if (bp & 0x08) { 1878 addr[nbp++] = (caddr_t)rdr3(); 1879 } 1880 1881 for (i = 0; i < nbp; i++) { 1882 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) { 1883 /* 1884 * addr[i] is in user space 1885 */ 1886 return nbp; 1887 } 1888 } 1889 1890 /* 1891 * None of the breakpoints are in user space. 1892 */ 1893 return 0; 1894 } 1895 1896 #ifdef KDB 1897 1898 /* 1899 * Provide inb() and outb() as functions. They are normally only 1900 * available as macros calling inlined functions, thus cannot be 1901 * called from the debugger. 1902 * 1903 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined. 1904 */ 1905 1906 #undef inb 1907 #undef outb 1908 1909 /* silence compiler warnings */ 1910 u_char inb(u_int); 1911 void outb(u_int, u_char); 1912 1913 u_char 1914 inb(u_int port) 1915 { 1916 u_char data; 1917 /* 1918 * We use %%dx and not %1 here because i/o is done at %dx and not at 1919 * %edx, while gcc generates inferior code (movw instead of movl) 1920 * if we tell it to load (u_short) port. 1921 */ 1922 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port)); 1923 return (data); 1924 } 1925 1926 void 1927 outb(u_int port, u_char data) 1928 { 1929 u_char al; 1930 /* 1931 * Use an unnecessary assignment to help gcc's register allocator. 1932 * This make a large difference for gcc-1.40 and a tiny difference 1933 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for 1934 * best results. gcc-2.6.0 can't handle this. 1935 */ 1936 al = data; 1937 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port)); 1938 } 1939 1940 #endif /* KDB */
Cache object: a60d8af618da74651130deef57019698
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