Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/amd64/amd64/machdep.c
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1 /*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD: releng/8.1/sys/amd64/amd64/machdep.c 206890 2010-04-20 08:19:43Z kib $"); 43 44 #include "opt_atalk.h" 45 #include "opt_atpic.h" 46 #include "opt_compat.h" 47 #include "opt_cpu.h" 48 #include "opt_ddb.h" 49 #include "opt_inet.h" 50 #include "opt_ipx.h" 51 #include "opt_isa.h" 52 #include "opt_kstack_pages.h" 53 #include "opt_maxmem.h" 54 #include "opt_msgbuf.h" 55 #include "opt_perfmon.h" 56 #include "opt_sched.h" 57 58 #include <sys/param.h> 59 #include <sys/proc.h> 60 #include <sys/systm.h> 61 #include <sys/bio.h> 62 #include <sys/buf.h> 63 #include <sys/bus.h> 64 #include <sys/callout.h> 65 #include <sys/cons.h> 66 #include <sys/cpu.h> 67 #include <sys/eventhandler.h> 68 #include <sys/exec.h> 69 #include <sys/imgact.h> 70 #include <sys/kdb.h> 71 #include <sys/kernel.h> 72 #include <sys/ktr.h> 73 #include <sys/linker.h> 74 #include <sys/lock.h> 75 #include <sys/malloc.h> 76 #include <sys/memrange.h> 77 #include <sys/msgbuf.h> 78 #include <sys/mutex.h> 79 #include <sys/pcpu.h> 80 #include <sys/ptrace.h> 81 #include <sys/reboot.h> 82 #include <sys/sched.h> 83 #include <sys/signalvar.h> 84 #include <sys/sysctl.h> 85 #include <sys/sysent.h> 86 #include <sys/sysproto.h> 87 #include <sys/ucontext.h> 88 #include <sys/vmmeter.h> 89 90 #include <vm/vm.h> 91 #include <vm/vm_extern.h> 92 #include <vm/vm_kern.h> 93 #include <vm/vm_page.h> 94 #include <vm/vm_map.h> 95 #include <vm/vm_object.h> 96 #include <vm/vm_pager.h> 97 #include <vm/vm_param.h> 98 99 #ifdef DDB 100 #ifndef KDB 101 #error KDB must be enabled in order for DDB to work! 102 #endif 103 #include <ddb/ddb.h> 104 #include <ddb/db_sym.h> 105 #endif 106 107 #include <net/netisr.h> 108 109 #include <machine/clock.h> 110 #include <machine/cpu.h> 111 #include <machine/cputypes.h> 112 #include <machine/intr_machdep.h> 113 #include <machine/mca.h> 114 #include <machine/md_var.h> 115 #include <machine/metadata.h> 116 #include <machine/pc/bios.h> 117 #include <machine/pcb.h> 118 #include <machine/proc.h> 119 #include <machine/reg.h> 120 #include <machine/sigframe.h> 121 #include <machine/specialreg.h> 122 #ifdef PERFMON 123 #include <machine/perfmon.h> 124 #endif 125 #include <machine/tss.h> 126 #ifdef SMP 127 #include <machine/smp.h> 128 #endif 129 130 #ifdef DEV_ATPIC 131 #include <amd64/isa/icu.h> 132 #else 133 #include <machine/apicvar.h> 134 #endif 135 136 #include <isa/isareg.h> 137 #include <isa/rtc.h> 138 139 /* Sanity check for __curthread() */ 140 CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); 141 142 extern u_int64_t hammer_time(u_int64_t, u_int64_t); 143 144 extern void printcpuinfo(void); /* XXX header file */ 145 extern void identify_cpu(void); 146 extern void panicifcpuunsupported(void); 147 148 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 149 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 150 151 static void cpu_startup(void *); 152 static void get_fpcontext(struct thread *td, mcontext_t *mcp); 153 static int set_fpcontext(struct thread *td, const mcontext_t *mcp); 154 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 155 156 #ifdef DDB 157 extern vm_offset_t ksym_start, ksym_end; 158 #endif 159 160 /* Intel ICH registers */ 161 #define ICH_PMBASE 0x400 162 #define ICH_SMI_EN ICH_PMBASE + 0x30 163 164 int _udatasel, _ucodesel, _ucode32sel, _ufssel, _ugssel; 165 166 int cold = 1; 167 168 long Maxmem = 0; 169 long realmem = 0; 170 171 /* 172 * The number of PHYSMAP entries must be one less than the number of 173 * PHYSSEG entries because the PHYSMAP entry that spans the largest 174 * physical address that is accessible by ISA DMA is split into two 175 * PHYSSEG entries. 176 */ 177 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 178 179 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 180 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 181 182 /* must be 2 less so 0 0 can signal end of chunks */ 183 #define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2) 184 #define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2) 185 186 struct kva_md_info kmi; 187 188 static struct trapframe proc0_tf; 189 struct region_descriptor r_gdt, r_idt; 190 191 struct pcpu __pcpu[MAXCPU]; 192 193 struct mtx icu_lock; 194 195 struct mem_range_softc mem_range_softc; 196 197 struct mtx dt_lock; /* lock for GDT and LDT */ 198 199 static void 200 cpu_startup(dummy) 201 void *dummy; 202 { 203 uintmax_t memsize; 204 char *sysenv; 205 206 /* 207 * On MacBooks, we need to disallow the legacy USB circuit to 208 * generate an SMI# because this can cause several problems, 209 * namely: incorrect CPU frequency detection and failure to 210 * start the APs. 211 * We do this by disabling a bit in the SMI_EN (SMI Control and 212 * Enable register) of the Intel ICH LPC Interface Bridge. 213 */ 214 sysenv = getenv("smbios.system.product"); 215 if (sysenv != NULL) { 216 if (strncmp(sysenv, "MacBook1,1", 10) == 0 || 217 strncmp(sysenv, "MacBook3,1", 10) == 0 || 218 strncmp(sysenv, "MacBookPro1,1", 13) == 0 || 219 strncmp(sysenv, "MacBookPro1,2", 13) == 0 || 220 strncmp(sysenv, "MacBookPro3,1", 13) == 0 || 221 strncmp(sysenv, "Macmini1,1", 10) == 0) { 222 if (bootverbose) 223 printf("Disabling LEGACY_USB_EN bit on " 224 "Intel ICH.\n"); 225 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8); 226 } 227 freeenv(sysenv); 228 } 229 230 /* 231 * Good {morning,afternoon,evening,night}. 232 */ 233 startrtclock(); 234 printcpuinfo(); 235 panicifcpuunsupported(); 236 #ifdef PERFMON 237 perfmon_init(); 238 #endif 239 realmem = Maxmem; 240 241 /* 242 * Display physical memory if SMBIOS reports reasonable amount. 243 */ 244 memsize = 0; 245 sysenv = getenv("smbios.memory.enabled"); 246 if (sysenv != NULL) { 247 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10; 248 freeenv(sysenv); 249 } 250 if (memsize < ptoa((uintmax_t)cnt.v_free_count)) 251 memsize = ptoa((uintmax_t)Maxmem); 252 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20); 253 254 /* 255 * Display any holes after the first chunk of extended memory. 256 */ 257 if (bootverbose) { 258 int indx; 259 260 printf("Physical memory chunk(s):\n"); 261 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 262 vm_paddr_t size; 263 264 size = phys_avail[indx + 1] - phys_avail[indx]; 265 printf( 266 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", 267 (uintmax_t)phys_avail[indx], 268 (uintmax_t)phys_avail[indx + 1] - 1, 269 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE); 270 } 271 } 272 273 vm_ksubmap_init(&kmi); 274 275 printf("avail memory = %ju (%ju MB)\n", 276 ptoa((uintmax_t)cnt.v_free_count), 277 ptoa((uintmax_t)cnt.v_free_count) / 1048576); 278 279 /* 280 * Set up buffers, so they can be used to read disk labels. 281 */ 282 bufinit(); 283 vm_pager_bufferinit(); 284 285 cpu_setregs(); 286 mca_init(); 287 } 288 289 /* 290 * Send an interrupt to process. 291 * 292 * Stack is set up to allow sigcode stored 293 * at top to call routine, followed by call 294 * to sigreturn routine below. After sigreturn 295 * resets the signal mask, the stack, and the 296 * frame pointer, it returns to the user 297 * specified pc, psl. 298 */ 299 void 300 sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask) 301 { 302 struct sigframe sf, *sfp; 303 struct proc *p; 304 struct thread *td; 305 struct sigacts *psp; 306 char *sp; 307 struct trapframe *regs; 308 int sig; 309 int oonstack; 310 311 td = curthread; 312 p = td->td_proc; 313 PROC_LOCK_ASSERT(p, MA_OWNED); 314 sig = ksi->ksi_signo; 315 psp = p->p_sigacts; 316 mtx_assert(&psp->ps_mtx, MA_OWNED); 317 regs = td->td_frame; 318 oonstack = sigonstack(regs->tf_rsp); 319 320 /* Save user context. */ 321 bzero(&sf, sizeof(sf)); 322 sf.sf_uc.uc_sigmask = *mask; 323 sf.sf_uc.uc_stack = td->td_sigstk; 324 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) 325 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE; 326 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0; 327 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs)); 328 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */ 329 get_fpcontext(td, &sf.sf_uc.uc_mcontext); 330 fpstate_drop(td); 331 sf.sf_uc.uc_mcontext.mc_fsbase = td->td_pcb->pcb_fsbase; 332 sf.sf_uc.uc_mcontext.mc_gsbase = td->td_pcb->pcb_gsbase; 333 334 /* Allocate space for the signal handler context. */ 335 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack && 336 SIGISMEMBER(psp->ps_sigonstack, sig)) { 337 sp = td->td_sigstk.ss_sp + 338 td->td_sigstk.ss_size - sizeof(struct sigframe); 339 #if defined(COMPAT_43) 340 td->td_sigstk.ss_flags |= SS_ONSTACK; 341 #endif 342 } else 343 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128; 344 /* Align to 16 bytes. */ 345 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul); 346 347 /* Translate the signal if appropriate. */ 348 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize) 349 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 350 351 /* Build the argument list for the signal handler. */ 352 regs->tf_rdi = sig; /* arg 1 in %rdi */ 353 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */ 354 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 355 /* Signal handler installed with SA_SIGINFO. */ 356 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */ 357 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 358 359 /* Fill in POSIX parts */ 360 sf.sf_si = ksi->ksi_info; 361 sf.sf_si.si_signo = sig; /* maybe a translated signal */ 362 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 363 } else { 364 /* Old FreeBSD-style arguments. */ 365 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */ 366 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 367 sf.sf_ahu.sf_handler = catcher; 368 } 369 mtx_unlock(&psp->ps_mtx); 370 PROC_UNLOCK(p); 371 372 /* 373 * Copy the sigframe out to the user's stack. 374 */ 375 if (copyout(&sf, sfp, sizeof(*sfp)) != 0) { 376 #ifdef DEBUG 377 printf("process %ld has trashed its stack\n", (long)p->p_pid); 378 #endif 379 PROC_LOCK(p); 380 sigexit(td, SIGILL); 381 } 382 383 regs->tf_rsp = (long)sfp; 384 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode); 385 regs->tf_rflags &= ~(PSL_T | PSL_D); 386 regs->tf_cs = _ucodesel; 387 regs->tf_ds = _udatasel; 388 regs->tf_es = _udatasel; 389 regs->tf_fs = _ufssel; 390 regs->tf_gs = _ugssel; 391 regs->tf_flags = TF_HASSEGS; 392 td->td_pcb->pcb_full_iret = 1; 393 PROC_LOCK(p); 394 mtx_lock(&psp->ps_mtx); 395 } 396 397 /* 398 * System call to cleanup state after a signal 399 * has been taken. Reset signal mask and 400 * stack state from context left by sendsig (above). 401 * Return to previous pc and psl as specified by 402 * context left by sendsig. Check carefully to 403 * make sure that the user has not modified the 404 * state to gain improper privileges. 405 * 406 * MPSAFE 407 */ 408 int 409 sigreturn(td, uap) 410 struct thread *td; 411 struct sigreturn_args /* { 412 const struct __ucontext *sigcntxp; 413 } */ *uap; 414 { 415 ucontext_t uc; 416 struct proc *p = td->td_proc; 417 struct trapframe *regs; 418 ucontext_t *ucp; 419 long rflags; 420 int cs, error, ret; 421 ksiginfo_t ksi; 422 423 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 424 if (error != 0) { 425 uprintf("pid %d (%s): sigreturn copyin failed\n", 426 p->p_pid, td->td_name); 427 return (error); 428 } 429 ucp = &uc; 430 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) { 431 uprintf("pid %d (%s): sigreturn mc_flags %x\n", p->p_pid, 432 td->td_name, ucp->uc_mcontext.mc_flags); 433 return (EINVAL); 434 } 435 regs = td->td_frame; 436 rflags = ucp->uc_mcontext.mc_rflags; 437 /* 438 * Don't allow users to change privileged or reserved flags. 439 */ 440 /* 441 * XXX do allow users to change the privileged flag PSL_RF. 442 * The cpu sets PSL_RF in tf_rflags for faults. Debuggers 443 * should sometimes set it there too. tf_rflags is kept in 444 * the signal context during signal handling and there is no 445 * other place to remember it, so the PSL_RF bit may be 446 * corrupted by the signal handler without us knowing. 447 * Corruption of the PSL_RF bit at worst causes one more or 448 * one less debugger trap, so allowing it is fairly harmless. 449 */ 450 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) { 451 uprintf("pid %d (%s): sigreturn rflags = 0x%lx\n", p->p_pid, 452 td->td_name, rflags); 453 return (EINVAL); 454 } 455 456 /* 457 * Don't allow users to load a valid privileged %cs. Let the 458 * hardware check for invalid selectors, excess privilege in 459 * other selectors, invalid %eip's and invalid %esp's. 460 */ 461 cs = ucp->uc_mcontext.mc_cs; 462 if (!CS_SECURE(cs)) { 463 uprintf("pid %d (%s): sigreturn cs = 0x%x\n", p->p_pid, 464 td->td_name, cs); 465 ksiginfo_init_trap(&ksi); 466 ksi.ksi_signo = SIGBUS; 467 ksi.ksi_code = BUS_OBJERR; 468 ksi.ksi_trapno = T_PROTFLT; 469 ksi.ksi_addr = (void *)regs->tf_rip; 470 trapsignal(td, &ksi); 471 return (EINVAL); 472 } 473 474 ret = set_fpcontext(td, &ucp->uc_mcontext); 475 if (ret != 0) { 476 uprintf("pid %d (%s): sigreturn set_fpcontext err %d\n", 477 p->p_pid, td->td_name, ret); 478 return (ret); 479 } 480 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs)); 481 td->td_pcb->pcb_fsbase = ucp->uc_mcontext.mc_fsbase; 482 td->td_pcb->pcb_gsbase = ucp->uc_mcontext.mc_gsbase; 483 484 #if defined(COMPAT_43) 485 if (ucp->uc_mcontext.mc_onstack & 1) 486 td->td_sigstk.ss_flags |= SS_ONSTACK; 487 else 488 td->td_sigstk.ss_flags &= ~SS_ONSTACK; 489 #endif 490 491 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0); 492 td->td_pcb->pcb_flags |= PCB_FULLCTX; 493 td->td_pcb->pcb_full_iret = 1; 494 return (EJUSTRETURN); 495 } 496 497 #ifdef COMPAT_FREEBSD4 498 int 499 freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap) 500 { 501 502 return sigreturn(td, (struct sigreturn_args *)uap); 503 } 504 #endif 505 506 507 /* 508 * Machine dependent boot() routine 509 * 510 * I haven't seen anything to put here yet 511 * Possibly some stuff might be grafted back here from boot() 512 */ 513 void 514 cpu_boot(int howto) 515 { 516 } 517 518 /* 519 * Flush the D-cache for non-DMA I/O so that the I-cache can 520 * be made coherent later. 521 */ 522 void 523 cpu_flush_dcache(void *ptr, size_t len) 524 { 525 /* Not applicable */ 526 } 527 528 /* Get current clock frequency for the given cpu id. */ 529 int 530 cpu_est_clockrate(int cpu_id, uint64_t *rate) 531 { 532 register_t reg; 533 uint64_t tsc1, tsc2; 534 535 if (pcpu_find(cpu_id) == NULL || rate == NULL) 536 return (EINVAL); 537 538 /* If we're booting, trust the rate calibrated moments ago. */ 539 if (cold) { 540 *rate = tsc_freq; 541 return (0); 542 } 543 544 #ifdef SMP 545 /* Schedule ourselves on the indicated cpu. */ 546 thread_lock(curthread); 547 sched_bind(curthread, cpu_id); 548 thread_unlock(curthread); 549 #endif 550 551 /* Calibrate by measuring a short delay. */ 552 reg = intr_disable(); 553 tsc1 = rdtsc(); 554 DELAY(1000); 555 tsc2 = rdtsc(); 556 intr_restore(reg); 557 558 #ifdef SMP 559 thread_lock(curthread); 560 sched_unbind(curthread); 561 thread_unlock(curthread); 562 #endif 563 564 /* 565 * Calculate the difference in readings, convert to Mhz, and 566 * subtract 0.5% of the total. Empirical testing has shown that 567 * overhead in DELAY() works out to approximately this value. 568 */ 569 tsc2 -= tsc1; 570 *rate = tsc2 * 1000 - tsc2 * 5; 571 return (0); 572 } 573 574 /* 575 * Shutdown the CPU as much as possible 576 */ 577 void 578 cpu_halt(void) 579 { 580 for (;;) 581 __asm__ ("hlt"); 582 } 583 584 void (*cpu_idle_hook)(void) = NULL; /* ACPI idle hook. */ 585 586 static void 587 cpu_idle_hlt(int busy) 588 { 589 /* 590 * we must absolutely guarentee that hlt is the next instruction 591 * after sti or we introduce a timing window. 592 */ 593 disable_intr(); 594 if (sched_runnable()) 595 enable_intr(); 596 else 597 __asm __volatile("sti; hlt"); 598 } 599 600 static void 601 cpu_idle_acpi(int busy) 602 { 603 disable_intr(); 604 if (sched_runnable()) 605 enable_intr(); 606 else if (cpu_idle_hook) 607 cpu_idle_hook(); 608 else 609 __asm __volatile("sti; hlt"); 610 } 611 612 static int cpu_ident_amdc1e = 0; 613 614 static int 615 cpu_probe_amdc1e(void) 616 { 617 int i; 618 619 /* 620 * Forget it, if we're not using local APIC timer. 621 */ 622 if (resource_disabled("apic", 0) || 623 (resource_int_value("apic", 0, "clock", &i) == 0 && i == 0)) 624 return (0); 625 626 /* 627 * Detect the presence of C1E capability mostly on latest 628 * dual-cores (or future) k8 family. 629 */ 630 if (cpu_vendor_id == CPU_VENDOR_AMD && 631 (cpu_id & 0x00000f00) == 0x00000f00 && 632 (cpu_id & 0x0fff0000) >= 0x00040000) { 633 cpu_ident_amdc1e = 1; 634 return (1); 635 } 636 637 return (0); 638 } 639 640 /* 641 * C1E renders the local APIC timer dead, so we disable it by 642 * reading the Interrupt Pending Message register and clearing 643 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 644 * 645 * Reference: 646 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 647 * #32559 revision 3.00+ 648 */ 649 #define MSR_AMDK8_IPM 0xc0010055 650 #define AMDK8_SMIONCMPHALT (1ULL << 27) 651 #define AMDK8_C1EONCMPHALT (1ULL << 28) 652 #define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 653 654 static void 655 cpu_idle_amdc1e(int busy) 656 { 657 658 disable_intr(); 659 if (sched_runnable()) 660 enable_intr(); 661 else { 662 uint64_t msr; 663 664 msr = rdmsr(MSR_AMDK8_IPM); 665 if (msr & AMDK8_CMPHALT) 666 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 667 668 if (cpu_idle_hook) 669 cpu_idle_hook(); 670 else 671 __asm __volatile("sti; hlt"); 672 } 673 } 674 675 static void 676 cpu_idle_spin(int busy) 677 { 678 return; 679 } 680 681 void (*cpu_idle_fn)(int) = cpu_idle_acpi; 682 683 void 684 cpu_idle(int busy) 685 { 686 #ifdef SMP 687 if (mp_grab_cpu_hlt()) 688 return; 689 #endif 690 cpu_idle_fn(busy); 691 } 692 693 /* 694 * mwait cpu power states. Lower 4 bits are sub-states. 695 */ 696 #define MWAIT_C0 0xf0 697 #define MWAIT_C1 0x00 698 #define MWAIT_C2 0x10 699 #define MWAIT_C3 0x20 700 #define MWAIT_C4 0x30 701 702 #define MWAIT_DISABLED 0x0 703 #define MWAIT_WOKEN 0x1 704 #define MWAIT_WAITING 0x2 705 706 static void 707 cpu_idle_mwait(int busy) 708 { 709 int *mwait; 710 711 mwait = (int *)PCPU_PTR(monitorbuf); 712 *mwait = MWAIT_WAITING; 713 if (sched_runnable()) 714 return; 715 cpu_monitor(mwait, 0, 0); 716 if (*mwait == MWAIT_WAITING) 717 cpu_mwait(0, MWAIT_C1); 718 } 719 720 static void 721 cpu_idle_mwait_hlt(int busy) 722 { 723 int *mwait; 724 725 mwait = (int *)PCPU_PTR(monitorbuf); 726 if (busy == 0) { 727 *mwait = MWAIT_DISABLED; 728 cpu_idle_hlt(busy); 729 return; 730 } 731 *mwait = MWAIT_WAITING; 732 if (sched_runnable()) 733 return; 734 cpu_monitor(mwait, 0, 0); 735 if (*mwait == MWAIT_WAITING) 736 cpu_mwait(0, MWAIT_C1); 737 } 738 739 int 740 cpu_idle_wakeup(int cpu) 741 { 742 struct pcpu *pcpu; 743 int *mwait; 744 745 if (cpu_idle_fn == cpu_idle_spin) 746 return (1); 747 if (cpu_idle_fn != cpu_idle_mwait && cpu_idle_fn != cpu_idle_mwait_hlt) 748 return (0); 749 pcpu = pcpu_find(cpu); 750 mwait = (int *)pcpu->pc_monitorbuf; 751 /* 752 * This doesn't need to be atomic since missing the race will 753 * simply result in unnecessary IPIs. 754 */ 755 if (cpu_idle_fn == cpu_idle_mwait_hlt && *mwait == MWAIT_DISABLED) 756 return (0); 757 *mwait = MWAIT_WOKEN; 758 759 return (1); 760 } 761 762 /* 763 * Ordered by speed/power consumption. 764 */ 765 struct { 766 void *id_fn; 767 char *id_name; 768 } idle_tbl[] = { 769 { cpu_idle_spin, "spin" }, 770 { cpu_idle_mwait, "mwait" }, 771 { cpu_idle_mwait_hlt, "mwait_hlt" }, 772 { cpu_idle_amdc1e, "amdc1e" }, 773 { cpu_idle_hlt, "hlt" }, 774 { cpu_idle_acpi, "acpi" }, 775 { NULL, NULL } 776 }; 777 778 static int 779 idle_sysctl_available(SYSCTL_HANDLER_ARGS) 780 { 781 char *avail, *p; 782 int error; 783 int i; 784 785 avail = malloc(256, M_TEMP, M_WAITOK); 786 p = avail; 787 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 788 if (strstr(idle_tbl[i].id_name, "mwait") && 789 (cpu_feature2 & CPUID2_MON) == 0) 790 continue; 791 if (strcmp(idle_tbl[i].id_name, "amdc1e") == 0 && 792 cpu_ident_amdc1e == 0) 793 continue; 794 p += sprintf(p, "%s, ", idle_tbl[i].id_name); 795 } 796 error = sysctl_handle_string(oidp, avail, 0, req); 797 free(avail, M_TEMP); 798 return (error); 799 } 800 801 static int 802 idle_sysctl(SYSCTL_HANDLER_ARGS) 803 { 804 char buf[16]; 805 int error; 806 char *p; 807 int i; 808 809 p = "unknown"; 810 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 811 if (idle_tbl[i].id_fn == cpu_idle_fn) { 812 p = idle_tbl[i].id_name; 813 break; 814 } 815 } 816 strncpy(buf, p, sizeof(buf)); 817 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 818 if (error != 0 || req->newptr == NULL) 819 return (error); 820 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 821 if (strstr(idle_tbl[i].id_name, "mwait") && 822 (cpu_feature2 & CPUID2_MON) == 0) 823 continue; 824 if (strcmp(idle_tbl[i].id_name, "amdc1e") == 0 && 825 cpu_ident_amdc1e == 0) 826 continue; 827 if (strcmp(idle_tbl[i].id_name, buf)) 828 continue; 829 cpu_idle_fn = idle_tbl[i].id_fn; 830 return (0); 831 } 832 return (EINVAL); 833 } 834 835 SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 836 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 837 838 SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 839 idle_sysctl, "A", "currently selected idle function"); 840 841 /* 842 * Reset registers to default values on exec. 843 */ 844 void 845 exec_setregs(td, entry, stack, ps_strings) 846 struct thread *td; 847 u_long entry; 848 u_long stack; 849 u_long ps_strings; 850 { 851 struct trapframe *regs = td->td_frame; 852 struct pcb *pcb = td->td_pcb; 853 854 mtx_lock(&dt_lock); 855 if (td->td_proc->p_md.md_ldt != NULL) 856 user_ldt_free(td); 857 else 858 mtx_unlock(&dt_lock); 859 860 pcb->pcb_fsbase = 0; 861 pcb->pcb_gsbase = 0; 862 pcb->pcb_flags &= ~(PCB_32BIT | PCB_GS32BIT); 863 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__; 864 pcb->pcb_full_iret = 1; 865 866 bzero((char *)regs, sizeof(struct trapframe)); 867 regs->tf_rip = entry; 868 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; 869 regs->tf_rdi = stack; /* argv */ 870 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 871 regs->tf_ss = _udatasel; 872 regs->tf_cs = _ucodesel; 873 regs->tf_ds = _udatasel; 874 regs->tf_es = _udatasel; 875 regs->tf_fs = _ufssel; 876 regs->tf_gs = _ugssel; 877 regs->tf_flags = TF_HASSEGS; 878 879 /* 880 * Reset the hardware debug registers if they were in use. 881 * They won't have any meaning for the newly exec'd process. 882 */ 883 if (pcb->pcb_flags & PCB_DBREGS) { 884 pcb->pcb_dr0 = 0; 885 pcb->pcb_dr1 = 0; 886 pcb->pcb_dr2 = 0; 887 pcb->pcb_dr3 = 0; 888 pcb->pcb_dr6 = 0; 889 pcb->pcb_dr7 = 0; 890 if (pcb == PCPU_GET(curpcb)) { 891 /* 892 * Clear the debug registers on the running 893 * CPU, otherwise they will end up affecting 894 * the next process we switch to. 895 */ 896 reset_dbregs(); 897 } 898 pcb->pcb_flags &= ~PCB_DBREGS; 899 } 900 901 /* 902 * Drop the FP state if we hold it, so that the process gets a 903 * clean FP state if it uses the FPU again. 904 */ 905 fpstate_drop(td); 906 } 907 908 void 909 cpu_setregs(void) 910 { 911 register_t cr0; 912 913 cr0 = rcr0(); 914 /* 915 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the 916 * BSP. See the comments there about why we set them. 917 */ 918 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; 919 load_cr0(cr0); 920 } 921 922 /* 923 * Initialize amd64 and configure to run kernel 924 */ 925 926 /* 927 * Initialize segments & interrupt table 928 */ 929 930 struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */ 931 static struct gate_descriptor idt0[NIDT]; 932 struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ 933 934 static char dblfault_stack[PAGE_SIZE] __aligned(16); 935 936 static char nmi0_stack[PAGE_SIZE] __aligned(16); 937 CTASSERT(sizeof(struct nmi_pcpu) == 16); 938 939 struct amd64tss common_tss[MAXCPU]; 940 941 /* 942 * Software prototypes -- in more palatable form. 943 * 944 * Keep GUFS32, GUGS32, GUCODE32 and GUDATA at the same 945 * slots as corresponding segments for i386 kernel. 946 */ 947 struct soft_segment_descriptor gdt_segs[] = { 948 /* GNULL_SEL 0 Null Descriptor */ 949 { .ssd_base = 0x0, 950 .ssd_limit = 0x0, 951 .ssd_type = 0, 952 .ssd_dpl = 0, 953 .ssd_p = 0, 954 .ssd_long = 0, 955 .ssd_def32 = 0, 956 .ssd_gran = 0 }, 957 /* GNULL2_SEL 1 Null Descriptor */ 958 { .ssd_base = 0x0, 959 .ssd_limit = 0x0, 960 .ssd_type = 0, 961 .ssd_dpl = 0, 962 .ssd_p = 0, 963 .ssd_long = 0, 964 .ssd_def32 = 0, 965 .ssd_gran = 0 }, 966 /* GUFS32_SEL 2 32 bit %gs Descriptor for user */ 967 { .ssd_base = 0x0, 968 .ssd_limit = 0xfffff, 969 .ssd_type = SDT_MEMRWA, 970 .ssd_dpl = SEL_UPL, 971 .ssd_p = 1, 972 .ssd_long = 0, 973 .ssd_def32 = 1, 974 .ssd_gran = 1 }, 975 /* GUGS32_SEL 3 32 bit %fs Descriptor for user */ 976 { .ssd_base = 0x0, 977 .ssd_limit = 0xfffff, 978 .ssd_type = SDT_MEMRWA, 979 .ssd_dpl = SEL_UPL, 980 .ssd_p = 1, 981 .ssd_long = 0, 982 .ssd_def32 = 1, 983 .ssd_gran = 1 }, 984 /* GCODE_SEL 4 Code Descriptor for kernel */ 985 { .ssd_base = 0x0, 986 .ssd_limit = 0xfffff, 987 .ssd_type = SDT_MEMERA, 988 .ssd_dpl = SEL_KPL, 989 .ssd_p = 1, 990 .ssd_long = 1, 991 .ssd_def32 = 0, 992 .ssd_gran = 1 }, 993 /* GDATA_SEL 5 Data Descriptor for kernel */ 994 { .ssd_base = 0x0, 995 .ssd_limit = 0xfffff, 996 .ssd_type = SDT_MEMRWA, 997 .ssd_dpl = SEL_KPL, 998 .ssd_p = 1, 999 .ssd_long = 1, 1000 .ssd_def32 = 0, 1001 .ssd_gran = 1 }, 1002 /* GUCODE32_SEL 6 32 bit Code Descriptor for user */ 1003 { .ssd_base = 0x0, 1004 .ssd_limit = 0xfffff, 1005 .ssd_type = SDT_MEMERA, 1006 .ssd_dpl = SEL_UPL, 1007 .ssd_p = 1, 1008 .ssd_long = 0, 1009 .ssd_def32 = 1, 1010 .ssd_gran = 1 }, 1011 /* GUDATA_SEL 7 32/64 bit Data Descriptor for user */ 1012 { .ssd_base = 0x0, 1013 .ssd_limit = 0xfffff, 1014 .ssd_type = SDT_MEMRWA, 1015 .ssd_dpl = SEL_UPL, 1016 .ssd_p = 1, 1017 .ssd_long = 0, 1018 .ssd_def32 = 1, 1019 .ssd_gran = 1 }, 1020 /* GUCODE_SEL 8 64 bit Code Descriptor for user */ 1021 { .ssd_base = 0x0, 1022 .ssd_limit = 0xfffff, 1023 .ssd_type = SDT_MEMERA, 1024 .ssd_dpl = SEL_UPL, 1025 .ssd_p = 1, 1026 .ssd_long = 1, 1027 .ssd_def32 = 0, 1028 .ssd_gran = 1 }, 1029 /* GPROC0_SEL 9 Proc 0 Tss Descriptor */ 1030 { .ssd_base = 0x0, 1031 .ssd_limit = sizeof(struct amd64tss) + IOPAGES * PAGE_SIZE - 1, 1032 .ssd_type = SDT_SYSTSS, 1033 .ssd_dpl = SEL_KPL, 1034 .ssd_p = 1, 1035 .ssd_long = 0, 1036 .ssd_def32 = 0, 1037 .ssd_gran = 0 }, 1038 /* Actually, the TSS is a system descriptor which is double size */ 1039 { .ssd_base = 0x0, 1040 .ssd_limit = 0x0, 1041 .ssd_type = 0, 1042 .ssd_dpl = 0, 1043 .ssd_p = 0, 1044 .ssd_long = 0, 1045 .ssd_def32 = 0, 1046 .ssd_gran = 0 }, 1047 /* GUSERLDT_SEL 11 LDT Descriptor */ 1048 { .ssd_base = 0x0, 1049 .ssd_limit = 0x0, 1050 .ssd_type = 0, 1051 .ssd_dpl = 0, 1052 .ssd_p = 0, 1053 .ssd_long = 0, 1054 .ssd_def32 = 0, 1055 .ssd_gran = 0 }, 1056 /* GUSERLDT_SEL 12 LDT Descriptor, double size */ 1057 { .ssd_base = 0x0, 1058 .ssd_limit = 0x0, 1059 .ssd_type = 0, 1060 .ssd_dpl = 0, 1061 .ssd_p = 0, 1062 .ssd_long = 0, 1063 .ssd_def32 = 0, 1064 .ssd_gran = 0 }, 1065 }; 1066 1067 void 1068 setidt(idx, func, typ, dpl, ist) 1069 int idx; 1070 inthand_t *func; 1071 int typ; 1072 int dpl; 1073 int ist; 1074 { 1075 struct gate_descriptor *ip; 1076 1077 ip = idt + idx; 1078 ip->gd_looffset = (uintptr_t)func; 1079 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1080 ip->gd_ist = ist; 1081 ip->gd_xx = 0; 1082 ip->gd_type = typ; 1083 ip->gd_dpl = dpl; 1084 ip->gd_p = 1; 1085 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1086 } 1087 1088 extern inthand_t 1089 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1090 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1091 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1092 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1093 IDTVEC(xmm), IDTVEC(dblfault), 1094 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1095 1096 #ifdef DDB 1097 /* 1098 * Display the index and function name of any IDT entries that don't use 1099 * the default 'rsvd' entry point. 1100 */ 1101 DB_SHOW_COMMAND(idt, db_show_idt) 1102 { 1103 struct gate_descriptor *ip; 1104 int idx; 1105 uintptr_t func; 1106 1107 ip = idt; 1108 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) { 1109 func = ((long)ip->gd_hioffset << 16 | ip->gd_looffset); 1110 if (func != (uintptr_t)&IDTVEC(rsvd)) { 1111 db_printf("%3d\t", idx); 1112 db_printsym(func, DB_STGY_PROC); 1113 db_printf("\n"); 1114 } 1115 ip++; 1116 } 1117 } 1118 #endif 1119 1120 void 1121 sdtossd(sd, ssd) 1122 struct user_segment_descriptor *sd; 1123 struct soft_segment_descriptor *ssd; 1124 { 1125 1126 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1127 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1128 ssd->ssd_type = sd->sd_type; 1129 ssd->ssd_dpl = sd->sd_dpl; 1130 ssd->ssd_p = sd->sd_p; 1131 ssd->ssd_long = sd->sd_long; 1132 ssd->ssd_def32 = sd->sd_def32; 1133 ssd->ssd_gran = sd->sd_gran; 1134 } 1135 1136 void 1137 ssdtosd(ssd, sd) 1138 struct soft_segment_descriptor *ssd; 1139 struct user_segment_descriptor *sd; 1140 { 1141 1142 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1143 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1144 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1145 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1146 sd->sd_type = ssd->ssd_type; 1147 sd->sd_dpl = ssd->ssd_dpl; 1148 sd->sd_p = ssd->ssd_p; 1149 sd->sd_long = ssd->ssd_long; 1150 sd->sd_def32 = ssd->ssd_def32; 1151 sd->sd_gran = ssd->ssd_gran; 1152 } 1153 1154 void 1155 ssdtosyssd(ssd, sd) 1156 struct soft_segment_descriptor *ssd; 1157 struct system_segment_descriptor *sd; 1158 { 1159 1160 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1161 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1162 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1163 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1164 sd->sd_type = ssd->ssd_type; 1165 sd->sd_dpl = ssd->ssd_dpl; 1166 sd->sd_p = ssd->ssd_p; 1167 sd->sd_gran = ssd->ssd_gran; 1168 } 1169 1170 #if !defined(DEV_ATPIC) && defined(DEV_ISA) 1171 #include <isa/isavar.h> 1172 #include <isa/isareg.h> 1173 /* 1174 * Return a bitmap of the current interrupt requests. This is 8259-specific 1175 * and is only suitable for use at probe time. 1176 * This is only here to pacify sio. It is NOT FATAL if this doesn't work. 1177 * It shouldn't be here. There should probably be an APIC centric 1178 * implementation in the apic driver code, if at all. 1179 */ 1180 intrmask_t 1181 isa_irq_pending(void) 1182 { 1183 u_char irr1; 1184 u_char irr2; 1185 1186 irr1 = inb(IO_ICU1); 1187 irr2 = inb(IO_ICU2); 1188 return ((irr2 << 8) | irr1); 1189 } 1190 #endif 1191 1192 u_int basemem; 1193 1194 static int 1195 add_smap_entry(struct bios_smap *smap, vm_paddr_t *physmap, int *physmap_idxp) 1196 { 1197 int i, insert_idx, physmap_idx; 1198 1199 physmap_idx = *physmap_idxp; 1200 1201 if (boothowto & RB_VERBOSE) 1202 printf("SMAP type=%02x base=%016lx len=%016lx\n", 1203 smap->type, smap->base, smap->length); 1204 1205 if (smap->type != SMAP_TYPE_MEMORY) 1206 return (1); 1207 1208 if (smap->length == 0) 1209 return (0); 1210 1211 /* 1212 * Find insertion point while checking for overlap. Start off by 1213 * assuming the new entry will be added to the end. 1214 */ 1215 insert_idx = physmap_idx + 2; 1216 for (i = 0; i <= physmap_idx; i += 2) { 1217 if (smap->base < physmap[i + 1]) { 1218 if (smap->base + smap->length <= physmap[i]) { 1219 insert_idx = i; 1220 break; 1221 } 1222 if (boothowto & RB_VERBOSE) 1223 printf( 1224 "Overlapping memory regions, ignoring second region\n"); 1225 return (1); 1226 } 1227 } 1228 1229 /* See if we can prepend to the next entry. */ 1230 if (insert_idx <= physmap_idx && 1231 smap->base + smap->length == physmap[insert_idx]) { 1232 physmap[insert_idx] = smap->base; 1233 return (1); 1234 } 1235 1236 /* See if we can append to the previous entry. */ 1237 if (insert_idx > 0 && smap->base == physmap[insert_idx - 1]) { 1238 physmap[insert_idx - 1] += smap->length; 1239 return (1); 1240 } 1241 1242 physmap_idx += 2; 1243 *physmap_idxp = physmap_idx; 1244 if (physmap_idx == PHYSMAP_SIZE) { 1245 printf( 1246 "Too many segments in the physical address map, giving up\n"); 1247 return (0); 1248 } 1249 1250 /* 1251 * Move the last 'N' entries down to make room for the new 1252 * entry if needed. 1253 */ 1254 for (i = physmap_idx; i > insert_idx; i -= 2) { 1255 physmap[i] = physmap[i - 2]; 1256 physmap[i + 1] = physmap[i - 1]; 1257 } 1258 1259 /* Insert the new entry. */ 1260 physmap[insert_idx] = smap->base; 1261 physmap[insert_idx + 1] = smap->base + smap->length; 1262 return (1); 1263 } 1264 1265 /* 1266 * Populate the (physmap) array with base/bound pairs describing the 1267 * available physical memory in the system, then test this memory and 1268 * build the phys_avail array describing the actually-available memory. 1269 * 1270 * If we cannot accurately determine the physical memory map, then use 1271 * value from the 0xE801 call, and failing that, the RTC. 1272 * 1273 * Total memory size may be set by the kernel environment variable 1274 * hw.physmem or the compile-time define MAXMEM. 1275 * 1276 * XXX first should be vm_paddr_t. 1277 */ 1278 static void 1279 getmemsize(caddr_t kmdp, u_int64_t first) 1280 { 1281 int i, off, physmap_idx, pa_indx, da_indx; 1282 vm_paddr_t pa, physmap[PHYSMAP_SIZE]; 1283 u_long physmem_tunable; 1284 pt_entry_t *pte; 1285 struct bios_smap *smapbase, *smap, *smapend; 1286 u_int32_t smapsize; 1287 quad_t dcons_addr, dcons_size; 1288 1289 bzero(physmap, sizeof(physmap)); 1290 basemem = 0; 1291 physmap_idx = 0; 1292 1293 /* 1294 * get memory map from INT 15:E820, kindly supplied by the loader. 1295 * 1296 * subr_module.c says: 1297 * "Consumer may safely assume that size value precedes data." 1298 * ie: an int32_t immediately precedes smap. 1299 */ 1300 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1301 MODINFO_METADATA | MODINFOMD_SMAP); 1302 if (smapbase == NULL) 1303 panic("No BIOS smap info from loader!"); 1304 1305 smapsize = *((u_int32_t *)smapbase - 1); 1306 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1307 1308 for (smap = smapbase; smap < smapend; smap++) 1309 if (!add_smap_entry(smap, physmap, &physmap_idx)) 1310 break; 1311 1312 /* 1313 * Find the 'base memory' segment for SMP 1314 */ 1315 basemem = 0; 1316 for (i = 0; i <= physmap_idx; i += 2) { 1317 if (physmap[i] == 0x00000000) { 1318 basemem = physmap[i + 1] / 1024; 1319 break; 1320 } 1321 } 1322 if (basemem == 0) 1323 panic("BIOS smap did not include a basemem segment!"); 1324 1325 #ifdef SMP 1326 /* make hole for AP bootstrap code */ 1327 physmap[1] = mp_bootaddress(physmap[1] / 1024); 1328 #endif 1329 1330 /* 1331 * Maxmem isn't the "maximum memory", it's one larger than the 1332 * highest page of the physical address space. It should be 1333 * called something like "Maxphyspage". We may adjust this 1334 * based on ``hw.physmem'' and the results of the memory test. 1335 */ 1336 Maxmem = atop(physmap[physmap_idx + 1]); 1337 1338 #ifdef MAXMEM 1339 Maxmem = MAXMEM / 4; 1340 #endif 1341 1342 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1343 Maxmem = atop(physmem_tunable); 1344 1345 /* 1346 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1347 * in the system. 1348 */ 1349 if (Maxmem > atop(physmap[physmap_idx + 1])) 1350 Maxmem = atop(physmap[physmap_idx + 1]); 1351 1352 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1353 (boothowto & RB_VERBOSE)) 1354 printf("Physical memory use set to %ldK\n", Maxmem * 4); 1355 1356 /* call pmap initialization to make new kernel address space */ 1357 pmap_bootstrap(&first); 1358 1359 /* 1360 * Size up each available chunk of physical memory. 1361 */ 1362 physmap[0] = PAGE_SIZE; /* mask off page 0 */ 1363 pa_indx = 0; 1364 da_indx = 1; 1365 phys_avail[pa_indx++] = physmap[0]; 1366 phys_avail[pa_indx] = physmap[0]; 1367 dump_avail[da_indx] = physmap[0]; 1368 pte = CMAP1; 1369 1370 /* 1371 * Get dcons buffer address 1372 */ 1373 if (getenv_quad("dcons.addr", &dcons_addr) == 0 || 1374 getenv_quad("dcons.size", &dcons_size) == 0) 1375 dcons_addr = 0; 1376 1377 /* 1378 * physmap is in bytes, so when converting to page boundaries, 1379 * round up the start address and round down the end address. 1380 */ 1381 for (i = 0; i <= physmap_idx; i += 2) { 1382 vm_paddr_t end; 1383 1384 end = ptoa((vm_paddr_t)Maxmem); 1385 if (physmap[i + 1] < end) 1386 end = trunc_page(physmap[i + 1]); 1387 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) { 1388 int tmp, page_bad, full; 1389 int *ptr = (int *)CADDR1; 1390 1391 full = FALSE; 1392 /* 1393 * block out kernel memory as not available. 1394 */ 1395 if (pa >= 0x100000 && pa < first) 1396 goto do_dump_avail; 1397 1398 /* 1399 * block out dcons buffer 1400 */ 1401 if (dcons_addr > 0 1402 && pa >= trunc_page(dcons_addr) 1403 && pa < dcons_addr + dcons_size) 1404 goto do_dump_avail; 1405 1406 page_bad = FALSE; 1407 1408 /* 1409 * map page into kernel: valid, read/write,non-cacheable 1410 */ 1411 *pte = pa | PG_V | PG_RW | PG_N; 1412 invltlb(); 1413 1414 tmp = *(int *)ptr; 1415 /* 1416 * Test for alternating 1's and 0's 1417 */ 1418 *(volatile int *)ptr = 0xaaaaaaaa; 1419 if (*(volatile int *)ptr != 0xaaaaaaaa) 1420 page_bad = TRUE; 1421 /* 1422 * Test for alternating 0's and 1's 1423 */ 1424 *(volatile int *)ptr = 0x55555555; 1425 if (*(volatile int *)ptr != 0x55555555) 1426 page_bad = TRUE; 1427 /* 1428 * Test for all 1's 1429 */ 1430 *(volatile int *)ptr = 0xffffffff; 1431 if (*(volatile int *)ptr != 0xffffffff) 1432 page_bad = TRUE; 1433 /* 1434 * Test for all 0's 1435 */ 1436 *(volatile int *)ptr = 0x0; 1437 if (*(volatile int *)ptr != 0x0) 1438 page_bad = TRUE; 1439 /* 1440 * Restore original value. 1441 */ 1442 *(int *)ptr = tmp; 1443 1444 /* 1445 * Adjust array of valid/good pages. 1446 */ 1447 if (page_bad == TRUE) 1448 continue; 1449 /* 1450 * If this good page is a continuation of the 1451 * previous set of good pages, then just increase 1452 * the end pointer. Otherwise start a new chunk. 1453 * Note that "end" points one higher than end, 1454 * making the range >= start and < end. 1455 * If we're also doing a speculative memory 1456 * test and we at or past the end, bump up Maxmem 1457 * so that we keep going. The first bad page 1458 * will terminate the loop. 1459 */ 1460 if (phys_avail[pa_indx] == pa) { 1461 phys_avail[pa_indx] += PAGE_SIZE; 1462 } else { 1463 pa_indx++; 1464 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1465 printf( 1466 "Too many holes in the physical address space, giving up\n"); 1467 pa_indx--; 1468 full = TRUE; 1469 goto do_dump_avail; 1470 } 1471 phys_avail[pa_indx++] = pa; /* start */ 1472 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */ 1473 } 1474 physmem++; 1475 do_dump_avail: 1476 if (dump_avail[da_indx] == pa) { 1477 dump_avail[da_indx] += PAGE_SIZE; 1478 } else { 1479 da_indx++; 1480 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1481 da_indx--; 1482 goto do_next; 1483 } 1484 dump_avail[da_indx++] = pa; /* start */ 1485 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */ 1486 } 1487 do_next: 1488 if (full) 1489 break; 1490 } 1491 } 1492 *pte = 0; 1493 invltlb(); 1494 1495 /* 1496 * XXX 1497 * The last chunk must contain at least one page plus the message 1498 * buffer to avoid complicating other code (message buffer address 1499 * calculation, etc.). 1500 */ 1501 while (phys_avail[pa_indx - 1] + PAGE_SIZE + 1502 round_page(MSGBUF_SIZE) >= phys_avail[pa_indx]) { 1503 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1504 phys_avail[pa_indx--] = 0; 1505 phys_avail[pa_indx--] = 0; 1506 } 1507 1508 Maxmem = atop(phys_avail[pa_indx]); 1509 1510 /* Trim off space for the message buffer. */ 1511 phys_avail[pa_indx] -= round_page(MSGBUF_SIZE); 1512 1513 /* Map the message buffer. */ 1514 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE) 1515 pmap_kenter((vm_offset_t)msgbufp + off, phys_avail[pa_indx] + 1516 off); 1517 } 1518 1519 u_int64_t 1520 hammer_time(u_int64_t modulep, u_int64_t physfree) 1521 { 1522 caddr_t kmdp; 1523 int gsel_tss, x; 1524 struct pcpu *pc; 1525 struct nmi_pcpu *np; 1526 u_int64_t msr; 1527 char *env; 1528 1529 thread0.td_kstack = physfree + KERNBASE; 1530 bzero((void *)thread0.td_kstack, KSTACK_PAGES * PAGE_SIZE); 1531 physfree += KSTACK_PAGES * PAGE_SIZE; 1532 thread0.td_pcb = (struct pcb *) 1533 (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1; 1534 1535 /* 1536 * This may be done better later if it gets more high level 1537 * components in it. If so just link td->td_proc here. 1538 */ 1539 proc_linkup0(&proc0, &thread0); 1540 1541 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE); 1542 preload_bootstrap_relocate(KERNBASE); 1543 kmdp = preload_search_by_type("elf kernel"); 1544 if (kmdp == NULL) 1545 kmdp = preload_search_by_type("elf64 kernel"); 1546 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1547 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE; 1548 #ifdef DDB 1549 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1550 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1551 #endif 1552 1553 /* Init basic tunables, hz etc */ 1554 init_param1(); 1555 1556 /* 1557 * make gdt memory segments 1558 */ 1559 for (x = 0; x < NGDT; x++) { 1560 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 1561 x != GUSERLDT_SEL && x != (GUSERLDT_SEL) + 1) 1562 ssdtosd(&gdt_segs[x], &gdt[x]); 1563 } 1564 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0]; 1565 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1566 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1567 1568 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1569 r_gdt.rd_base = (long) gdt; 1570 lgdt(&r_gdt); 1571 pc = &__pcpu[0]; 1572 1573 wrmsr(MSR_FSBASE, 0); /* User value */ 1574 wrmsr(MSR_GSBASE, (u_int64_t)pc); 1575 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1576 1577 pcpu_init(pc, 0, sizeof(struct pcpu)); 1578 dpcpu_init((void *)(physfree + KERNBASE), 0); 1579 physfree += DPCPU_SIZE; 1580 PCPU_SET(prvspace, pc); 1581 PCPU_SET(curthread, &thread0); 1582 PCPU_SET(curpcb, thread0.td_pcb); 1583 PCPU_SET(tssp, &common_tss[0]); 1584 PCPU_SET(commontssp, &common_tss[0]); 1585 PCPU_SET(tss, (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1586 PCPU_SET(ldt, (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL]); 1587 PCPU_SET(fs32p, &gdt[GUFS32_SEL]); 1588 PCPU_SET(gs32p, &gdt[GUGS32_SEL]); 1589 1590 /* 1591 * Initialize mutexes. 1592 * 1593 * icu_lock: in order to allow an interrupt to occur in a critical 1594 * section, to set pcpu->ipending (etc...) properly, we 1595 * must be able to get the icu lock, so it can't be 1596 * under witness. 1597 */ 1598 mutex_init(); 1599 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS); 1600 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_DEF); 1601 1602 /* exceptions */ 1603 for (x = 0; x < NIDT; x++) 1604 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1605 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1606 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1607 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2); 1608 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1609 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1610 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1611 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1612 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1613 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1614 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1615 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1616 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1617 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1618 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1619 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1620 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1621 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1622 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1623 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1624 1625 r_idt.rd_limit = sizeof(idt0) - 1; 1626 r_idt.rd_base = (long) idt; 1627 lidt(&r_idt); 1628 1629 /* 1630 * Initialize the i8254 before the console so that console 1631 * initialization can use DELAY(). 1632 */ 1633 i8254_init(); 1634 1635 /* 1636 * Initialize the console before we print anything out. 1637 */ 1638 cninit(); 1639 1640 #ifdef DEV_ISA 1641 #ifdef DEV_ATPIC 1642 elcr_probe(); 1643 atpic_startup(); 1644 #else 1645 /* Reset and mask the atpics and leave them shut down. */ 1646 atpic_reset(); 1647 1648 /* 1649 * Point the ICU spurious interrupt vectors at the APIC spurious 1650 * interrupt handler. 1651 */ 1652 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1653 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1654 #endif 1655 #else 1656 #error "have you forgotten the isa device?"; 1657 #endif 1658 1659 kdb_init(); 1660 1661 #ifdef KDB 1662 if (boothowto & RB_KDB) 1663 kdb_enter(KDB_WHY_BOOTFLAGS, 1664 "Boot flags requested debugger"); 1665 #endif 1666 1667 identify_cpu(); /* Final stage of CPU initialization */ 1668 initializecpu(); /* Initialize CPU registers */ 1669 initializecpucache(); 1670 1671 /* make an initial tss so cpu can get interrupt stack on syscall! */ 1672 common_tss[0].tss_rsp0 = thread0.td_kstack + \ 1673 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb); 1674 /* Ensure the stack is aligned to 16 bytes */ 1675 common_tss[0].tss_rsp0 &= ~0xFul; 1676 PCPU_SET(rsp0, common_tss[0].tss_rsp0); 1677 1678 /* doublefault stack space, runs on ist1 */ 1679 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)]; 1680 1681 /* 1682 * NMI stack, runs on ist2. The pcpu pointer is stored just 1683 * above the start of the ist2 stack. 1684 */ 1685 np = ((struct nmi_pcpu *) &nmi0_stack[sizeof(nmi0_stack)]) - 1; 1686 np->np_pcpu = (register_t) pc; 1687 common_tss[0].tss_ist2 = (long) np; 1688 1689 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1690 common_tss[0].tss_iobase = sizeof(struct amd64tss) + 1691 IOPAGES * PAGE_SIZE; 1692 1693 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1694 ltr(gsel_tss); 1695 1696 /* Set up the fast syscall stuff */ 1697 msr = rdmsr(MSR_EFER) | EFER_SCE; 1698 wrmsr(MSR_EFER, msr); 1699 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1700 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1701 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1702 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1703 wrmsr(MSR_STAR, msr); 1704 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 1705 1706 getmemsize(kmdp, physfree); 1707 init_param2(physmem); 1708 1709 /* now running on new page tables, configured,and u/iom is accessible */ 1710 1711 msgbufinit(msgbufp, MSGBUF_SIZE); 1712 fpuinit(); 1713 1714 /* transfer to user mode */ 1715 1716 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 1717 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 1718 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 1719 _ufssel = GSEL(GUFS32_SEL, SEL_UPL); 1720 _ugssel = GSEL(GUGS32_SEL, SEL_UPL); 1721 1722 load_ds(_udatasel); 1723 load_es(_udatasel); 1724 load_fs(_ufssel); 1725 1726 /* setup proc 0's pcb */ 1727 thread0.td_pcb->pcb_flags = 0; 1728 thread0.td_pcb->pcb_cr3 = KPML4phys; 1729 thread0.td_frame = &proc0_tf; 1730 1731 env = getenv("kernelname"); 1732 if (env != NULL) 1733 strlcpy(kernelname, env, sizeof(kernelname)); 1734 1735 #ifdef XENHVM 1736 if (inw(0x10) == 0x49d2) { 1737 if (bootverbose) 1738 printf("Xen detected: disabling emulated block and network devices\n"); 1739 outw(0x10, 3); 1740 } 1741 #endif 1742 1743 if (cpu_probe_amdc1e()) 1744 cpu_idle_fn = cpu_idle_amdc1e; 1745 1746 /* Location of kernel stack for locore */ 1747 return ((u_int64_t)thread0.td_pcb); 1748 } 1749 1750 void 1751 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 1752 { 1753 1754 pcpu->pc_acpi_id = 0xffffffff; 1755 } 1756 1757 void 1758 spinlock_enter(void) 1759 { 1760 struct thread *td; 1761 1762 td = curthread; 1763 if (td->td_md.md_spinlock_count == 0) 1764 td->td_md.md_saved_flags = intr_disable(); 1765 td->td_md.md_spinlock_count++; 1766 critical_enter(); 1767 } 1768 1769 void 1770 spinlock_exit(void) 1771 { 1772 struct thread *td; 1773 1774 td = curthread; 1775 critical_exit(); 1776 td->td_md.md_spinlock_count--; 1777 if (td->td_md.md_spinlock_count == 0) 1778 intr_restore(td->td_md.md_saved_flags); 1779 } 1780 1781 /* 1782 * Construct a PCB from a trapframe. This is called from kdb_trap() where 1783 * we want to start a backtrace from the function that caused us to enter 1784 * the debugger. We have the context in the trapframe, but base the trace 1785 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 1786 * enough for a backtrace. 1787 */ 1788 void 1789 makectx(struct trapframe *tf, struct pcb *pcb) 1790 { 1791 1792 pcb->pcb_r12 = tf->tf_r12; 1793 pcb->pcb_r13 = tf->tf_r13; 1794 pcb->pcb_r14 = tf->tf_r14; 1795 pcb->pcb_r15 = tf->tf_r15; 1796 pcb->pcb_rbp = tf->tf_rbp; 1797 pcb->pcb_rbx = tf->tf_rbx; 1798 pcb->pcb_rip = tf->tf_rip; 1799 pcb->pcb_rsp = (ISPL(tf->tf_cs)) ? tf->tf_rsp : (long)(tf + 1) - 8; 1800 } 1801 1802 int 1803 ptrace_set_pc(struct thread *td, unsigned long addr) 1804 { 1805 td->td_frame->tf_rip = addr; 1806 return (0); 1807 } 1808 1809 int 1810 ptrace_single_step(struct thread *td) 1811 { 1812 td->td_frame->tf_rflags |= PSL_T; 1813 return (0); 1814 } 1815 1816 int 1817 ptrace_clear_single_step(struct thread *td) 1818 { 1819 td->td_frame->tf_rflags &= ~PSL_T; 1820 return (0); 1821 } 1822 1823 int 1824 fill_regs(struct thread *td, struct reg *regs) 1825 { 1826 struct trapframe *tp; 1827 1828 tp = td->td_frame; 1829 regs->r_r15 = tp->tf_r15; 1830 regs->r_r14 = tp->tf_r14; 1831 regs->r_r13 = tp->tf_r13; 1832 regs->r_r12 = tp->tf_r12; 1833 regs->r_r11 = tp->tf_r11; 1834 regs->r_r10 = tp->tf_r10; 1835 regs->r_r9 = tp->tf_r9; 1836 regs->r_r8 = tp->tf_r8; 1837 regs->r_rdi = tp->tf_rdi; 1838 regs->r_rsi = tp->tf_rsi; 1839 regs->r_rbp = tp->tf_rbp; 1840 regs->r_rbx = tp->tf_rbx; 1841 regs->r_rdx = tp->tf_rdx; 1842 regs->r_rcx = tp->tf_rcx; 1843 regs->r_rax = tp->tf_rax; 1844 regs->r_rip = tp->tf_rip; 1845 regs->r_cs = tp->tf_cs; 1846 regs->r_rflags = tp->tf_rflags; 1847 regs->r_rsp = tp->tf_rsp; 1848 regs->r_ss = tp->tf_ss; 1849 if (tp->tf_flags & TF_HASSEGS) { 1850 regs->r_ds = tp->tf_ds; 1851 regs->r_es = tp->tf_es; 1852 regs->r_fs = tp->tf_fs; 1853 regs->r_gs = tp->tf_gs; 1854 } else { 1855 regs->r_ds = 0; 1856 regs->r_es = 0; 1857 regs->r_fs = 0; 1858 regs->r_gs = 0; 1859 } 1860 return (0); 1861 } 1862 1863 int 1864 set_regs(struct thread *td, struct reg *regs) 1865 { 1866 struct trapframe *tp; 1867 register_t rflags; 1868 1869 tp = td->td_frame; 1870 rflags = regs->r_rflags & 0xffffffff; 1871 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs)) 1872 return (EINVAL); 1873 tp->tf_r15 = regs->r_r15; 1874 tp->tf_r14 = regs->r_r14; 1875 tp->tf_r13 = regs->r_r13; 1876 tp->tf_r12 = regs->r_r12; 1877 tp->tf_r11 = regs->r_r11; 1878 tp->tf_r10 = regs->r_r10; 1879 tp->tf_r9 = regs->r_r9; 1880 tp->tf_r8 = regs->r_r8; 1881 tp->tf_rdi = regs->r_rdi; 1882 tp->tf_rsi = regs->r_rsi; 1883 tp->tf_rbp = regs->r_rbp; 1884 tp->tf_rbx = regs->r_rbx; 1885 tp->tf_rdx = regs->r_rdx; 1886 tp->tf_rcx = regs->r_rcx; 1887 tp->tf_rax = regs->r_rax; 1888 tp->tf_rip = regs->r_rip; 1889 tp->tf_cs = regs->r_cs; 1890 tp->tf_rflags = rflags; 1891 tp->tf_rsp = regs->r_rsp; 1892 tp->tf_ss = regs->r_ss; 1893 if (0) { /* XXXKIB */ 1894 tp->tf_ds = regs->r_ds; 1895 tp->tf_es = regs->r_es; 1896 tp->tf_fs = regs->r_fs; 1897 tp->tf_gs = regs->r_gs; 1898 tp->tf_flags = TF_HASSEGS; 1899 } 1900 td->td_pcb->pcb_flags |= PCB_FULLCTX; 1901 return (0); 1902 } 1903 1904 /* XXX check all this stuff! */ 1905 /* externalize from sv_xmm */ 1906 static void 1907 fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs) 1908 { 1909 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 1910 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1911 int i; 1912 1913 /* pcb -> fpregs */ 1914 bzero(fpregs, sizeof(*fpregs)); 1915 1916 /* FPU control/status */ 1917 penv_fpreg->en_cw = penv_xmm->en_cw; 1918 penv_fpreg->en_sw = penv_xmm->en_sw; 1919 penv_fpreg->en_tw = penv_xmm->en_tw; 1920 penv_fpreg->en_opcode = penv_xmm->en_opcode; 1921 penv_fpreg->en_rip = penv_xmm->en_rip; 1922 penv_fpreg->en_rdp = penv_xmm->en_rdp; 1923 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr; 1924 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask; 1925 1926 /* FPU registers */ 1927 for (i = 0; i < 8; ++i) 1928 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10); 1929 1930 /* SSE registers */ 1931 for (i = 0; i < 16; ++i) 1932 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16); 1933 } 1934 1935 /* internalize from fpregs into sv_xmm */ 1936 static void 1937 set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm) 1938 { 1939 struct envxmm *penv_xmm = &sv_xmm->sv_env; 1940 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 1941 int i; 1942 1943 /* fpregs -> pcb */ 1944 /* FPU control/status */ 1945 penv_xmm->en_cw = penv_fpreg->en_cw; 1946 penv_xmm->en_sw = penv_fpreg->en_sw; 1947 penv_xmm->en_tw = penv_fpreg->en_tw; 1948 penv_xmm->en_opcode = penv_fpreg->en_opcode; 1949 penv_xmm->en_rip = penv_fpreg->en_rip; 1950 penv_xmm->en_rdp = penv_fpreg->en_rdp; 1951 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr; 1952 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask; 1953 1954 /* FPU registers */ 1955 for (i = 0; i < 8; ++i) 1956 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10); 1957 1958 /* SSE registers */ 1959 for (i = 0; i < 16; ++i) 1960 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16); 1961 } 1962 1963 /* externalize from td->pcb */ 1964 int 1965 fill_fpregs(struct thread *td, struct fpreg *fpregs) 1966 { 1967 1968 fill_fpregs_xmm(&td->td_pcb->pcb_save, fpregs); 1969 return (0); 1970 } 1971 1972 /* internalize to td->pcb */ 1973 int 1974 set_fpregs(struct thread *td, struct fpreg *fpregs) 1975 { 1976 1977 set_fpregs_xmm(fpregs, &td->td_pcb->pcb_save); 1978 return (0); 1979 } 1980 1981 /* 1982 * Get machine context. 1983 */ 1984 int 1985 get_mcontext(struct thread *td, mcontext_t *mcp, int flags) 1986 { 1987 struct trapframe *tp; 1988 1989 tp = td->td_frame; 1990 PROC_LOCK(curthread->td_proc); 1991 mcp->mc_onstack = sigonstack(tp->tf_rsp); 1992 PROC_UNLOCK(curthread->td_proc); 1993 mcp->mc_r15 = tp->tf_r15; 1994 mcp->mc_r14 = tp->tf_r14; 1995 mcp->mc_r13 = tp->tf_r13; 1996 mcp->mc_r12 = tp->tf_r12; 1997 mcp->mc_r11 = tp->tf_r11; 1998 mcp->mc_r10 = tp->tf_r10; 1999 mcp->mc_r9 = tp->tf_r9; 2000 mcp->mc_r8 = tp->tf_r8; 2001 mcp->mc_rdi = tp->tf_rdi; 2002 mcp->mc_rsi = tp->tf_rsi; 2003 mcp->mc_rbp = tp->tf_rbp; 2004 mcp->mc_rbx = tp->tf_rbx; 2005 mcp->mc_rcx = tp->tf_rcx; 2006 mcp->mc_rflags = tp->tf_rflags; 2007 if (flags & GET_MC_CLEAR_RET) { 2008 mcp->mc_rax = 0; 2009 mcp->mc_rdx = 0; 2010 mcp->mc_rflags &= ~PSL_C; 2011 } else { 2012 mcp->mc_rax = tp->tf_rax; 2013 mcp->mc_rdx = tp->tf_rdx; 2014 } 2015 mcp->mc_rip = tp->tf_rip; 2016 mcp->mc_cs = tp->tf_cs; 2017 mcp->mc_rsp = tp->tf_rsp; 2018 mcp->mc_ss = tp->tf_ss; 2019 mcp->mc_ds = tp->tf_ds; 2020 mcp->mc_es = tp->tf_es; 2021 mcp->mc_fs = tp->tf_fs; 2022 mcp->mc_gs = tp->tf_gs; 2023 mcp->mc_flags = tp->tf_flags; 2024 mcp->mc_len = sizeof(*mcp); 2025 get_fpcontext(td, mcp); 2026 mcp->mc_fsbase = td->td_pcb->pcb_fsbase; 2027 mcp->mc_gsbase = td->td_pcb->pcb_gsbase; 2028 return (0); 2029 } 2030 2031 /* 2032 * Set machine context. 2033 * 2034 * However, we don't set any but the user modifiable flags, and we won't 2035 * touch the cs selector. 2036 */ 2037 int 2038 set_mcontext(struct thread *td, const mcontext_t *mcp) 2039 { 2040 struct trapframe *tp; 2041 long rflags; 2042 int ret; 2043 2044 tp = td->td_frame; 2045 if (mcp->mc_len != sizeof(*mcp) || 2046 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0) 2047 return (EINVAL); 2048 rflags = (mcp->mc_rflags & PSL_USERCHANGE) | 2049 (tp->tf_rflags & ~PSL_USERCHANGE); 2050 ret = set_fpcontext(td, mcp); 2051 if (ret != 0) 2052 return (ret); 2053 tp->tf_r15 = mcp->mc_r15; 2054 tp->tf_r14 = mcp->mc_r14; 2055 tp->tf_r13 = mcp->mc_r13; 2056 tp->tf_r12 = mcp->mc_r12; 2057 tp->tf_r11 = mcp->mc_r11; 2058 tp->tf_r10 = mcp->mc_r10; 2059 tp->tf_r9 = mcp->mc_r9; 2060 tp->tf_r8 = mcp->mc_r8; 2061 tp->tf_rdi = mcp->mc_rdi; 2062 tp->tf_rsi = mcp->mc_rsi; 2063 tp->tf_rbp = mcp->mc_rbp; 2064 tp->tf_rbx = mcp->mc_rbx; 2065 tp->tf_rdx = mcp->mc_rdx; 2066 tp->tf_rcx = mcp->mc_rcx; 2067 tp->tf_rax = mcp->mc_rax; 2068 tp->tf_rip = mcp->mc_rip; 2069 tp->tf_rflags = rflags; 2070 tp->tf_rsp = mcp->mc_rsp; 2071 tp->tf_ss = mcp->mc_ss; 2072 tp->tf_flags = mcp->mc_flags; 2073 if (tp->tf_flags & TF_HASSEGS) { 2074 tp->tf_ds = mcp->mc_ds; 2075 tp->tf_es = mcp->mc_es; 2076 tp->tf_fs = mcp->mc_fs; 2077 tp->tf_gs = mcp->mc_gs; 2078 } 2079 if (mcp->mc_flags & _MC_HASBASES) { 2080 td->td_pcb->pcb_fsbase = mcp->mc_fsbase; 2081 td->td_pcb->pcb_gsbase = mcp->mc_gsbase; 2082 } 2083 td->td_pcb->pcb_flags |= PCB_FULLCTX; 2084 td->td_pcb->pcb_full_iret = 1; 2085 return (0); 2086 } 2087 2088 static void 2089 get_fpcontext(struct thread *td, mcontext_t *mcp) 2090 { 2091 2092 mcp->mc_ownedfp = fpugetregs(td, (struct savefpu *)&mcp->mc_fpstate); 2093 mcp->mc_fpformat = fpuformat(); 2094 } 2095 2096 static int 2097 set_fpcontext(struct thread *td, const mcontext_t *mcp) 2098 { 2099 struct savefpu *fpstate; 2100 2101 if (mcp->mc_fpformat == _MC_FPFMT_NODEV) 2102 return (0); 2103 else if (mcp->mc_fpformat != _MC_FPFMT_XMM) 2104 return (EINVAL); 2105 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) 2106 /* We don't care what state is left in the FPU or PCB. */ 2107 fpstate_drop(td); 2108 else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || 2109 mcp->mc_ownedfp == _MC_FPOWNED_PCB) { 2110 /* 2111 * XXX we violate the dubious requirement that fpusetregs() 2112 * be called with interrupts disabled. 2113 * XXX obsolete on trap-16 systems? 2114 */ 2115 fpstate = (struct savefpu *)&mcp->mc_fpstate; 2116 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask; 2117 fpusetregs(td, fpstate); 2118 } else 2119 return (EINVAL); 2120 return (0); 2121 } 2122 2123 void 2124 fpstate_drop(struct thread *td) 2125 { 2126 register_t s; 2127 2128 s = intr_disable(); 2129 if (PCPU_GET(fpcurthread) == td) 2130 fpudrop(); 2131 /* 2132 * XXX force a full drop of the fpu. The above only drops it if we 2133 * owned it. 2134 * 2135 * XXX I don't much like fpugetregs()'s semantics of doing a full 2136 * drop. Dropping only to the pcb matches fnsave's behaviour. 2137 * We only need to drop to !PCB_INITDONE in sendsig(). But 2138 * sendsig() is the only caller of fpugetregs()... perhaps we just 2139 * have too many layers. 2140 */ 2141 curthread->td_pcb->pcb_flags &= ~PCB_FPUINITDONE; 2142 intr_restore(s); 2143 } 2144 2145 int 2146 fill_dbregs(struct thread *td, struct dbreg *dbregs) 2147 { 2148 struct pcb *pcb; 2149 2150 if (td == NULL) { 2151 dbregs->dr[0] = rdr0(); 2152 dbregs->dr[1] = rdr1(); 2153 dbregs->dr[2] = rdr2(); 2154 dbregs->dr[3] = rdr3(); 2155 dbregs->dr[6] = rdr6(); 2156 dbregs->dr[7] = rdr7(); 2157 } else { 2158 pcb = td->td_pcb; 2159 dbregs->dr[0] = pcb->pcb_dr0; 2160 dbregs->dr[1] = pcb->pcb_dr1; 2161 dbregs->dr[2] = pcb->pcb_dr2; 2162 dbregs->dr[3] = pcb->pcb_dr3; 2163 dbregs->dr[6] = pcb->pcb_dr6; 2164 dbregs->dr[7] = pcb->pcb_dr7; 2165 } 2166 dbregs->dr[4] = 0; 2167 dbregs->dr[5] = 0; 2168 dbregs->dr[8] = 0; 2169 dbregs->dr[9] = 0; 2170 dbregs->dr[10] = 0; 2171 dbregs->dr[11] = 0; 2172 dbregs->dr[12] = 0; 2173 dbregs->dr[13] = 0; 2174 dbregs->dr[14] = 0; 2175 dbregs->dr[15] = 0; 2176 return (0); 2177 } 2178 2179 int 2180 set_dbregs(struct thread *td, struct dbreg *dbregs) 2181 { 2182 struct pcb *pcb; 2183 int i; 2184 2185 if (td == NULL) { 2186 load_dr0(dbregs->dr[0]); 2187 load_dr1(dbregs->dr[1]); 2188 load_dr2(dbregs->dr[2]); 2189 load_dr3(dbregs->dr[3]); 2190 load_dr6(dbregs->dr[6]); 2191 load_dr7(dbregs->dr[7]); 2192 } else { 2193 /* 2194 * Don't let an illegal value for dr7 get set. Specifically, 2195 * check for undefined settings. Setting these bit patterns 2196 * result in undefined behaviour and can lead to an unexpected 2197 * TRCTRAP or a general protection fault right here. 2198 * Upper bits of dr6 and dr7 must not be set 2199 */ 2200 for (i = 0; i < 4; i++) { 2201 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02) 2202 return (EINVAL); 2203 if (td->td_frame->tf_cs == _ucode32sel && 2204 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8) 2205 return (EINVAL); 2206 } 2207 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 || 2208 (dbregs->dr[7] & 0xffffffff00000000ul) != 0) 2209 return (EINVAL); 2210 2211 pcb = td->td_pcb; 2212 2213 /* 2214 * Don't let a process set a breakpoint that is not within the 2215 * process's address space. If a process could do this, it 2216 * could halt the system by setting a breakpoint in the kernel 2217 * (if ddb was enabled). Thus, we need to check to make sure 2218 * that no breakpoints are being enabled for addresses outside 2219 * process's address space. 2220 * 2221 * XXX - what about when the watched area of the user's 2222 * address space is written into from within the kernel 2223 * ... wouldn't that still cause a breakpoint to be generated 2224 * from within kernel mode? 2225 */ 2226 2227 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) { 2228 /* dr0 is enabled */ 2229 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS) 2230 return (EINVAL); 2231 } 2232 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) { 2233 /* dr1 is enabled */ 2234 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS) 2235 return (EINVAL); 2236 } 2237 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) { 2238 /* dr2 is enabled */ 2239 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS) 2240 return (EINVAL); 2241 } 2242 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) { 2243 /* dr3 is enabled */ 2244 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS) 2245 return (EINVAL); 2246 } 2247 2248 pcb->pcb_dr0 = dbregs->dr[0]; 2249 pcb->pcb_dr1 = dbregs->dr[1]; 2250 pcb->pcb_dr2 = dbregs->dr[2]; 2251 pcb->pcb_dr3 = dbregs->dr[3]; 2252 pcb->pcb_dr6 = dbregs->dr[6]; 2253 pcb->pcb_dr7 = dbregs->dr[7]; 2254 2255 pcb->pcb_flags |= PCB_DBREGS; 2256 } 2257 2258 return (0); 2259 } 2260 2261 void 2262 reset_dbregs(void) 2263 { 2264 2265 load_dr7(0); /* Turn off the control bits first */ 2266 load_dr0(0); 2267 load_dr1(0); 2268 load_dr2(0); 2269 load_dr3(0); 2270 load_dr6(0); 2271 } 2272 2273 /* 2274 * Return > 0 if a hardware breakpoint has been hit, and the 2275 * breakpoint was in user space. Return 0, otherwise. 2276 */ 2277 int 2278 user_dbreg_trap(void) 2279 { 2280 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2281 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2282 int nbp; /* number of breakpoints that triggered */ 2283 caddr_t addr[4]; /* breakpoint addresses */ 2284 int i; 2285 2286 dr7 = rdr7(); 2287 if ((dr7 & 0x000000ff) == 0) { 2288 /* 2289 * all GE and LE bits in the dr7 register are zero, 2290 * thus the trap couldn't have been caused by the 2291 * hardware debug registers 2292 */ 2293 return 0; 2294 } 2295 2296 nbp = 0; 2297 dr6 = rdr6(); 2298 bp = dr6 & 0x0000000f; 2299 2300 if (!bp) { 2301 /* 2302 * None of the breakpoint bits are set meaning this 2303 * trap was not caused by any of the debug registers 2304 */ 2305 return 0; 2306 } 2307 2308 /* 2309 * at least one of the breakpoints were hit, check to see 2310 * which ones and if any of them are user space addresses 2311 */ 2312 2313 if (bp & 0x01) { 2314 addr[nbp++] = (caddr_t)rdr0(); 2315 } 2316 if (bp & 0x02) { 2317 addr[nbp++] = (caddr_t)rdr1(); 2318 } 2319 if (bp & 0x04) { 2320 addr[nbp++] = (caddr_t)rdr2(); 2321 } 2322 if (bp & 0x08) { 2323 addr[nbp++] = (caddr_t)rdr3(); 2324 } 2325 2326 for (i = 0; i < nbp; i++) { 2327 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) { 2328 /* 2329 * addr[i] is in user space 2330 */ 2331 return nbp; 2332 } 2333 } 2334 2335 /* 2336 * None of the breakpoints are in user space. 2337 */ 2338 return 0; 2339 } 2340 2341 #ifdef KDB 2342 2343 /* 2344 * Provide inb() and outb() as functions. They are normally only available as 2345 * inline functions, thus cannot be called from the debugger. 2346 */ 2347 2348 /* silence compiler warnings */ 2349 u_char inb_(u_short); 2350 void outb_(u_short, u_char); 2351 2352 u_char 2353 inb_(u_short port) 2354 { 2355 return inb(port); 2356 } 2357 2358 void 2359 outb_(u_short port, u_char data) 2360 { 2361 outb(port, data); 2362 } 2363 2364 #endif /* KDB */
Cache object: 70eb592588155a90853051b64890a2ca
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