1 /*-
2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
39 */
40
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD: releng/9.1/sys/amd64/amd64/machdep.c 235260 2012-05-11 04:10:23Z attilio $");
43
44 #include "opt_atalk.h"
45 #include "opt_atpic.h"
46 #include "opt_compat.h"
47 #include "opt_cpu.h"
48 #include "opt_ddb.h"
49 #include "opt_inet.h"
50 #include "opt_ipx.h"
51 #include "opt_isa.h"
52 #include "opt_kstack_pages.h"
53 #include "opt_maxmem.h"
54 #include "opt_mp_watchdog.h"
55 #include "opt_perfmon.h"
56 #include "opt_sched.h"
57 #include "opt_kdtrace.h"
58
59 #include <sys/param.h>
60 #include <sys/proc.h>
61 #include <sys/systm.h>
62 #include <sys/bio.h>
63 #include <sys/buf.h>
64 #include <sys/bus.h>
65 #include <sys/callout.h>
66 #include <sys/cons.h>
67 #include <sys/cpu.h>
68 #include <sys/eventhandler.h>
69 #include <sys/exec.h>
70 #include <sys/imgact.h>
71 #include <sys/kdb.h>
72 #include <sys/kernel.h>
73 #include <sys/ktr.h>
74 #include <sys/linker.h>
75 #include <sys/lock.h>
76 #include <sys/malloc.h>
77 #include <sys/msgbuf.h>
78 #include <sys/mutex.h>
79 #include <sys/pcpu.h>
80 #include <sys/ptrace.h>
81 #include <sys/reboot.h>
82 #include <sys/sched.h>
83 #include <sys/signalvar.h>
84 #ifdef SMP
85 #include <sys/smp.h>
86 #endif
87 #include <sys/syscallsubr.h>
88 #include <sys/sysctl.h>
89 #include <sys/sysent.h>
90 #include <sys/sysproto.h>
91 #include <sys/ucontext.h>
92 #include <sys/vmmeter.h>
93
94 #include <vm/vm.h>
95 #include <vm/vm_extern.h>
96 #include <vm/vm_kern.h>
97 #include <vm/vm_page.h>
98 #include <vm/vm_map.h>
99 #include <vm/vm_object.h>
100 #include <vm/vm_pager.h>
101 #include <vm/vm_param.h>
102
103 #ifdef DDB
104 #ifndef KDB
105 #error KDB must be enabled in order for DDB to work!
106 #endif
107 #include <ddb/ddb.h>
108 #include <ddb/db_sym.h>
109 #endif
110
111 #include <net/netisr.h>
112
113 #include <machine/clock.h>
114 #include <machine/cpu.h>
115 #include <machine/cputypes.h>
116 #include <machine/intr_machdep.h>
117 #include <x86/mca.h>
118 #include <machine/md_var.h>
119 #include <machine/metadata.h>
120 #include <machine/mp_watchdog.h>
121 #include <machine/pc/bios.h>
122 #include <machine/pcb.h>
123 #include <machine/proc.h>
124 #include <machine/reg.h>
125 #include <machine/sigframe.h>
126 #include <machine/specialreg.h>
127 #ifdef PERFMON
128 #include <machine/perfmon.h>
129 #endif
130 #include <machine/tss.h>
131 #ifdef SMP
132 #include <machine/smp.h>
133 #endif
134
135 #ifdef DEV_ATPIC
136 #include <x86/isa/icu.h>
137 #else
138 #include <machine/apicvar.h>
139 #endif
140
141 #include <isa/isareg.h>
142 #include <isa/rtc.h>
143
144 /* Sanity check for __curthread() */
145 CTASSERT(offsetof(struct pcpu, pc_curthread) == 0);
146
147 extern u_int64_t hammer_time(u_int64_t, u_int64_t);
148
149 extern void printcpuinfo(void); /* XXX header file */
150 extern void identify_cpu(void);
151 extern void panicifcpuunsupported(void);
152
153 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
154 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
155
156 static void cpu_startup(void *);
157 static void get_fpcontext(struct thread *td, mcontext_t *mcp,
158 char *xfpusave, size_t xfpusave_len);
159 static int set_fpcontext(struct thread *td, const mcontext_t *mcp,
160 char *xfpustate, size_t xfpustate_len);
161 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
162
163 /*
164 * The file "conf/ldscript.amd64" defines the symbol "kernphys". Its value is
165 * the physical address at which the kernel is loaded.
166 */
167 extern char kernphys[];
168 #ifdef DDB
169 extern vm_offset_t ksym_start, ksym_end;
170 #endif
171
172 struct msgbuf *msgbufp;
173
174 /* Intel ICH registers */
175 #define ICH_PMBASE 0x400
176 #define ICH_SMI_EN ICH_PMBASE + 0x30
177
178 int _udatasel, _ucodesel, _ucode32sel, _ufssel, _ugssel;
179
180 int cold = 1;
181
182 long Maxmem = 0;
183 long realmem = 0;
184
185 /*
186 * The number of PHYSMAP entries must be one less than the number of
187 * PHYSSEG entries because the PHYSMAP entry that spans the largest
188 * physical address that is accessible by ISA DMA is split into two
189 * PHYSSEG entries.
190 */
191 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
192
193 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
194 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
195
196 /* must be 2 less so 0 0 can signal end of chunks */
197 #define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2)
198 #define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2)
199
200 struct kva_md_info kmi;
201
202 static struct trapframe proc0_tf;
203 struct region_descriptor r_gdt, r_idt;
204
205 struct pcpu __pcpu[MAXCPU];
206
207 struct mtx icu_lock;
208
209 struct mtx dt_lock; /* lock for GDT and LDT */
210
211 static void
212 cpu_startup(dummy)
213 void *dummy;
214 {
215 uintmax_t memsize;
216 char *sysenv;
217
218 /*
219 * On MacBooks, we need to disallow the legacy USB circuit to
220 * generate an SMI# because this can cause several problems,
221 * namely: incorrect CPU frequency detection and failure to
222 * start the APs.
223 * We do this by disabling a bit in the SMI_EN (SMI Control and
224 * Enable register) of the Intel ICH LPC Interface Bridge.
225 */
226 sysenv = getenv("smbios.system.product");
227 if (sysenv != NULL) {
228 if (strncmp(sysenv, "MacBook1,1", 10) == 0 ||
229 strncmp(sysenv, "MacBook3,1", 10) == 0 ||
230 strncmp(sysenv, "MacBookPro1,1", 13) == 0 ||
231 strncmp(sysenv, "MacBookPro1,2", 13) == 0 ||
232 strncmp(sysenv, "MacBookPro3,1", 13) == 0 ||
233 strncmp(sysenv, "Macmini1,1", 10) == 0) {
234 if (bootverbose)
235 printf("Disabling LEGACY_USB_EN bit on "
236 "Intel ICH.\n");
237 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8);
238 }
239 freeenv(sysenv);
240 }
241
242 /*
243 * Good {morning,afternoon,evening,night}.
244 */
245 startrtclock();
246 printcpuinfo();
247 panicifcpuunsupported();
248 #ifdef PERFMON
249 perfmon_init();
250 #endif
251 realmem = Maxmem;
252
253 /*
254 * Display physical memory if SMBIOS reports reasonable amount.
255 */
256 memsize = 0;
257 sysenv = getenv("smbios.memory.enabled");
258 if (sysenv != NULL) {
259 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10;
260 freeenv(sysenv);
261 }
262 if (memsize < ptoa((uintmax_t)cnt.v_free_count))
263 memsize = ptoa((uintmax_t)Maxmem);
264 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20);
265
266 /*
267 * Display any holes after the first chunk of extended memory.
268 */
269 if (bootverbose) {
270 int indx;
271
272 printf("Physical memory chunk(s):\n");
273 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
274 vm_paddr_t size;
275
276 size = phys_avail[indx + 1] - phys_avail[indx];
277 printf(
278 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n",
279 (uintmax_t)phys_avail[indx],
280 (uintmax_t)phys_avail[indx + 1] - 1,
281 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE);
282 }
283 }
284
285 vm_ksubmap_init(&kmi);
286
287 printf("avail memory = %ju (%ju MB)\n",
288 ptoa((uintmax_t)cnt.v_free_count),
289 ptoa((uintmax_t)cnt.v_free_count) / 1048576);
290
291 /*
292 * Set up buffers, so they can be used to read disk labels.
293 */
294 bufinit();
295 vm_pager_bufferinit();
296
297 cpu_setregs();
298
299 /*
300 * Add BSP as an interrupt target.
301 */
302 intr_add_cpu(0);
303 }
304
305 /*
306 * Send an interrupt to process.
307 *
308 * Stack is set up to allow sigcode stored
309 * at top to call routine, followed by call
310 * to sigreturn routine below. After sigreturn
311 * resets the signal mask, the stack, and the
312 * frame pointer, it returns to the user
313 * specified pc, psl.
314 */
315 void
316 sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
317 {
318 struct sigframe sf, *sfp;
319 struct pcb *pcb;
320 struct proc *p;
321 struct thread *td;
322 struct sigacts *psp;
323 char *sp;
324 struct trapframe *regs;
325 char *xfpusave;
326 size_t xfpusave_len;
327 int sig;
328 int oonstack;
329
330 td = curthread;
331 pcb = td->td_pcb;
332 p = td->td_proc;
333 PROC_LOCK_ASSERT(p, MA_OWNED);
334 sig = ksi->ksi_signo;
335 psp = p->p_sigacts;
336 mtx_assert(&psp->ps_mtx, MA_OWNED);
337 regs = td->td_frame;
338 oonstack = sigonstack(regs->tf_rsp);
339
340 if (cpu_max_ext_state_size > sizeof(struct savefpu) && use_xsave) {
341 xfpusave_len = cpu_max_ext_state_size - sizeof(struct savefpu);
342 xfpusave = __builtin_alloca(xfpusave_len);
343 } else {
344 xfpusave_len = 0;
345 xfpusave = NULL;
346 }
347
348 /* Save user context. */
349 bzero(&sf, sizeof(sf));
350 sf.sf_uc.uc_sigmask = *mask;
351 sf.sf_uc.uc_stack = td->td_sigstk;
352 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK)
353 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE;
354 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0;
355 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs));
356 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */
357 get_fpcontext(td, &sf.sf_uc.uc_mcontext, xfpusave, xfpusave_len);
358 fpstate_drop(td);
359 sf.sf_uc.uc_mcontext.mc_fsbase = pcb->pcb_fsbase;
360 sf.sf_uc.uc_mcontext.mc_gsbase = pcb->pcb_gsbase;
361 bzero(sf.sf_uc.uc_mcontext.mc_spare,
362 sizeof(sf.sf_uc.uc_mcontext.mc_spare));
363 bzero(sf.sf_uc.__spare__, sizeof(sf.sf_uc.__spare__));
364
365 /* Allocate space for the signal handler context. */
366 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
367 SIGISMEMBER(psp->ps_sigonstack, sig)) {
368 sp = td->td_sigstk.ss_sp + td->td_sigstk.ss_size;
369 #if defined(COMPAT_43)
370 td->td_sigstk.ss_flags |= SS_ONSTACK;
371 #endif
372 } else
373 sp = (char *)regs->tf_rsp - 128;
374 if (xfpusave != NULL) {
375 sp -= xfpusave_len;
376 sp = (char *)((unsigned long)sp & ~0x3Ful);
377 sf.sf_uc.uc_mcontext.mc_xfpustate = (register_t)sp;
378 }
379 sp -= sizeof(struct sigframe);
380 /* Align to 16 bytes. */
381 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul);
382
383 /* Translate the signal if appropriate. */
384 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize)
385 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
386
387 /* Build the argument list for the signal handler. */
388 regs->tf_rdi = sig; /* arg 1 in %rdi */
389 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */
390 bzero(&sf.sf_si, sizeof(sf.sf_si));
391 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
392 /* Signal handler installed with SA_SIGINFO. */
393 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */
394 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
395
396 /* Fill in POSIX parts */
397 sf.sf_si = ksi->ksi_info;
398 sf.sf_si.si_signo = sig; /* maybe a translated signal */
399 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */
400 } else {
401 /* Old FreeBSD-style arguments. */
402 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */
403 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */
404 sf.sf_ahu.sf_handler = catcher;
405 }
406 mtx_unlock(&psp->ps_mtx);
407 PROC_UNLOCK(p);
408
409 /*
410 * Copy the sigframe out to the user's stack.
411 */
412 if (copyout(&sf, sfp, sizeof(*sfp)) != 0 ||
413 (xfpusave != NULL && copyout(xfpusave,
414 (void *)sf.sf_uc.uc_mcontext.mc_xfpustate, xfpusave_len)
415 != 0)) {
416 #ifdef DEBUG
417 printf("process %ld has trashed its stack\n", (long)p->p_pid);
418 #endif
419 PROC_LOCK(p);
420 sigexit(td, SIGILL);
421 }
422
423 regs->tf_rsp = (long)sfp;
424 regs->tf_rip = p->p_sysent->sv_sigcode_base;
425 regs->tf_rflags &= ~(PSL_T | PSL_D);
426 regs->tf_cs = _ucodesel;
427 regs->tf_ds = _udatasel;
428 regs->tf_es = _udatasel;
429 regs->tf_fs = _ufssel;
430 regs->tf_gs = _ugssel;
431 regs->tf_flags = TF_HASSEGS;
432 set_pcb_flags(pcb, PCB_FULL_IRET);
433 PROC_LOCK(p);
434 mtx_lock(&psp->ps_mtx);
435 }
436
437 /*
438 * System call to cleanup state after a signal
439 * has been taken. Reset signal mask and
440 * stack state from context left by sendsig (above).
441 * Return to previous pc and psl as specified by
442 * context left by sendsig. Check carefully to
443 * make sure that the user has not modified the
444 * state to gain improper privileges.
445 *
446 * MPSAFE
447 */
448 int
449 sys_sigreturn(td, uap)
450 struct thread *td;
451 struct sigreturn_args /* {
452 const struct __ucontext *sigcntxp;
453 } */ *uap;
454 {
455 ucontext_t uc;
456 struct pcb *pcb;
457 struct proc *p;
458 struct trapframe *regs;
459 ucontext_t *ucp;
460 char *xfpustate;
461 size_t xfpustate_len;
462 long rflags;
463 int cs, error, ret;
464 ksiginfo_t ksi;
465
466 pcb = td->td_pcb;
467 p = td->td_proc;
468
469 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
470 if (error != 0) {
471 uprintf("pid %d (%s): sigreturn copyin failed\n",
472 p->p_pid, td->td_name);
473 return (error);
474 }
475 ucp = &uc;
476 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) {
477 uprintf("pid %d (%s): sigreturn mc_flags %x\n", p->p_pid,
478 td->td_name, ucp->uc_mcontext.mc_flags);
479 return (EINVAL);
480 }
481 regs = td->td_frame;
482 rflags = ucp->uc_mcontext.mc_rflags;
483 /*
484 * Don't allow users to change privileged or reserved flags.
485 */
486 /*
487 * XXX do allow users to change the privileged flag PSL_RF.
488 * The cpu sets PSL_RF in tf_rflags for faults. Debuggers
489 * should sometimes set it there too. tf_rflags is kept in
490 * the signal context during signal handling and there is no
491 * other place to remember it, so the PSL_RF bit may be
492 * corrupted by the signal handler without us knowing.
493 * Corruption of the PSL_RF bit at worst causes one more or
494 * one less debugger trap, so allowing it is fairly harmless.
495 */
496 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
497 uprintf("pid %d (%s): sigreturn rflags = 0x%lx\n", p->p_pid,
498 td->td_name, rflags);
499 return (EINVAL);
500 }
501
502 /*
503 * Don't allow users to load a valid privileged %cs. Let the
504 * hardware check for invalid selectors, excess privilege in
505 * other selectors, invalid %eip's and invalid %esp's.
506 */
507 cs = ucp->uc_mcontext.mc_cs;
508 if (!CS_SECURE(cs)) {
509 uprintf("pid %d (%s): sigreturn cs = 0x%x\n", p->p_pid,
510 td->td_name, cs);
511 ksiginfo_init_trap(&ksi);
512 ksi.ksi_signo = SIGBUS;
513 ksi.ksi_code = BUS_OBJERR;
514 ksi.ksi_trapno = T_PROTFLT;
515 ksi.ksi_addr = (void *)regs->tf_rip;
516 trapsignal(td, &ksi);
517 return (EINVAL);
518 }
519
520 if ((uc.uc_mcontext.mc_flags & _MC_HASFPXSTATE) != 0) {
521 xfpustate_len = uc.uc_mcontext.mc_xfpustate_len;
522 if (xfpustate_len > cpu_max_ext_state_size -
523 sizeof(struct savefpu)) {
524 uprintf("pid %d (%s): sigreturn xfpusave_len = 0x%zx\n",
525 p->p_pid, td->td_name, xfpustate_len);
526 return (EINVAL);
527 }
528 xfpustate = __builtin_alloca(xfpustate_len);
529 error = copyin((const void *)uc.uc_mcontext.mc_xfpustate,
530 xfpustate, xfpustate_len);
531 if (error != 0) {
532 uprintf(
533 "pid %d (%s): sigreturn copying xfpustate failed\n",
534 p->p_pid, td->td_name);
535 return (error);
536 }
537 } else {
538 xfpustate = NULL;
539 xfpustate_len = 0;
540 }
541 ret = set_fpcontext(td, &ucp->uc_mcontext, xfpustate, xfpustate_len);
542 if (ret != 0) {
543 uprintf("pid %d (%s): sigreturn set_fpcontext err %d\n",
544 p->p_pid, td->td_name, ret);
545 return (ret);
546 }
547 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs));
548 pcb->pcb_fsbase = ucp->uc_mcontext.mc_fsbase;
549 pcb->pcb_gsbase = ucp->uc_mcontext.mc_gsbase;
550
551 #if defined(COMPAT_43)
552 if (ucp->uc_mcontext.mc_onstack & 1)
553 td->td_sigstk.ss_flags |= SS_ONSTACK;
554 else
555 td->td_sigstk.ss_flags &= ~SS_ONSTACK;
556 #endif
557
558 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0);
559 set_pcb_flags(pcb, PCB_FULL_IRET);
560 return (EJUSTRETURN);
561 }
562
563 #ifdef COMPAT_FREEBSD4
564 int
565 freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap)
566 {
567
568 return sys_sigreturn(td, (struct sigreturn_args *)uap);
569 }
570 #endif
571
572
573 /*
574 * Machine dependent boot() routine
575 *
576 * I haven't seen anything to put here yet
577 * Possibly some stuff might be grafted back here from boot()
578 */
579 void
580 cpu_boot(int howto)
581 {
582 }
583
584 /*
585 * Flush the D-cache for non-DMA I/O so that the I-cache can
586 * be made coherent later.
587 */
588 void
589 cpu_flush_dcache(void *ptr, size_t len)
590 {
591 /* Not applicable */
592 }
593
594 /* Get current clock frequency for the given cpu id. */
595 int
596 cpu_est_clockrate(int cpu_id, uint64_t *rate)
597 {
598 uint64_t tsc1, tsc2;
599 uint64_t acnt, mcnt, perf;
600 register_t reg;
601
602 if (pcpu_find(cpu_id) == NULL || rate == NULL)
603 return (EINVAL);
604
605 /*
606 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist,
607 * DELAY(9) based logic fails.
608 */
609 if (tsc_is_invariant && !tsc_perf_stat)
610 return (EOPNOTSUPP);
611
612 #ifdef SMP
613 if (smp_cpus > 1) {
614 /* Schedule ourselves on the indicated cpu. */
615 thread_lock(curthread);
616 sched_bind(curthread, cpu_id);
617 thread_unlock(curthread);
618 }
619 #endif
620
621 /* Calibrate by measuring a short delay. */
622 reg = intr_disable();
623 if (tsc_is_invariant) {
624 wrmsr(MSR_MPERF, 0);
625 wrmsr(MSR_APERF, 0);
626 tsc1 = rdtsc();
627 DELAY(1000);
628 mcnt = rdmsr(MSR_MPERF);
629 acnt = rdmsr(MSR_APERF);
630 tsc2 = rdtsc();
631 intr_restore(reg);
632 perf = 1000 * acnt / mcnt;
633 *rate = (tsc2 - tsc1) * perf;
634 } else {
635 tsc1 = rdtsc();
636 DELAY(1000);
637 tsc2 = rdtsc();
638 intr_restore(reg);
639 *rate = (tsc2 - tsc1) * 1000;
640 }
641
642 #ifdef SMP
643 if (smp_cpus > 1) {
644 thread_lock(curthread);
645 sched_unbind(curthread);
646 thread_unlock(curthread);
647 }
648 #endif
649
650 return (0);
651 }
652
653 /*
654 * Shutdown the CPU as much as possible
655 */
656 void
657 cpu_halt(void)
658 {
659 for (;;)
660 __asm__ ("hlt");
661 }
662
663 void (*cpu_idle_hook)(void) = NULL; /* ACPI idle hook. */
664 static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */
665 static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */
666 TUNABLE_INT("machdep.idle_mwait", &idle_mwait);
667 SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait,
668 0, "Use MONITOR/MWAIT for short idle");
669
670 #define STATE_RUNNING 0x0
671 #define STATE_MWAIT 0x1
672 #define STATE_SLEEPING 0x2
673
674 static void
675 cpu_idle_acpi(int busy)
676 {
677 int *state;
678
679 state = (int *)PCPU_PTR(monitorbuf);
680 *state = STATE_SLEEPING;
681 disable_intr();
682 if (sched_runnable())
683 enable_intr();
684 else if (cpu_idle_hook)
685 cpu_idle_hook();
686 else
687 __asm __volatile("sti; hlt");
688 *state = STATE_RUNNING;
689 }
690
691 static void
692 cpu_idle_hlt(int busy)
693 {
694 int *state;
695
696 state = (int *)PCPU_PTR(monitorbuf);
697 *state = STATE_SLEEPING;
698 /*
699 * We must absolutely guarentee that hlt is the next instruction
700 * after sti or we introduce a timing window.
701 */
702 disable_intr();
703 if (sched_runnable())
704 enable_intr();
705 else
706 __asm __volatile("sti; hlt");
707 *state = STATE_RUNNING;
708 }
709
710 /*
711 * MWAIT cpu power states. Lower 4 bits are sub-states.
712 */
713 #define MWAIT_C0 0xf0
714 #define MWAIT_C1 0x00
715 #define MWAIT_C2 0x10
716 #define MWAIT_C3 0x20
717 #define MWAIT_C4 0x30
718
719 static void
720 cpu_idle_mwait(int busy)
721 {
722 int *state;
723
724 state = (int *)PCPU_PTR(monitorbuf);
725 *state = STATE_MWAIT;
726 if (!sched_runnable()) {
727 cpu_monitor(state, 0, 0);
728 if (*state == STATE_MWAIT)
729 cpu_mwait(0, MWAIT_C1);
730 }
731 *state = STATE_RUNNING;
732 }
733
734 static void
735 cpu_idle_spin(int busy)
736 {
737 int *state;
738 int i;
739
740 state = (int *)PCPU_PTR(monitorbuf);
741 *state = STATE_RUNNING;
742 for (i = 0; i < 1000; i++) {
743 if (sched_runnable())
744 return;
745 cpu_spinwait();
746 }
747 }
748
749 /*
750 * C1E renders the local APIC timer dead, so we disable it by
751 * reading the Interrupt Pending Message register and clearing
752 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
753 *
754 * Reference:
755 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors"
756 * #32559 revision 3.00+
757 */
758 #define MSR_AMDK8_IPM 0xc0010055
759 #define AMDK8_SMIONCMPHALT (1ULL << 27)
760 #define AMDK8_C1EONCMPHALT (1ULL << 28)
761 #define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT)
762
763 static void
764 cpu_probe_amdc1e(void)
765 {
766
767 /*
768 * Detect the presence of C1E capability mostly on latest
769 * dual-cores (or future) k8 family.
770 */
771 if (cpu_vendor_id == CPU_VENDOR_AMD &&
772 (cpu_id & 0x00000f00) == 0x00000f00 &&
773 (cpu_id & 0x0fff0000) >= 0x00040000) {
774 cpu_ident_amdc1e = 1;
775 }
776 }
777
778 void (*cpu_idle_fn)(int) = cpu_idle_acpi;
779
780 void
781 cpu_idle(int busy)
782 {
783 uint64_t msr;
784
785 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
786 busy, curcpu);
787 #ifdef MP_WATCHDOG
788 ap_watchdog(PCPU_GET(cpuid));
789 #endif
790 /* If we are busy - try to use fast methods. */
791 if (busy) {
792 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) {
793 cpu_idle_mwait(busy);
794 goto out;
795 }
796 }
797
798 /* If we have time - switch timers into idle mode. */
799 if (!busy) {
800 critical_enter();
801 cpu_idleclock();
802 }
803
804 /* Apply AMD APIC timer C1E workaround. */
805 if (cpu_ident_amdc1e && cpu_disable_deep_sleep) {
806 msr = rdmsr(MSR_AMDK8_IPM);
807 if (msr & AMDK8_CMPHALT)
808 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT);
809 }
810
811 /* Call main idle method. */
812 cpu_idle_fn(busy);
813
814 /* Switch timers mack into active mode. */
815 if (!busy) {
816 cpu_activeclock();
817 critical_exit();
818 }
819 out:
820 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
821 busy, curcpu);
822 }
823
824 int
825 cpu_idle_wakeup(int cpu)
826 {
827 struct pcpu *pcpu;
828 int *state;
829
830 pcpu = pcpu_find(cpu);
831 state = (int *)pcpu->pc_monitorbuf;
832 /*
833 * This doesn't need to be atomic since missing the race will
834 * simply result in unnecessary IPIs.
835 */
836 if (*state == STATE_SLEEPING)
837 return (0);
838 if (*state == STATE_MWAIT)
839 *state = STATE_RUNNING;
840 return (1);
841 }
842
843 /*
844 * Ordered by speed/power consumption.
845 */
846 struct {
847 void *id_fn;
848 char *id_name;
849 } idle_tbl[] = {
850 { cpu_idle_spin, "spin" },
851 { cpu_idle_mwait, "mwait" },
852 { cpu_idle_hlt, "hlt" },
853 { cpu_idle_acpi, "acpi" },
854 { NULL, NULL }
855 };
856
857 static int
858 idle_sysctl_available(SYSCTL_HANDLER_ARGS)
859 {
860 char *avail, *p;
861 int error;
862 int i;
863
864 avail = malloc(256, M_TEMP, M_WAITOK);
865 p = avail;
866 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
867 if (strstr(idle_tbl[i].id_name, "mwait") &&
868 (cpu_feature2 & CPUID2_MON) == 0)
869 continue;
870 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
871 cpu_idle_hook == NULL)
872 continue;
873 p += sprintf(p, "%s%s", p != avail ? ", " : "",
874 idle_tbl[i].id_name);
875 }
876 error = sysctl_handle_string(oidp, avail, 0, req);
877 free(avail, M_TEMP);
878 return (error);
879 }
880
881 SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD,
882 0, 0, idle_sysctl_available, "A", "list of available idle functions");
883
884 static int
885 idle_sysctl(SYSCTL_HANDLER_ARGS)
886 {
887 char buf[16];
888 int error;
889 char *p;
890 int i;
891
892 p = "unknown";
893 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
894 if (idle_tbl[i].id_fn == cpu_idle_fn) {
895 p = idle_tbl[i].id_name;
896 break;
897 }
898 }
899 strncpy(buf, p, sizeof(buf));
900 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
901 if (error != 0 || req->newptr == NULL)
902 return (error);
903 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
904 if (strstr(idle_tbl[i].id_name, "mwait") &&
905 (cpu_feature2 & CPUID2_MON) == 0)
906 continue;
907 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
908 cpu_idle_hook == NULL)
909 continue;
910 if (strcmp(idle_tbl[i].id_name, buf))
911 continue;
912 cpu_idle_fn = idle_tbl[i].id_fn;
913 return (0);
914 }
915 return (EINVAL);
916 }
917
918 SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0,
919 idle_sysctl, "A", "currently selected idle function");
920
921 /*
922 * Reset registers to default values on exec.
923 */
924 void
925 exec_setregs(struct thread *td, struct image_params *imgp, u_long stack)
926 {
927 struct trapframe *regs = td->td_frame;
928 struct pcb *pcb = td->td_pcb;
929
930 mtx_lock(&dt_lock);
931 if (td->td_proc->p_md.md_ldt != NULL)
932 user_ldt_free(td);
933 else
934 mtx_unlock(&dt_lock);
935
936 pcb->pcb_fsbase = 0;
937 pcb->pcb_gsbase = 0;
938 clear_pcb_flags(pcb, PCB_32BIT | PCB_GS32BIT);
939 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__;
940 set_pcb_flags(pcb, PCB_FULL_IRET);
941
942 bzero((char *)regs, sizeof(struct trapframe));
943 regs->tf_rip = imgp->entry_addr;
944 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8;
945 regs->tf_rdi = stack; /* argv */
946 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
947 regs->tf_ss = _udatasel;
948 regs->tf_cs = _ucodesel;
949 regs->tf_ds = _udatasel;
950 regs->tf_es = _udatasel;
951 regs->tf_fs = _ufssel;
952 regs->tf_gs = _ugssel;
953 regs->tf_flags = TF_HASSEGS;
954 td->td_retval[1] = 0;
955
956 /*
957 * Reset the hardware debug registers if they were in use.
958 * They won't have any meaning for the newly exec'd process.
959 */
960 if (pcb->pcb_flags & PCB_DBREGS) {
961 pcb->pcb_dr0 = 0;
962 pcb->pcb_dr1 = 0;
963 pcb->pcb_dr2 = 0;
964 pcb->pcb_dr3 = 0;
965 pcb->pcb_dr6 = 0;
966 pcb->pcb_dr7 = 0;
967 if (pcb == PCPU_GET(curpcb)) {
968 /*
969 * Clear the debug registers on the running
970 * CPU, otherwise they will end up affecting
971 * the next process we switch to.
972 */
973 reset_dbregs();
974 }
975 clear_pcb_flags(pcb, PCB_DBREGS);
976 }
977
978 /*
979 * Drop the FP state if we hold it, so that the process gets a
980 * clean FP state if it uses the FPU again.
981 */
982 fpstate_drop(td);
983 }
984
985 void
986 cpu_setregs(void)
987 {
988 register_t cr0;
989
990 cr0 = rcr0();
991 /*
992 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the
993 * BSP. See the comments there about why we set them.
994 */
995 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM;
996 load_cr0(cr0);
997 }
998
999 /*
1000 * Initialize amd64 and configure to run kernel
1001 */
1002
1003 /*
1004 * Initialize segments & interrupt table
1005 */
1006
1007 struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */
1008 static struct gate_descriptor idt0[NIDT];
1009 struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
1010
1011 static char dblfault_stack[PAGE_SIZE] __aligned(16);
1012
1013 static char nmi0_stack[PAGE_SIZE] __aligned(16);
1014 CTASSERT(sizeof(struct nmi_pcpu) == 16);
1015
1016 struct amd64tss common_tss[MAXCPU];
1017
1018 /*
1019 * Software prototypes -- in more palatable form.
1020 *
1021 * Keep GUFS32, GUGS32, GUCODE32 and GUDATA at the same
1022 * slots as corresponding segments for i386 kernel.
1023 */
1024 struct soft_segment_descriptor gdt_segs[] = {
1025 /* GNULL_SEL 0 Null Descriptor */
1026 { .ssd_base = 0x0,
1027 .ssd_limit = 0x0,
1028 .ssd_type = 0,
1029 .ssd_dpl = 0,
1030 .ssd_p = 0,
1031 .ssd_long = 0,
1032 .ssd_def32 = 0,
1033 .ssd_gran = 0 },
1034 /* GNULL2_SEL 1 Null Descriptor */
1035 { .ssd_base = 0x0,
1036 .ssd_limit = 0x0,
1037 .ssd_type = 0,
1038 .ssd_dpl = 0,
1039 .ssd_p = 0,
1040 .ssd_long = 0,
1041 .ssd_def32 = 0,
1042 .ssd_gran = 0 },
1043 /* GUFS32_SEL 2 32 bit %gs Descriptor for user */
1044 { .ssd_base = 0x0,
1045 .ssd_limit = 0xfffff,
1046 .ssd_type = SDT_MEMRWA,
1047 .ssd_dpl = SEL_UPL,
1048 .ssd_p = 1,
1049 .ssd_long = 0,
1050 .ssd_def32 = 1,
1051 .ssd_gran = 1 },
1052 /* GUGS32_SEL 3 32 bit %fs Descriptor for user */
1053 { .ssd_base = 0x0,
1054 .ssd_limit = 0xfffff,
1055 .ssd_type = SDT_MEMRWA,
1056 .ssd_dpl = SEL_UPL,
1057 .ssd_p = 1,
1058 .ssd_long = 0,
1059 .ssd_def32 = 1,
1060 .ssd_gran = 1 },
1061 /* GCODE_SEL 4 Code Descriptor for kernel */
1062 { .ssd_base = 0x0,
1063 .ssd_limit = 0xfffff,
1064 .ssd_type = SDT_MEMERA,
1065 .ssd_dpl = SEL_KPL,
1066 .ssd_p = 1,
1067 .ssd_long = 1,
1068 .ssd_def32 = 0,
1069 .ssd_gran = 1 },
1070 /* GDATA_SEL 5 Data Descriptor for kernel */
1071 { .ssd_base = 0x0,
1072 .ssd_limit = 0xfffff,
1073 .ssd_type = SDT_MEMRWA,
1074 .ssd_dpl = SEL_KPL,
1075 .ssd_p = 1,
1076 .ssd_long = 1,
1077 .ssd_def32 = 0,
1078 .ssd_gran = 1 },
1079 /* GUCODE32_SEL 6 32 bit Code Descriptor for user */
1080 { .ssd_base = 0x0,
1081 .ssd_limit = 0xfffff,
1082 .ssd_type = SDT_MEMERA,
1083 .ssd_dpl = SEL_UPL,
1084 .ssd_p = 1,
1085 .ssd_long = 0,
1086 .ssd_def32 = 1,
1087 .ssd_gran = 1 },
1088 /* GUDATA_SEL 7 32/64 bit Data Descriptor for user */
1089 { .ssd_base = 0x0,
1090 .ssd_limit = 0xfffff,
1091 .ssd_type = SDT_MEMRWA,
1092 .ssd_dpl = SEL_UPL,
1093 .ssd_p = 1,
1094 .ssd_long = 0,
1095 .ssd_def32 = 1,
1096 .ssd_gran = 1 },
1097 /* GUCODE_SEL 8 64 bit Code Descriptor for user */
1098 { .ssd_base = 0x0,
1099 .ssd_limit = 0xfffff,
1100 .ssd_type = SDT_MEMERA,
1101 .ssd_dpl = SEL_UPL,
1102 .ssd_p = 1,
1103 .ssd_long = 1,
1104 .ssd_def32 = 0,
1105 .ssd_gran = 1 },
1106 /* GPROC0_SEL 9 Proc 0 Tss Descriptor */
1107 { .ssd_base = 0x0,
1108 .ssd_limit = sizeof(struct amd64tss) + IOPAGES * PAGE_SIZE - 1,
1109 .ssd_type = SDT_SYSTSS,
1110 .ssd_dpl = SEL_KPL,
1111 .ssd_p = 1,
1112 .ssd_long = 0,
1113 .ssd_def32 = 0,
1114 .ssd_gran = 0 },
1115 /* Actually, the TSS is a system descriptor which is double size */
1116 { .ssd_base = 0x0,
1117 .ssd_limit = 0x0,
1118 .ssd_type = 0,
1119 .ssd_dpl = 0,
1120 .ssd_p = 0,
1121 .ssd_long = 0,
1122 .ssd_def32 = 0,
1123 .ssd_gran = 0 },
1124 /* GUSERLDT_SEL 11 LDT Descriptor */
1125 { .ssd_base = 0x0,
1126 .ssd_limit = 0x0,
1127 .ssd_type = 0,
1128 .ssd_dpl = 0,
1129 .ssd_p = 0,
1130 .ssd_long = 0,
1131 .ssd_def32 = 0,
1132 .ssd_gran = 0 },
1133 /* GUSERLDT_SEL 12 LDT Descriptor, double size */
1134 { .ssd_base = 0x0,
1135 .ssd_limit = 0x0,
1136 .ssd_type = 0,
1137 .ssd_dpl = 0,
1138 .ssd_p = 0,
1139 .ssd_long = 0,
1140 .ssd_def32 = 0,
1141 .ssd_gran = 0 },
1142 };
1143
1144 void
1145 setidt(idx, func, typ, dpl, ist)
1146 int idx;
1147 inthand_t *func;
1148 int typ;
1149 int dpl;
1150 int ist;
1151 {
1152 struct gate_descriptor *ip;
1153
1154 ip = idt + idx;
1155 ip->gd_looffset = (uintptr_t)func;
1156 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1157 ip->gd_ist = ist;
1158 ip->gd_xx = 0;
1159 ip->gd_type = typ;
1160 ip->gd_dpl = dpl;
1161 ip->gd_p = 1;
1162 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1163 }
1164
1165 extern inthand_t
1166 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1167 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1168 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1169 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1170 IDTVEC(xmm), IDTVEC(dblfault),
1171 #ifdef KDTRACE_HOOKS
1172 IDTVEC(dtrace_ret),
1173 #endif
1174 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1175
1176 #ifdef DDB
1177 /*
1178 * Display the index and function name of any IDT entries that don't use
1179 * the default 'rsvd' entry point.
1180 */
1181 DB_SHOW_COMMAND(idt, db_show_idt)
1182 {
1183 struct gate_descriptor *ip;
1184 int idx;
1185 uintptr_t func;
1186
1187 ip = idt;
1188 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) {
1189 func = ((long)ip->gd_hioffset << 16 | ip->gd_looffset);
1190 if (func != (uintptr_t)&IDTVEC(rsvd)) {
1191 db_printf("%3d\t", idx);
1192 db_printsym(func, DB_STGY_PROC);
1193 db_printf("\n");
1194 }
1195 ip++;
1196 }
1197 }
1198 #endif
1199
1200 void
1201 sdtossd(sd, ssd)
1202 struct user_segment_descriptor *sd;
1203 struct soft_segment_descriptor *ssd;
1204 {
1205
1206 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1207 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1208 ssd->ssd_type = sd->sd_type;
1209 ssd->ssd_dpl = sd->sd_dpl;
1210 ssd->ssd_p = sd->sd_p;
1211 ssd->ssd_long = sd->sd_long;
1212 ssd->ssd_def32 = sd->sd_def32;
1213 ssd->ssd_gran = sd->sd_gran;
1214 }
1215
1216 void
1217 ssdtosd(ssd, sd)
1218 struct soft_segment_descriptor *ssd;
1219 struct user_segment_descriptor *sd;
1220 {
1221
1222 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1223 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1224 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1225 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1226 sd->sd_type = ssd->ssd_type;
1227 sd->sd_dpl = ssd->ssd_dpl;
1228 sd->sd_p = ssd->ssd_p;
1229 sd->sd_long = ssd->ssd_long;
1230 sd->sd_def32 = ssd->ssd_def32;
1231 sd->sd_gran = ssd->ssd_gran;
1232 }
1233
1234 void
1235 ssdtosyssd(ssd, sd)
1236 struct soft_segment_descriptor *ssd;
1237 struct system_segment_descriptor *sd;
1238 {
1239
1240 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1241 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1242 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1243 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1244 sd->sd_type = ssd->ssd_type;
1245 sd->sd_dpl = ssd->ssd_dpl;
1246 sd->sd_p = ssd->ssd_p;
1247 sd->sd_gran = ssd->ssd_gran;
1248 }
1249
1250 #if !defined(DEV_ATPIC) && defined(DEV_ISA)
1251 #include <isa/isavar.h>
1252 #include <isa/isareg.h>
1253 /*
1254 * Return a bitmap of the current interrupt requests. This is 8259-specific
1255 * and is only suitable for use at probe time.
1256 * This is only here to pacify sio. It is NOT FATAL if this doesn't work.
1257 * It shouldn't be here. There should probably be an APIC centric
1258 * implementation in the apic driver code, if at all.
1259 */
1260 intrmask_t
1261 isa_irq_pending(void)
1262 {
1263 u_char irr1;
1264 u_char irr2;
1265
1266 irr1 = inb(IO_ICU1);
1267 irr2 = inb(IO_ICU2);
1268 return ((irr2 << 8) | irr1);
1269 }
1270 #endif
1271
1272 u_int basemem;
1273
1274 static int
1275 add_smap_entry(struct bios_smap *smap, vm_paddr_t *physmap, int *physmap_idxp)
1276 {
1277 int i, insert_idx, physmap_idx;
1278
1279 physmap_idx = *physmap_idxp;
1280
1281 if (boothowto & RB_VERBOSE)
1282 printf("SMAP type=%02x base=%016lx len=%016lx\n",
1283 smap->type, smap->base, smap->length);
1284
1285 if (smap->type != SMAP_TYPE_MEMORY)
1286 return (1);
1287
1288 if (smap->length == 0)
1289 return (0);
1290
1291 /*
1292 * Find insertion point while checking for overlap. Start off by
1293 * assuming the new entry will be added to the end.
1294 */
1295 insert_idx = physmap_idx + 2;
1296 for (i = 0; i <= physmap_idx; i += 2) {
1297 if (smap->base < physmap[i + 1]) {
1298 if (smap->base + smap->length <= physmap[i]) {
1299 insert_idx = i;
1300 break;
1301 }
1302 if (boothowto & RB_VERBOSE)
1303 printf(
1304 "Overlapping memory regions, ignoring second region\n");
1305 return (1);
1306 }
1307 }
1308
1309 /* See if we can prepend to the next entry. */
1310 if (insert_idx <= physmap_idx &&
1311 smap->base + smap->length == physmap[insert_idx]) {
1312 physmap[insert_idx] = smap->base;
1313 return (1);
1314 }
1315
1316 /* See if we can append to the previous entry. */
1317 if (insert_idx > 0 && smap->base == physmap[insert_idx - 1]) {
1318 physmap[insert_idx - 1] += smap->length;
1319 return (1);
1320 }
1321
1322 physmap_idx += 2;
1323 *physmap_idxp = physmap_idx;
1324 if (physmap_idx == PHYSMAP_SIZE) {
1325 printf(
1326 "Too many segments in the physical address map, giving up\n");
1327 return (0);
1328 }
1329
1330 /*
1331 * Move the last 'N' entries down to make room for the new
1332 * entry if needed.
1333 */
1334 for (i = physmap_idx; i > insert_idx; i -= 2) {
1335 physmap[i] = physmap[i - 2];
1336 physmap[i + 1] = physmap[i - 1];
1337 }
1338
1339 /* Insert the new entry. */
1340 physmap[insert_idx] = smap->base;
1341 physmap[insert_idx + 1] = smap->base + smap->length;
1342 return (1);
1343 }
1344
1345 /*
1346 * Populate the (physmap) array with base/bound pairs describing the
1347 * available physical memory in the system, then test this memory and
1348 * build the phys_avail array describing the actually-available memory.
1349 *
1350 * Total memory size may be set by the kernel environment variable
1351 * hw.physmem or the compile-time define MAXMEM.
1352 *
1353 * XXX first should be vm_paddr_t.
1354 */
1355 static void
1356 getmemsize(caddr_t kmdp, u_int64_t first)
1357 {
1358 int i, physmap_idx, pa_indx, da_indx;
1359 vm_paddr_t pa, physmap[PHYSMAP_SIZE];
1360 u_long physmem_start, physmem_tunable, memtest;
1361 pt_entry_t *pte;
1362 struct bios_smap *smapbase, *smap, *smapend;
1363 u_int32_t smapsize;
1364 quad_t dcons_addr, dcons_size;
1365
1366 bzero(physmap, sizeof(physmap));
1367 basemem = 0;
1368 physmap_idx = 0;
1369
1370 /*
1371 * get memory map from INT 15:E820, kindly supplied by the loader.
1372 *
1373 * subr_module.c says:
1374 * "Consumer may safely assume that size value precedes data."
1375 * ie: an int32_t immediately precedes smap.
1376 */
1377 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1378 MODINFO_METADATA | MODINFOMD_SMAP);
1379 if (smapbase == NULL)
1380 panic("No BIOS smap info from loader!");
1381
1382 smapsize = *((u_int32_t *)smapbase - 1);
1383 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1384
1385 for (smap = smapbase; smap < smapend; smap++)
1386 if (!add_smap_entry(smap, physmap, &physmap_idx))
1387 break;
1388
1389 /*
1390 * Find the 'base memory' segment for SMP
1391 */
1392 basemem = 0;
1393 for (i = 0; i <= physmap_idx; i += 2) {
1394 if (physmap[i] == 0x00000000) {
1395 basemem = physmap[i + 1] / 1024;
1396 break;
1397 }
1398 }
1399 if (basemem == 0)
1400 panic("BIOS smap did not include a basemem segment!");
1401
1402 #ifdef SMP
1403 /* make hole for AP bootstrap code */
1404 physmap[1] = mp_bootaddress(physmap[1] / 1024);
1405 #endif
1406
1407 /*
1408 * Maxmem isn't the "maximum memory", it's one larger than the
1409 * highest page of the physical address space. It should be
1410 * called something like "Maxphyspage". We may adjust this
1411 * based on ``hw.physmem'' and the results of the memory test.
1412 */
1413 Maxmem = atop(physmap[physmap_idx + 1]);
1414
1415 #ifdef MAXMEM
1416 Maxmem = MAXMEM / 4;
1417 #endif
1418
1419 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1420 Maxmem = atop(physmem_tunable);
1421
1422 /*
1423 * By default enable the memory test on real hardware, and disable
1424 * it if we appear to be running in a VM. This avoids touching all
1425 * pages unnecessarily, which doesn't matter on real hardware but is
1426 * bad for shared VM hosts. Use a general name so that
1427 * one could eventually do more with the code than just disable it.
1428 */
1429 memtest = (vm_guest > VM_GUEST_NO) ? 0 : 1;
1430 TUNABLE_ULONG_FETCH("hw.memtest.tests", &memtest);
1431
1432 /*
1433 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1434 * in the system.
1435 */
1436 if (Maxmem > atop(physmap[physmap_idx + 1]))
1437 Maxmem = atop(physmap[physmap_idx + 1]);
1438
1439 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1440 (boothowto & RB_VERBOSE))
1441 printf("Physical memory use set to %ldK\n", Maxmem * 4);
1442
1443 /* call pmap initialization to make new kernel address space */
1444 pmap_bootstrap(&first);
1445
1446 /*
1447 * Size up each available chunk of physical memory.
1448 *
1449 * XXX Some BIOSes corrupt low 64KB between suspend and resume.
1450 * By default, mask off the first 16 pages unless we appear to be
1451 * running in a VM.
1452 */
1453 physmem_start = (vm_guest > VM_GUEST_NO ? 1 : 16) << PAGE_SHIFT;
1454 TUNABLE_ULONG_FETCH("hw.physmem.start", &physmem_start);
1455 if (physmem_start < PAGE_SIZE)
1456 physmap[0] = PAGE_SIZE;
1457 else if (physmem_start >= physmap[1])
1458 physmap[0] = round_page(physmap[1] - PAGE_SIZE);
1459 else
1460 physmap[0] = round_page(physmem_start);
1461 pa_indx = 0;
1462 da_indx = 1;
1463 phys_avail[pa_indx++] = physmap[0];
1464 phys_avail[pa_indx] = physmap[0];
1465 dump_avail[da_indx] = physmap[0];
1466 pte = CMAP1;
1467
1468 /*
1469 * Get dcons buffer address
1470 */
1471 if (getenv_quad("dcons.addr", &dcons_addr) == 0 ||
1472 getenv_quad("dcons.size", &dcons_size) == 0)
1473 dcons_addr = 0;
1474
1475 /*
1476 * physmap is in bytes, so when converting to page boundaries,
1477 * round up the start address and round down the end address.
1478 */
1479 for (i = 0; i <= physmap_idx; i += 2) {
1480 vm_paddr_t end;
1481
1482 end = ptoa((vm_paddr_t)Maxmem);
1483 if (physmap[i + 1] < end)
1484 end = trunc_page(physmap[i + 1]);
1485 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) {
1486 int tmp, page_bad, full;
1487 int *ptr = (int *)CADDR1;
1488
1489 full = FALSE;
1490 /*
1491 * block out kernel memory as not available.
1492 */
1493 if (pa >= (vm_paddr_t)kernphys && pa < first)
1494 goto do_dump_avail;
1495
1496 /*
1497 * block out dcons buffer
1498 */
1499 if (dcons_addr > 0
1500 && pa >= trunc_page(dcons_addr)
1501 && pa < dcons_addr + dcons_size)
1502 goto do_dump_avail;
1503
1504 page_bad = FALSE;
1505 if (memtest == 0)
1506 goto skip_memtest;
1507
1508 /*
1509 * map page into kernel: valid, read/write,non-cacheable
1510 */
1511 *pte = pa | PG_V | PG_RW | PG_N;
1512 invltlb();
1513
1514 tmp = *(int *)ptr;
1515 /*
1516 * Test for alternating 1's and 0's
1517 */
1518 *(volatile int *)ptr = 0xaaaaaaaa;
1519 if (*(volatile int *)ptr != 0xaaaaaaaa)
1520 page_bad = TRUE;
1521 /*
1522 * Test for alternating 0's and 1's
1523 */
1524 *(volatile int *)ptr = 0x55555555;
1525 if (*(volatile int *)ptr != 0x55555555)
1526 page_bad = TRUE;
1527 /*
1528 * Test for all 1's
1529 */
1530 *(volatile int *)ptr = 0xffffffff;
1531 if (*(volatile int *)ptr != 0xffffffff)
1532 page_bad = TRUE;
1533 /*
1534 * Test for all 0's
1535 */
1536 *(volatile int *)ptr = 0x0;
1537 if (*(volatile int *)ptr != 0x0)
1538 page_bad = TRUE;
1539 /*
1540 * Restore original value.
1541 */
1542 *(int *)ptr = tmp;
1543
1544 skip_memtest:
1545 /*
1546 * Adjust array of valid/good pages.
1547 */
1548 if (page_bad == TRUE)
1549 continue;
1550 /*
1551 * If this good page is a continuation of the
1552 * previous set of good pages, then just increase
1553 * the end pointer. Otherwise start a new chunk.
1554 * Note that "end" points one higher than end,
1555 * making the range >= start and < end.
1556 * If we're also doing a speculative memory
1557 * test and we at or past the end, bump up Maxmem
1558 * so that we keep going. The first bad page
1559 * will terminate the loop.
1560 */
1561 if (phys_avail[pa_indx] == pa) {
1562 phys_avail[pa_indx] += PAGE_SIZE;
1563 } else {
1564 pa_indx++;
1565 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
1566 printf(
1567 "Too many holes in the physical address space, giving up\n");
1568 pa_indx--;
1569 full = TRUE;
1570 goto do_dump_avail;
1571 }
1572 phys_avail[pa_indx++] = pa; /* start */
1573 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */
1574 }
1575 physmem++;
1576 do_dump_avail:
1577 if (dump_avail[da_indx] == pa) {
1578 dump_avail[da_indx] += PAGE_SIZE;
1579 } else {
1580 da_indx++;
1581 if (da_indx == DUMP_AVAIL_ARRAY_END) {
1582 da_indx--;
1583 goto do_next;
1584 }
1585 dump_avail[da_indx++] = pa; /* start */
1586 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */
1587 }
1588 do_next:
1589 if (full)
1590 break;
1591 }
1592 }
1593 *pte = 0;
1594 invltlb();
1595
1596 /*
1597 * XXX
1598 * The last chunk must contain at least one page plus the message
1599 * buffer to avoid complicating other code (message buffer address
1600 * calculation, etc.).
1601 */
1602 while (phys_avail[pa_indx - 1] + PAGE_SIZE +
1603 round_page(msgbufsize) >= phys_avail[pa_indx]) {
1604 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1605 phys_avail[pa_indx--] = 0;
1606 phys_avail[pa_indx--] = 0;
1607 }
1608
1609 Maxmem = atop(phys_avail[pa_indx]);
1610
1611 /* Trim off space for the message buffer. */
1612 phys_avail[pa_indx] -= round_page(msgbufsize);
1613
1614 /* Map the message buffer. */
1615 msgbufp = (struct msgbuf *)PHYS_TO_DMAP(phys_avail[pa_indx]);
1616 }
1617
1618 u_int64_t
1619 hammer_time(u_int64_t modulep, u_int64_t physfree)
1620 {
1621 caddr_t kmdp;
1622 int gsel_tss, x;
1623 struct pcpu *pc;
1624 struct nmi_pcpu *np;
1625 struct xstate_hdr *xhdr;
1626 u_int64_t msr;
1627 char *env;
1628 size_t kstack0_sz;
1629
1630 thread0.td_kstack = physfree + KERNBASE;
1631 thread0.td_kstack_pages = KSTACK_PAGES;
1632 kstack0_sz = thread0.td_kstack_pages * PAGE_SIZE;
1633 bzero((void *)thread0.td_kstack, kstack0_sz);
1634 physfree += kstack0_sz;
1635
1636 /*
1637 * This may be done better later if it gets more high level
1638 * components in it. If so just link td->td_proc here.
1639 */
1640 proc_linkup0(&proc0, &thread0);
1641
1642 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE);
1643 preload_bootstrap_relocate(KERNBASE);
1644 kmdp = preload_search_by_type("elf kernel");
1645 if (kmdp == NULL)
1646 kmdp = preload_search_by_type("elf64 kernel");
1647 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
1648 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE;
1649 #ifdef DDB
1650 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
1651 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
1652 #endif
1653
1654 /* Init basic tunables, hz etc */
1655 init_param1();
1656
1657 /*
1658 * make gdt memory segments
1659 */
1660 for (x = 0; x < NGDT; x++) {
1661 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) &&
1662 x != GUSERLDT_SEL && x != (GUSERLDT_SEL) + 1)
1663 ssdtosd(&gdt_segs[x], &gdt[x]);
1664 }
1665 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0];
1666 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1667 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
1668
1669 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1670 r_gdt.rd_base = (long) gdt;
1671 lgdt(&r_gdt);
1672 pc = &__pcpu[0];
1673
1674 wrmsr(MSR_FSBASE, 0); /* User value */
1675 wrmsr(MSR_GSBASE, (u_int64_t)pc);
1676 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
1677
1678 pcpu_init(pc, 0, sizeof(struct pcpu));
1679 dpcpu_init((void *)(physfree + KERNBASE), 0);
1680 physfree += DPCPU_SIZE;
1681 PCPU_SET(prvspace, pc);
1682 PCPU_SET(curthread, &thread0);
1683 PCPU_SET(tssp, &common_tss[0]);
1684 PCPU_SET(commontssp, &common_tss[0]);
1685 PCPU_SET(tss, (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
1686 PCPU_SET(ldt, (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL]);
1687 PCPU_SET(fs32p, &gdt[GUFS32_SEL]);
1688 PCPU_SET(gs32p, &gdt[GUGS32_SEL]);
1689
1690 /*
1691 * Initialize mutexes.
1692 *
1693 * icu_lock: in order to allow an interrupt to occur in a critical
1694 * section, to set pcpu->ipending (etc...) properly, we
1695 * must be able to get the icu lock, so it can't be
1696 * under witness.
1697 */
1698 mutex_init();
1699 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS);
1700 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_DEF);
1701
1702 /* exceptions */
1703 for (x = 0; x < NIDT; x++)
1704 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
1705 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
1706 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
1707 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2);
1708 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
1709 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
1710 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
1711 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
1712 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
1713 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
1714 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
1715 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
1716 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
1717 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
1718 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
1719 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
1720 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
1721 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
1722 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
1723 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
1724 #ifdef KDTRACE_HOOKS
1725 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret), SDT_SYSIGT, SEL_UPL, 0);
1726 #endif
1727
1728 r_idt.rd_limit = sizeof(idt0) - 1;
1729 r_idt.rd_base = (long) idt;
1730 lidt(&r_idt);
1731
1732 /*
1733 * Initialize the i8254 before the console so that console
1734 * initialization can use DELAY().
1735 */
1736 i8254_init();
1737
1738 /*
1739 * Initialize the console before we print anything out.
1740 */
1741 cninit();
1742
1743 #ifdef DEV_ISA
1744 #ifdef DEV_ATPIC
1745 elcr_probe();
1746 atpic_startup();
1747 #else
1748 /* Reset and mask the atpics and leave them shut down. */
1749 atpic_reset();
1750
1751 /*
1752 * Point the ICU spurious interrupt vectors at the APIC spurious
1753 * interrupt handler.
1754 */
1755 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0);
1756 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0);
1757 #endif
1758 #else
1759 #error "have you forgotten the isa device?";
1760 #endif
1761
1762 kdb_init();
1763
1764 #ifdef KDB
1765 if (boothowto & RB_KDB)
1766 kdb_enter(KDB_WHY_BOOTFLAGS,
1767 "Boot flags requested debugger");
1768 #endif
1769
1770 identify_cpu(); /* Final stage of CPU initialization */
1771 initializecpu(); /* Initialize CPU registers */
1772 initializecpucache();
1773
1774 /* doublefault stack space, runs on ist1 */
1775 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)];
1776
1777 /*
1778 * NMI stack, runs on ist2. The pcpu pointer is stored just
1779 * above the start of the ist2 stack.
1780 */
1781 np = ((struct nmi_pcpu *) &nmi0_stack[sizeof(nmi0_stack)]) - 1;
1782 np->np_pcpu = (register_t) pc;
1783 common_tss[0].tss_ist2 = (long) np;
1784
1785 /* Set the IO permission bitmap (empty due to tss seg limit) */
1786 common_tss[0].tss_iobase = sizeof(struct amd64tss) +
1787 IOPAGES * PAGE_SIZE;
1788
1789 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
1790 ltr(gsel_tss);
1791
1792 /* Set up the fast syscall stuff */
1793 msr = rdmsr(MSR_EFER) | EFER_SCE;
1794 wrmsr(MSR_EFER, msr);
1795 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
1796 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
1797 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
1798 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
1799 wrmsr(MSR_STAR, msr);
1800 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
1801
1802 getmemsize(kmdp, physfree);
1803 init_param2(physmem);
1804
1805 /* now running on new page tables, configured,and u/iom is accessible */
1806
1807 msgbufinit(msgbufp, msgbufsize);
1808 fpuinit();
1809
1810 /*
1811 * Set up thread0 pcb after fpuinit calculated pcb + fpu save
1812 * area size. Zero out the extended state header in fpu save
1813 * area.
1814 */
1815 thread0.td_pcb = get_pcb_td(&thread0);
1816 bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size);
1817 if (use_xsave) {
1818 xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) +
1819 1);
1820 xhdr->xstate_bv = xsave_mask;
1821 }
1822 /* make an initial tss so cpu can get interrupt stack on syscall! */
1823 common_tss[0].tss_rsp0 = (vm_offset_t)thread0.td_pcb;
1824 /* Ensure the stack is aligned to 16 bytes */
1825 common_tss[0].tss_rsp0 &= ~0xFul;
1826 PCPU_SET(rsp0, common_tss[0].tss_rsp0);
1827 PCPU_SET(curpcb, thread0.td_pcb);
1828
1829 /* transfer to user mode */
1830
1831 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
1832 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
1833 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
1834 _ufssel = GSEL(GUFS32_SEL, SEL_UPL);
1835 _ugssel = GSEL(GUGS32_SEL, SEL_UPL);
1836
1837 load_ds(_udatasel);
1838 load_es(_udatasel);
1839 load_fs(_ufssel);
1840
1841 /* setup proc 0's pcb */
1842 thread0.td_pcb->pcb_flags = 0;
1843 thread0.td_pcb->pcb_cr3 = KPML4phys;
1844 thread0.td_frame = &proc0_tf;
1845
1846 env = getenv("kernelname");
1847 if (env != NULL)
1848 strlcpy(kernelname, env, sizeof(kernelname));
1849
1850 #ifdef XENHVM
1851 if (inw(0x10) == 0x49d2) {
1852 if (bootverbose)
1853 printf("Xen detected: disabling emulated block and network devices\n");
1854 outw(0x10, 3);
1855 }
1856 #endif
1857
1858 cpu_probe_amdc1e();
1859
1860 /* Location of kernel stack for locore */
1861 return ((u_int64_t)thread0.td_pcb);
1862 }
1863
1864 void
1865 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size)
1866 {
1867
1868 pcpu->pc_acpi_id = 0xffffffff;
1869 }
1870
1871 void
1872 spinlock_enter(void)
1873 {
1874 struct thread *td;
1875 register_t flags;
1876
1877 td = curthread;
1878 if (td->td_md.md_spinlock_count == 0) {
1879 flags = intr_disable();
1880 td->td_md.md_spinlock_count = 1;
1881 td->td_md.md_saved_flags = flags;
1882 } else
1883 td->td_md.md_spinlock_count++;
1884 critical_enter();
1885 }
1886
1887 void
1888 spinlock_exit(void)
1889 {
1890 struct thread *td;
1891 register_t flags;
1892
1893 td = curthread;
1894 critical_exit();
1895 flags = td->td_md.md_saved_flags;
1896 td->td_md.md_spinlock_count--;
1897 if (td->td_md.md_spinlock_count == 0)
1898 intr_restore(flags);
1899 }
1900
1901 /*
1902 * Construct a PCB from a trapframe. This is called from kdb_trap() where
1903 * we want to start a backtrace from the function that caused us to enter
1904 * the debugger. We have the context in the trapframe, but base the trace
1905 * on the PCB. The PCB doesn't have to be perfect, as long as it contains
1906 * enough for a backtrace.
1907 */
1908 void
1909 makectx(struct trapframe *tf, struct pcb *pcb)
1910 {
1911
1912 pcb->pcb_r12 = tf->tf_r12;
1913 pcb->pcb_r13 = tf->tf_r13;
1914 pcb->pcb_r14 = tf->tf_r14;
1915 pcb->pcb_r15 = tf->tf_r15;
1916 pcb->pcb_rbp = tf->tf_rbp;
1917 pcb->pcb_rbx = tf->tf_rbx;
1918 pcb->pcb_rip = tf->tf_rip;
1919 pcb->pcb_rsp = tf->tf_rsp;
1920 }
1921
1922 int
1923 ptrace_set_pc(struct thread *td, unsigned long addr)
1924 {
1925 td->td_frame->tf_rip = addr;
1926 return (0);
1927 }
1928
1929 int
1930 ptrace_single_step(struct thread *td)
1931 {
1932 td->td_frame->tf_rflags |= PSL_T;
1933 return (0);
1934 }
1935
1936 int
1937 ptrace_clear_single_step(struct thread *td)
1938 {
1939 td->td_frame->tf_rflags &= ~PSL_T;
1940 return (0);
1941 }
1942
1943 int
1944 fill_regs(struct thread *td, struct reg *regs)
1945 {
1946 struct trapframe *tp;
1947
1948 tp = td->td_frame;
1949 return (fill_frame_regs(tp, regs));
1950 }
1951
1952 int
1953 fill_frame_regs(struct trapframe *tp, struct reg *regs)
1954 {
1955 regs->r_r15 = tp->tf_r15;
1956 regs->r_r14 = tp->tf_r14;
1957 regs->r_r13 = tp->tf_r13;
1958 regs->r_r12 = tp->tf_r12;
1959 regs->r_r11 = tp->tf_r11;
1960 regs->r_r10 = tp->tf_r10;
1961 regs->r_r9 = tp->tf_r9;
1962 regs->r_r8 = tp->tf_r8;
1963 regs->r_rdi = tp->tf_rdi;
1964 regs->r_rsi = tp->tf_rsi;
1965 regs->r_rbp = tp->tf_rbp;
1966 regs->r_rbx = tp->tf_rbx;
1967 regs->r_rdx = tp->tf_rdx;
1968 regs->r_rcx = tp->tf_rcx;
1969 regs->r_rax = tp->tf_rax;
1970 regs->r_rip = tp->tf_rip;
1971 regs->r_cs = tp->tf_cs;
1972 regs->r_rflags = tp->tf_rflags;
1973 regs->r_rsp = tp->tf_rsp;
1974 regs->r_ss = tp->tf_ss;
1975 if (tp->tf_flags & TF_HASSEGS) {
1976 regs->r_ds = tp->tf_ds;
1977 regs->r_es = tp->tf_es;
1978 regs->r_fs = tp->tf_fs;
1979 regs->r_gs = tp->tf_gs;
1980 } else {
1981 regs->r_ds = 0;
1982 regs->r_es = 0;
1983 regs->r_fs = 0;
1984 regs->r_gs = 0;
1985 }
1986 return (0);
1987 }
1988
1989 int
1990 set_regs(struct thread *td, struct reg *regs)
1991 {
1992 struct trapframe *tp;
1993 register_t rflags;
1994
1995 tp = td->td_frame;
1996 rflags = regs->r_rflags & 0xffffffff;
1997 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs))
1998 return (EINVAL);
1999 tp->tf_r15 = regs->r_r15;
2000 tp->tf_r14 = regs->r_r14;
2001 tp->tf_r13 = regs->r_r13;
2002 tp->tf_r12 = regs->r_r12;
2003 tp->tf_r11 = regs->r_r11;
2004 tp->tf_r10 = regs->r_r10;
2005 tp->tf_r9 = regs->r_r9;
2006 tp->tf_r8 = regs->r_r8;
2007 tp->tf_rdi = regs->r_rdi;
2008 tp->tf_rsi = regs->r_rsi;
2009 tp->tf_rbp = regs->r_rbp;
2010 tp->tf_rbx = regs->r_rbx;
2011 tp->tf_rdx = regs->r_rdx;
2012 tp->tf_rcx = regs->r_rcx;
2013 tp->tf_rax = regs->r_rax;
2014 tp->tf_rip = regs->r_rip;
2015 tp->tf_cs = regs->r_cs;
2016 tp->tf_rflags = rflags;
2017 tp->tf_rsp = regs->r_rsp;
2018 tp->tf_ss = regs->r_ss;
2019 if (0) { /* XXXKIB */
2020 tp->tf_ds = regs->r_ds;
2021 tp->tf_es = regs->r_es;
2022 tp->tf_fs = regs->r_fs;
2023 tp->tf_gs = regs->r_gs;
2024 tp->tf_flags = TF_HASSEGS;
2025 set_pcb_flags(td->td_pcb, PCB_FULL_IRET);
2026 }
2027 return (0);
2028 }
2029
2030 /* XXX check all this stuff! */
2031 /* externalize from sv_xmm */
2032 static void
2033 fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs)
2034 {
2035 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env;
2036 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2037 int i;
2038
2039 /* pcb -> fpregs */
2040 bzero(fpregs, sizeof(*fpregs));
2041
2042 /* FPU control/status */
2043 penv_fpreg->en_cw = penv_xmm->en_cw;
2044 penv_fpreg->en_sw = penv_xmm->en_sw;
2045 penv_fpreg->en_tw = penv_xmm->en_tw;
2046 penv_fpreg->en_opcode = penv_xmm->en_opcode;
2047 penv_fpreg->en_rip = penv_xmm->en_rip;
2048 penv_fpreg->en_rdp = penv_xmm->en_rdp;
2049 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr;
2050 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask;
2051
2052 /* FPU registers */
2053 for (i = 0; i < 8; ++i)
2054 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10);
2055
2056 /* SSE registers */
2057 for (i = 0; i < 16; ++i)
2058 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16);
2059 }
2060
2061 /* internalize from fpregs into sv_xmm */
2062 static void
2063 set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm)
2064 {
2065 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2066 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env;
2067 int i;
2068
2069 /* fpregs -> pcb */
2070 /* FPU control/status */
2071 penv_xmm->en_cw = penv_fpreg->en_cw;
2072 penv_xmm->en_sw = penv_fpreg->en_sw;
2073 penv_xmm->en_tw = penv_fpreg->en_tw;
2074 penv_xmm->en_opcode = penv_fpreg->en_opcode;
2075 penv_xmm->en_rip = penv_fpreg->en_rip;
2076 penv_xmm->en_rdp = penv_fpreg->en_rdp;
2077 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr;
2078 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask;
2079
2080 /* FPU registers */
2081 for (i = 0; i < 8; ++i)
2082 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10);
2083
2084 /* SSE registers */
2085 for (i = 0; i < 16; ++i)
2086 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16);
2087 }
2088
2089 /* externalize from td->pcb */
2090 int
2091 fill_fpregs(struct thread *td, struct fpreg *fpregs)
2092 {
2093
2094 KASSERT(td == curthread || TD_IS_SUSPENDED(td) ||
2095 P_SHOULDSTOP(td->td_proc),
2096 ("not suspended thread %p", td));
2097 fpugetregs(td);
2098 fill_fpregs_xmm(get_pcb_user_save_td(td), fpregs);
2099 return (0);
2100 }
2101
2102 /* internalize to td->pcb */
2103 int
2104 set_fpregs(struct thread *td, struct fpreg *fpregs)
2105 {
2106
2107 set_fpregs_xmm(fpregs, get_pcb_user_save_td(td));
2108 fpuuserinited(td);
2109 return (0);
2110 }
2111
2112 /*
2113 * Get machine context.
2114 */
2115 int
2116 get_mcontext(struct thread *td, mcontext_t *mcp, int flags)
2117 {
2118 struct pcb *pcb;
2119 struct trapframe *tp;
2120
2121 pcb = td->td_pcb;
2122 tp = td->td_frame;
2123 PROC_LOCK(curthread->td_proc);
2124 mcp->mc_onstack = sigonstack(tp->tf_rsp);
2125 PROC_UNLOCK(curthread->td_proc);
2126 mcp->mc_r15 = tp->tf_r15;
2127 mcp->mc_r14 = tp->tf_r14;
2128 mcp->mc_r13 = tp->tf_r13;
2129 mcp->mc_r12 = tp->tf_r12;
2130 mcp->mc_r11 = tp->tf_r11;
2131 mcp->mc_r10 = tp->tf_r10;
2132 mcp->mc_r9 = tp->tf_r9;
2133 mcp->mc_r8 = tp->tf_r8;
2134 mcp->mc_rdi = tp->tf_rdi;
2135 mcp->mc_rsi = tp->tf_rsi;
2136 mcp->mc_rbp = tp->tf_rbp;
2137 mcp->mc_rbx = tp->tf_rbx;
2138 mcp->mc_rcx = tp->tf_rcx;
2139 mcp->mc_rflags = tp->tf_rflags;
2140 if (flags & GET_MC_CLEAR_RET) {
2141 mcp->mc_rax = 0;
2142 mcp->mc_rdx = 0;
2143 mcp->mc_rflags &= ~PSL_C;
2144 } else {
2145 mcp->mc_rax = tp->tf_rax;
2146 mcp->mc_rdx = tp->tf_rdx;
2147 }
2148 mcp->mc_rip = tp->tf_rip;
2149 mcp->mc_cs = tp->tf_cs;
2150 mcp->mc_rsp = tp->tf_rsp;
2151 mcp->mc_ss = tp->tf_ss;
2152 mcp->mc_ds = tp->tf_ds;
2153 mcp->mc_es = tp->tf_es;
2154 mcp->mc_fs = tp->tf_fs;
2155 mcp->mc_gs = tp->tf_gs;
2156 mcp->mc_flags = tp->tf_flags;
2157 mcp->mc_len = sizeof(*mcp);
2158 get_fpcontext(td, mcp, NULL, 0);
2159 mcp->mc_fsbase = pcb->pcb_fsbase;
2160 mcp->mc_gsbase = pcb->pcb_gsbase;
2161 mcp->mc_xfpustate = 0;
2162 mcp->mc_xfpustate_len = 0;
2163 bzero(mcp->mc_spare, sizeof(mcp->mc_spare));
2164 return (0);
2165 }
2166
2167 /*
2168 * Set machine context.
2169 *
2170 * However, we don't set any but the user modifiable flags, and we won't
2171 * touch the cs selector.
2172 */
2173 int
2174 set_mcontext(struct thread *td, const mcontext_t *mcp)
2175 {
2176 struct pcb *pcb;
2177 struct trapframe *tp;
2178 char *xfpustate;
2179 long rflags;
2180 int ret;
2181
2182 pcb = td->td_pcb;
2183 tp = td->td_frame;
2184 if (mcp->mc_len != sizeof(*mcp) ||
2185 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0)
2186 return (EINVAL);
2187 rflags = (mcp->mc_rflags & PSL_USERCHANGE) |
2188 (tp->tf_rflags & ~PSL_USERCHANGE);
2189 if (mcp->mc_flags & _MC_HASFPXSTATE) {
2190 if (mcp->mc_xfpustate_len > cpu_max_ext_state_size -
2191 sizeof(struct savefpu))
2192 return (EINVAL);
2193 xfpustate = __builtin_alloca(mcp->mc_xfpustate_len);
2194 ret = copyin((void *)mcp->mc_xfpustate, xfpustate,
2195 mcp->mc_xfpustate_len);
2196 if (ret != 0)
2197 return (ret);
2198 } else
2199 xfpustate = NULL;
2200 ret = set_fpcontext(td, mcp, xfpustate, mcp->mc_xfpustate_len);
2201 if (ret != 0)
2202 return (ret);
2203 tp->tf_r15 = mcp->mc_r15;
2204 tp->tf_r14 = mcp->mc_r14;
2205 tp->tf_r13 = mcp->mc_r13;
2206 tp->tf_r12 = mcp->mc_r12;
2207 tp->tf_r11 = mcp->mc_r11;
2208 tp->tf_r10 = mcp->mc_r10;
2209 tp->tf_r9 = mcp->mc_r9;
2210 tp->tf_r8 = mcp->mc_r8;
2211 tp->tf_rdi = mcp->mc_rdi;
2212 tp->tf_rsi = mcp->mc_rsi;
2213 tp->tf_rbp = mcp->mc_rbp;
2214 tp->tf_rbx = mcp->mc_rbx;
2215 tp->tf_rdx = mcp->mc_rdx;
2216 tp->tf_rcx = mcp->mc_rcx;
2217 tp->tf_rax = mcp->mc_rax;
2218 tp->tf_rip = mcp->mc_rip;
2219 tp->tf_rflags = rflags;
2220 tp->tf_rsp = mcp->mc_rsp;
2221 tp->tf_ss = mcp->mc_ss;
2222 tp->tf_flags = mcp->mc_flags;
2223 if (tp->tf_flags & TF_HASSEGS) {
2224 tp->tf_ds = mcp->mc_ds;
2225 tp->tf_es = mcp->mc_es;
2226 tp->tf_fs = mcp->mc_fs;
2227 tp->tf_gs = mcp->mc_gs;
2228 }
2229 if (mcp->mc_flags & _MC_HASBASES) {
2230 pcb->pcb_fsbase = mcp->mc_fsbase;
2231 pcb->pcb_gsbase = mcp->mc_gsbase;
2232 }
2233 set_pcb_flags(pcb, PCB_FULL_IRET);
2234 return (0);
2235 }
2236
2237 static void
2238 get_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpusave,
2239 size_t xfpusave_len)
2240 {
2241 size_t max_len, len;
2242
2243 mcp->mc_ownedfp = fpugetregs(td);
2244 bcopy(get_pcb_user_save_td(td), &mcp->mc_fpstate,
2245 sizeof(mcp->mc_fpstate));
2246 mcp->mc_fpformat = fpuformat();
2247 if (!use_xsave || xfpusave_len == 0)
2248 return;
2249 max_len = cpu_max_ext_state_size - sizeof(struct savefpu);
2250 len = xfpusave_len;
2251 if (len > max_len) {
2252 len = max_len;
2253 bzero(xfpusave + max_len, len - max_len);
2254 }
2255 mcp->mc_flags |= _MC_HASFPXSTATE;
2256 mcp->mc_xfpustate_len = len;
2257 bcopy(get_pcb_user_save_td(td) + 1, xfpusave, len);
2258 }
2259
2260 static int
2261 set_fpcontext(struct thread *td, const mcontext_t *mcp, char *xfpustate,
2262 size_t xfpustate_len)
2263 {
2264 struct savefpu *fpstate;
2265 int error;
2266
2267 if (mcp->mc_fpformat == _MC_FPFMT_NODEV)
2268 return (0);
2269 else if (mcp->mc_fpformat != _MC_FPFMT_XMM)
2270 return (EINVAL);
2271 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) {
2272 /* We don't care what state is left in the FPU or PCB. */
2273 fpstate_drop(td);
2274 error = 0;
2275 } else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU ||
2276 mcp->mc_ownedfp == _MC_FPOWNED_PCB) {
2277 fpstate = (struct savefpu *)&mcp->mc_fpstate;
2278 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask;
2279 error = fpusetregs(td, fpstate, xfpustate, xfpustate_len);
2280 } else
2281 return (EINVAL);
2282 return (error);
2283 }
2284
2285 void
2286 fpstate_drop(struct thread *td)
2287 {
2288
2289 KASSERT(PCB_USER_FPU(td->td_pcb), ("fpstate_drop: kernel-owned fpu"));
2290 critical_enter();
2291 if (PCPU_GET(fpcurthread) == td)
2292 fpudrop();
2293 /*
2294 * XXX force a full drop of the fpu. The above only drops it if we
2295 * owned it.
2296 *
2297 * XXX I don't much like fpugetuserregs()'s semantics of doing a full
2298 * drop. Dropping only to the pcb matches fnsave's behaviour.
2299 * We only need to drop to !PCB_INITDONE in sendsig(). But
2300 * sendsig() is the only caller of fpugetuserregs()... perhaps we just
2301 * have too many layers.
2302 */
2303 clear_pcb_flags(curthread->td_pcb,
2304 PCB_FPUINITDONE | PCB_USERFPUINITDONE);
2305 critical_exit();
2306 }
2307
2308 int
2309 fill_dbregs(struct thread *td, struct dbreg *dbregs)
2310 {
2311 struct pcb *pcb;
2312
2313 if (td == NULL) {
2314 dbregs->dr[0] = rdr0();
2315 dbregs->dr[1] = rdr1();
2316 dbregs->dr[2] = rdr2();
2317 dbregs->dr[3] = rdr3();
2318 dbregs->dr[6] = rdr6();
2319 dbregs->dr[7] = rdr7();
2320 } else {
2321 pcb = td->td_pcb;
2322 dbregs->dr[0] = pcb->pcb_dr0;
2323 dbregs->dr[1] = pcb->pcb_dr1;
2324 dbregs->dr[2] = pcb->pcb_dr2;
2325 dbregs->dr[3] = pcb->pcb_dr3;
2326 dbregs->dr[6] = pcb->pcb_dr6;
2327 dbregs->dr[7] = pcb->pcb_dr7;
2328 }
2329 dbregs->dr[4] = 0;
2330 dbregs->dr[5] = 0;
2331 dbregs->dr[8] = 0;
2332 dbregs->dr[9] = 0;
2333 dbregs->dr[10] = 0;
2334 dbregs->dr[11] = 0;
2335 dbregs->dr[12] = 0;
2336 dbregs->dr[13] = 0;
2337 dbregs->dr[14] = 0;
2338 dbregs->dr[15] = 0;
2339 return (0);
2340 }
2341
2342 int
2343 set_dbregs(struct thread *td, struct dbreg *dbregs)
2344 {
2345 struct pcb *pcb;
2346 int i;
2347
2348 if (td == NULL) {
2349 load_dr0(dbregs->dr[0]);
2350 load_dr1(dbregs->dr[1]);
2351 load_dr2(dbregs->dr[2]);
2352 load_dr3(dbregs->dr[3]);
2353 load_dr6(dbregs->dr[6]);
2354 load_dr7(dbregs->dr[7]);
2355 } else {
2356 /*
2357 * Don't let an illegal value for dr7 get set. Specifically,
2358 * check for undefined settings. Setting these bit patterns
2359 * result in undefined behaviour and can lead to an unexpected
2360 * TRCTRAP or a general protection fault right here.
2361 * Upper bits of dr6 and dr7 must not be set
2362 */
2363 for (i = 0; i < 4; i++) {
2364 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02)
2365 return (EINVAL);
2366 if (td->td_frame->tf_cs == _ucode32sel &&
2367 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8)
2368 return (EINVAL);
2369 }
2370 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 ||
2371 (dbregs->dr[7] & 0xffffffff00000000ul) != 0)
2372 return (EINVAL);
2373
2374 pcb = td->td_pcb;
2375
2376 /*
2377 * Don't let a process set a breakpoint that is not within the
2378 * process's address space. If a process could do this, it
2379 * could halt the system by setting a breakpoint in the kernel
2380 * (if ddb was enabled). Thus, we need to check to make sure
2381 * that no breakpoints are being enabled for addresses outside
2382 * process's address space.
2383 *
2384 * XXX - what about when the watched area of the user's
2385 * address space is written into from within the kernel
2386 * ... wouldn't that still cause a breakpoint to be generated
2387 * from within kernel mode?
2388 */
2389
2390 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) {
2391 /* dr0 is enabled */
2392 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS)
2393 return (EINVAL);
2394 }
2395 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) {
2396 /* dr1 is enabled */
2397 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS)
2398 return (EINVAL);
2399 }
2400 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) {
2401 /* dr2 is enabled */
2402 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS)
2403 return (EINVAL);
2404 }
2405 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) {
2406 /* dr3 is enabled */
2407 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS)
2408 return (EINVAL);
2409 }
2410
2411 pcb->pcb_dr0 = dbregs->dr[0];
2412 pcb->pcb_dr1 = dbregs->dr[1];
2413 pcb->pcb_dr2 = dbregs->dr[2];
2414 pcb->pcb_dr3 = dbregs->dr[3];
2415 pcb->pcb_dr6 = dbregs->dr[6];
2416 pcb->pcb_dr7 = dbregs->dr[7];
2417
2418 set_pcb_flags(pcb, PCB_DBREGS);
2419 }
2420
2421 return (0);
2422 }
2423
2424 void
2425 reset_dbregs(void)
2426 {
2427
2428 load_dr7(0); /* Turn off the control bits first */
2429 load_dr0(0);
2430 load_dr1(0);
2431 load_dr2(0);
2432 load_dr3(0);
2433 load_dr6(0);
2434 }
2435
2436 /*
2437 * Return > 0 if a hardware breakpoint has been hit, and the
2438 * breakpoint was in user space. Return 0, otherwise.
2439 */
2440 int
2441 user_dbreg_trap(void)
2442 {
2443 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2444 u_int64_t bp; /* breakpoint bits extracted from dr6 */
2445 int nbp; /* number of breakpoints that triggered */
2446 caddr_t addr[4]; /* breakpoint addresses */
2447 int i;
2448
2449 dr7 = rdr7();
2450 if ((dr7 & 0x000000ff) == 0) {
2451 /*
2452 * all GE and LE bits in the dr7 register are zero,
2453 * thus the trap couldn't have been caused by the
2454 * hardware debug registers
2455 */
2456 return 0;
2457 }
2458
2459 nbp = 0;
2460 dr6 = rdr6();
2461 bp = dr6 & 0x0000000f;
2462
2463 if (!bp) {
2464 /*
2465 * None of the breakpoint bits are set meaning this
2466 * trap was not caused by any of the debug registers
2467 */
2468 return 0;
2469 }
2470
2471 /*
2472 * at least one of the breakpoints were hit, check to see
2473 * which ones and if any of them are user space addresses
2474 */
2475
2476 if (bp & 0x01) {
2477 addr[nbp++] = (caddr_t)rdr0();
2478 }
2479 if (bp & 0x02) {
2480 addr[nbp++] = (caddr_t)rdr1();
2481 }
2482 if (bp & 0x04) {
2483 addr[nbp++] = (caddr_t)rdr2();
2484 }
2485 if (bp & 0x08) {
2486 addr[nbp++] = (caddr_t)rdr3();
2487 }
2488
2489 for (i = 0; i < nbp; i++) {
2490 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) {
2491 /*
2492 * addr[i] is in user space
2493 */
2494 return nbp;
2495 }
2496 }
2497
2498 /*
2499 * None of the breakpoints are in user space.
2500 */
2501 return 0;
2502 }
2503
2504 #ifdef KDB
2505
2506 /*
2507 * Provide inb() and outb() as functions. They are normally only available as
2508 * inline functions, thus cannot be called from the debugger.
2509 */
2510
2511 /* silence compiler warnings */
2512 u_char inb_(u_short);
2513 void outb_(u_short, u_char);
2514
2515 u_char
2516 inb_(u_short port)
2517 {
2518 return inb(port);
2519 }
2520
2521 void
2522 outb_(u_short port, u_char data)
2523 {
2524 outb(port, data);
2525 }
2526
2527 #endif /* KDB */
Cache object: 79540e19070507597a8f3062cb0128d8
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