1 /*-
2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * William Jolitz.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the University of
21 * California, Berkeley and its contributors.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
39 */
40
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD: releng/9.2/sys/amd64/amd64/machdep.c 251290 2013-06-03 04:57:15Z kib $");
43
44 #include "opt_atalk.h"
45 #include "opt_atpic.h"
46 #include "opt_compat.h"
47 #include "opt_cpu.h"
48 #include "opt_ddb.h"
49 #include "opt_inet.h"
50 #include "opt_ipx.h"
51 #include "opt_isa.h"
52 #include "opt_kstack_pages.h"
53 #include "opt_maxmem.h"
54 #include "opt_mp_watchdog.h"
55 #include "opt_perfmon.h"
56 #include "opt_sched.h"
57 #include "opt_kdtrace.h"
58
59 #include <sys/param.h>
60 #include <sys/proc.h>
61 #include <sys/systm.h>
62 #include <sys/bio.h>
63 #include <sys/buf.h>
64 #include <sys/bus.h>
65 #include <sys/callout.h>
66 #include <sys/cons.h>
67 #include <sys/cpu.h>
68 #include <sys/eventhandler.h>
69 #include <sys/exec.h>
70 #include <sys/imgact.h>
71 #include <sys/kdb.h>
72 #include <sys/kernel.h>
73 #include <sys/ktr.h>
74 #include <sys/linker.h>
75 #include <sys/lock.h>
76 #include <sys/malloc.h>
77 #include <sys/memrange.h>
78 #include <sys/msgbuf.h>
79 #include <sys/mutex.h>
80 #include <sys/pcpu.h>
81 #include <sys/ptrace.h>
82 #include <sys/reboot.h>
83 #include <sys/sched.h>
84 #include <sys/signalvar.h>
85 #ifdef SMP
86 #include <sys/smp.h>
87 #endif
88 #include <sys/syscallsubr.h>
89 #include <sys/sysctl.h>
90 #include <sys/sysent.h>
91 #include <sys/sysproto.h>
92 #include <sys/ucontext.h>
93 #include <sys/vmmeter.h>
94
95 #include <vm/vm.h>
96 #include <vm/vm_extern.h>
97 #include <vm/vm_kern.h>
98 #include <vm/vm_page.h>
99 #include <vm/vm_map.h>
100 #include <vm/vm_object.h>
101 #include <vm/vm_pager.h>
102 #include <vm/vm_param.h>
103
104 #ifdef DDB
105 #ifndef KDB
106 #error KDB must be enabled in order for DDB to work!
107 #endif
108 #include <ddb/ddb.h>
109 #include <ddb/db_sym.h>
110 #endif
111
112 #include <net/netisr.h>
113
114 #include <machine/clock.h>
115 #include <machine/cpu.h>
116 #include <machine/cputypes.h>
117 #include <machine/intr_machdep.h>
118 #include <x86/mca.h>
119 #include <machine/md_var.h>
120 #include <machine/metadata.h>
121 #include <machine/mp_watchdog.h>
122 #include <machine/pc/bios.h>
123 #include <machine/pcb.h>
124 #include <machine/proc.h>
125 #include <machine/reg.h>
126 #include <machine/sigframe.h>
127 #include <machine/specialreg.h>
128 #ifdef PERFMON
129 #include <machine/perfmon.h>
130 #endif
131 #include <machine/tss.h>
132 #ifdef SMP
133 #include <machine/smp.h>
134 #endif
135
136 #ifdef DEV_ATPIC
137 #include <x86/isa/icu.h>
138 #else
139 #include <machine/apicvar.h>
140 #endif
141
142 #include <isa/isareg.h>
143 #include <isa/rtc.h>
144
145 /* Sanity check for __curthread() */
146 CTASSERT(offsetof(struct pcpu, pc_curthread) == 0);
147
148 extern u_int64_t hammer_time(u_int64_t, u_int64_t);
149
150 extern void printcpuinfo(void); /* XXX header file */
151 extern void identify_cpu(void);
152 extern void panicifcpuunsupported(void);
153
154 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
155 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
156
157 static void cpu_startup(void *);
158 static void get_fpcontext(struct thread *td, mcontext_t *mcp,
159 char *xfpusave, size_t xfpusave_len);
160 static int set_fpcontext(struct thread *td, const mcontext_t *mcp,
161 char *xfpustate, size_t xfpustate_len);
162 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
163
164 /*
165 * The file "conf/ldscript.amd64" defines the symbol "kernphys". Its value is
166 * the physical address at which the kernel is loaded.
167 */
168 extern char kernphys[];
169 #ifdef DDB
170 extern vm_offset_t ksym_start, ksym_end;
171 #endif
172
173 struct msgbuf *msgbufp;
174
175 /* Intel ICH registers */
176 #define ICH_PMBASE 0x400
177 #define ICH_SMI_EN ICH_PMBASE + 0x30
178
179 int _udatasel, _ucodesel, _ucode32sel, _ufssel, _ugssel;
180
181 int cold = 1;
182
183 long Maxmem = 0;
184 long realmem = 0;
185
186 /*
187 * The number of PHYSMAP entries must be one less than the number of
188 * PHYSSEG entries because the PHYSMAP entry that spans the largest
189 * physical address that is accessible by ISA DMA is split into two
190 * PHYSSEG entries.
191 */
192 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
193
194 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
195 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
196
197 /* must be 2 less so 0 0 can signal end of chunks */
198 #define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2)
199 #define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2)
200
201 struct kva_md_info kmi;
202
203 static struct trapframe proc0_tf;
204 struct region_descriptor r_gdt, r_idt;
205
206 struct pcpu __pcpu[MAXCPU];
207
208 struct mtx icu_lock;
209
210 struct mem_range_softc mem_range_softc;
211
212 struct mtx dt_lock; /* lock for GDT and LDT */
213
214 static void
215 cpu_startup(dummy)
216 void *dummy;
217 {
218 uintmax_t memsize;
219 char *sysenv;
220
221 /*
222 * On MacBooks, we need to disallow the legacy USB circuit to
223 * generate an SMI# because this can cause several problems,
224 * namely: incorrect CPU frequency detection and failure to
225 * start the APs.
226 * We do this by disabling a bit in the SMI_EN (SMI Control and
227 * Enable register) of the Intel ICH LPC Interface Bridge.
228 */
229 sysenv = getenv("smbios.system.product");
230 if (sysenv != NULL) {
231 if (strncmp(sysenv, "MacBook1,1", 10) == 0 ||
232 strncmp(sysenv, "MacBook3,1", 10) == 0 ||
233 strncmp(sysenv, "MacBookPro1,1", 13) == 0 ||
234 strncmp(sysenv, "MacBookPro1,2", 13) == 0 ||
235 strncmp(sysenv, "MacBookPro3,1", 13) == 0 ||
236 strncmp(sysenv, "Macmini1,1", 10) == 0) {
237 if (bootverbose)
238 printf("Disabling LEGACY_USB_EN bit on "
239 "Intel ICH.\n");
240 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8);
241 }
242 freeenv(sysenv);
243 }
244
245 /*
246 * Good {morning,afternoon,evening,night}.
247 */
248 startrtclock();
249 printcpuinfo();
250 panicifcpuunsupported();
251 #ifdef PERFMON
252 perfmon_init();
253 #endif
254 realmem = Maxmem;
255
256 /*
257 * Display physical memory if SMBIOS reports reasonable amount.
258 */
259 memsize = 0;
260 sysenv = getenv("smbios.memory.enabled");
261 if (sysenv != NULL) {
262 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10;
263 freeenv(sysenv);
264 }
265 if (memsize < ptoa((uintmax_t)cnt.v_free_count))
266 memsize = ptoa((uintmax_t)Maxmem);
267 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20);
268
269 /*
270 * Display any holes after the first chunk of extended memory.
271 */
272 if (bootverbose) {
273 int indx;
274
275 printf("Physical memory chunk(s):\n");
276 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
277 vm_paddr_t size;
278
279 size = phys_avail[indx + 1] - phys_avail[indx];
280 printf(
281 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n",
282 (uintmax_t)phys_avail[indx],
283 (uintmax_t)phys_avail[indx + 1] - 1,
284 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE);
285 }
286 }
287
288 vm_ksubmap_init(&kmi);
289
290 printf("avail memory = %ju (%ju MB)\n",
291 ptoa((uintmax_t)cnt.v_free_count),
292 ptoa((uintmax_t)cnt.v_free_count) / 1048576);
293
294 /*
295 * Set up buffers, so they can be used to read disk labels.
296 */
297 bufinit();
298 vm_pager_bufferinit();
299
300 cpu_setregs();
301
302 /*
303 * Add BSP as an interrupt target.
304 */
305 intr_add_cpu(0);
306 }
307
308 /*
309 * Send an interrupt to process.
310 *
311 * Stack is set up to allow sigcode stored
312 * at top to call routine, followed by call
313 * to sigreturn routine below. After sigreturn
314 * resets the signal mask, the stack, and the
315 * frame pointer, it returns to the user
316 * specified pc, psl.
317 */
318 void
319 sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
320 {
321 struct sigframe sf, *sfp;
322 struct pcb *pcb;
323 struct proc *p;
324 struct thread *td;
325 struct sigacts *psp;
326 char *sp;
327 struct trapframe *regs;
328 char *xfpusave;
329 size_t xfpusave_len;
330 int sig;
331 int oonstack;
332
333 td = curthread;
334 pcb = td->td_pcb;
335 p = td->td_proc;
336 PROC_LOCK_ASSERT(p, MA_OWNED);
337 sig = ksi->ksi_signo;
338 psp = p->p_sigacts;
339 mtx_assert(&psp->ps_mtx, MA_OWNED);
340 regs = td->td_frame;
341 oonstack = sigonstack(regs->tf_rsp);
342
343 if (cpu_max_ext_state_size > sizeof(struct savefpu) && use_xsave) {
344 xfpusave_len = cpu_max_ext_state_size - sizeof(struct savefpu);
345 xfpusave = __builtin_alloca(xfpusave_len);
346 } else {
347 xfpusave_len = 0;
348 xfpusave = NULL;
349 }
350
351 /* Save user context. */
352 bzero(&sf, sizeof(sf));
353 sf.sf_uc.uc_sigmask = *mask;
354 sf.sf_uc.uc_stack = td->td_sigstk;
355 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK)
356 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE;
357 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0;
358 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs));
359 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */
360 get_fpcontext(td, &sf.sf_uc.uc_mcontext, xfpusave, xfpusave_len);
361 fpstate_drop(td);
362 sf.sf_uc.uc_mcontext.mc_fsbase = pcb->pcb_fsbase;
363 sf.sf_uc.uc_mcontext.mc_gsbase = pcb->pcb_gsbase;
364 bzero(sf.sf_uc.uc_mcontext.mc_spare,
365 sizeof(sf.sf_uc.uc_mcontext.mc_spare));
366 bzero(sf.sf_uc.__spare__, sizeof(sf.sf_uc.__spare__));
367
368 /* Allocate space for the signal handler context. */
369 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
370 SIGISMEMBER(psp->ps_sigonstack, sig)) {
371 sp = td->td_sigstk.ss_sp + td->td_sigstk.ss_size;
372 #if defined(COMPAT_43)
373 td->td_sigstk.ss_flags |= SS_ONSTACK;
374 #endif
375 } else
376 sp = (char *)regs->tf_rsp - 128;
377 if (xfpusave != NULL) {
378 sp -= xfpusave_len;
379 sp = (char *)((unsigned long)sp & ~0x3Ful);
380 sf.sf_uc.uc_mcontext.mc_xfpustate = (register_t)sp;
381 }
382 sp -= sizeof(struct sigframe);
383 /* Align to 16 bytes. */
384 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul);
385
386 /* Translate the signal if appropriate. */
387 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize)
388 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
389
390 /* Build the argument list for the signal handler. */
391 regs->tf_rdi = sig; /* arg 1 in %rdi */
392 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */
393 bzero(&sf.sf_si, sizeof(sf.sf_si));
394 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
395 /* Signal handler installed with SA_SIGINFO. */
396 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */
397 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
398
399 /* Fill in POSIX parts */
400 sf.sf_si = ksi->ksi_info;
401 sf.sf_si.si_signo = sig; /* maybe a translated signal */
402 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */
403 } else {
404 /* Old FreeBSD-style arguments. */
405 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */
406 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */
407 sf.sf_ahu.sf_handler = catcher;
408 }
409 mtx_unlock(&psp->ps_mtx);
410 PROC_UNLOCK(p);
411
412 /*
413 * Copy the sigframe out to the user's stack.
414 */
415 if (copyout(&sf, sfp, sizeof(*sfp)) != 0 ||
416 (xfpusave != NULL && copyout(xfpusave,
417 (void *)sf.sf_uc.uc_mcontext.mc_xfpustate, xfpusave_len)
418 != 0)) {
419 #ifdef DEBUG
420 printf("process %ld has trashed its stack\n", (long)p->p_pid);
421 #endif
422 PROC_LOCK(p);
423 sigexit(td, SIGILL);
424 }
425
426 regs->tf_rsp = (long)sfp;
427 regs->tf_rip = p->p_sysent->sv_sigcode_base;
428 regs->tf_rflags &= ~(PSL_T | PSL_D);
429 regs->tf_cs = _ucodesel;
430 regs->tf_ds = _udatasel;
431 regs->tf_es = _udatasel;
432 regs->tf_fs = _ufssel;
433 regs->tf_gs = _ugssel;
434 regs->tf_flags = TF_HASSEGS;
435 set_pcb_flags(pcb, PCB_FULL_IRET);
436 PROC_LOCK(p);
437 mtx_lock(&psp->ps_mtx);
438 }
439
440 /*
441 * System call to cleanup state after a signal
442 * has been taken. Reset signal mask and
443 * stack state from context left by sendsig (above).
444 * Return to previous pc and psl as specified by
445 * context left by sendsig. Check carefully to
446 * make sure that the user has not modified the
447 * state to gain improper privileges.
448 *
449 * MPSAFE
450 */
451 int
452 sys_sigreturn(td, uap)
453 struct thread *td;
454 struct sigreturn_args /* {
455 const struct __ucontext *sigcntxp;
456 } */ *uap;
457 {
458 ucontext_t uc;
459 struct pcb *pcb;
460 struct proc *p;
461 struct trapframe *regs;
462 ucontext_t *ucp;
463 char *xfpustate;
464 size_t xfpustate_len;
465 long rflags;
466 int cs, error, ret;
467 ksiginfo_t ksi;
468
469 pcb = td->td_pcb;
470 p = td->td_proc;
471
472 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
473 if (error != 0) {
474 uprintf("pid %d (%s): sigreturn copyin failed\n",
475 p->p_pid, td->td_name);
476 return (error);
477 }
478 ucp = &uc;
479 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) {
480 uprintf("pid %d (%s): sigreturn mc_flags %x\n", p->p_pid,
481 td->td_name, ucp->uc_mcontext.mc_flags);
482 return (EINVAL);
483 }
484 regs = td->td_frame;
485 rflags = ucp->uc_mcontext.mc_rflags;
486 /*
487 * Don't allow users to change privileged or reserved flags.
488 */
489 /*
490 * XXX do allow users to change the privileged flag PSL_RF.
491 * The cpu sets PSL_RF in tf_rflags for faults. Debuggers
492 * should sometimes set it there too. tf_rflags is kept in
493 * the signal context during signal handling and there is no
494 * other place to remember it, so the PSL_RF bit may be
495 * corrupted by the signal handler without us knowing.
496 * Corruption of the PSL_RF bit at worst causes one more or
497 * one less debugger trap, so allowing it is fairly harmless.
498 */
499 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
500 uprintf("pid %d (%s): sigreturn rflags = 0x%lx\n", p->p_pid,
501 td->td_name, rflags);
502 return (EINVAL);
503 }
504
505 /*
506 * Don't allow users to load a valid privileged %cs. Let the
507 * hardware check for invalid selectors, excess privilege in
508 * other selectors, invalid %eip's and invalid %esp's.
509 */
510 cs = ucp->uc_mcontext.mc_cs;
511 if (!CS_SECURE(cs)) {
512 uprintf("pid %d (%s): sigreturn cs = 0x%x\n", p->p_pid,
513 td->td_name, cs);
514 ksiginfo_init_trap(&ksi);
515 ksi.ksi_signo = SIGBUS;
516 ksi.ksi_code = BUS_OBJERR;
517 ksi.ksi_trapno = T_PROTFLT;
518 ksi.ksi_addr = (void *)regs->tf_rip;
519 trapsignal(td, &ksi);
520 return (EINVAL);
521 }
522
523 if ((uc.uc_mcontext.mc_flags & _MC_HASFPXSTATE) != 0) {
524 xfpustate_len = uc.uc_mcontext.mc_xfpustate_len;
525 if (xfpustate_len > cpu_max_ext_state_size -
526 sizeof(struct savefpu)) {
527 uprintf("pid %d (%s): sigreturn xfpusave_len = 0x%zx\n",
528 p->p_pid, td->td_name, xfpustate_len);
529 return (EINVAL);
530 }
531 xfpustate = __builtin_alloca(xfpustate_len);
532 error = copyin((const void *)uc.uc_mcontext.mc_xfpustate,
533 xfpustate, xfpustate_len);
534 if (error != 0) {
535 uprintf(
536 "pid %d (%s): sigreturn copying xfpustate failed\n",
537 p->p_pid, td->td_name);
538 return (error);
539 }
540 } else {
541 xfpustate = NULL;
542 xfpustate_len = 0;
543 }
544 ret = set_fpcontext(td, &ucp->uc_mcontext, xfpustate, xfpustate_len);
545 if (ret != 0) {
546 uprintf("pid %d (%s): sigreturn set_fpcontext err %d\n",
547 p->p_pid, td->td_name, ret);
548 return (ret);
549 }
550 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs));
551 pcb->pcb_fsbase = ucp->uc_mcontext.mc_fsbase;
552 pcb->pcb_gsbase = ucp->uc_mcontext.mc_gsbase;
553
554 #if defined(COMPAT_43)
555 if (ucp->uc_mcontext.mc_onstack & 1)
556 td->td_sigstk.ss_flags |= SS_ONSTACK;
557 else
558 td->td_sigstk.ss_flags &= ~SS_ONSTACK;
559 #endif
560
561 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0);
562 set_pcb_flags(pcb, PCB_FULL_IRET);
563 return (EJUSTRETURN);
564 }
565
566 #ifdef COMPAT_FREEBSD4
567 int
568 freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap)
569 {
570
571 return sys_sigreturn(td, (struct sigreturn_args *)uap);
572 }
573 #endif
574
575
576 /*
577 * Machine dependent boot() routine
578 *
579 * I haven't seen anything to put here yet
580 * Possibly some stuff might be grafted back here from boot()
581 */
582 void
583 cpu_boot(int howto)
584 {
585 }
586
587 /*
588 * Flush the D-cache for non-DMA I/O so that the I-cache can
589 * be made coherent later.
590 */
591 void
592 cpu_flush_dcache(void *ptr, size_t len)
593 {
594 /* Not applicable */
595 }
596
597 /* Get current clock frequency for the given cpu id. */
598 int
599 cpu_est_clockrate(int cpu_id, uint64_t *rate)
600 {
601 uint64_t tsc1, tsc2;
602 uint64_t acnt, mcnt, perf;
603 register_t reg;
604
605 if (pcpu_find(cpu_id) == NULL || rate == NULL)
606 return (EINVAL);
607
608 /*
609 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist,
610 * DELAY(9) based logic fails.
611 */
612 if (tsc_is_invariant && !tsc_perf_stat)
613 return (EOPNOTSUPP);
614
615 #ifdef SMP
616 if (smp_cpus > 1) {
617 /* Schedule ourselves on the indicated cpu. */
618 thread_lock(curthread);
619 sched_bind(curthread, cpu_id);
620 thread_unlock(curthread);
621 }
622 #endif
623
624 /* Calibrate by measuring a short delay. */
625 reg = intr_disable();
626 if (tsc_is_invariant) {
627 wrmsr(MSR_MPERF, 0);
628 wrmsr(MSR_APERF, 0);
629 tsc1 = rdtsc();
630 DELAY(1000);
631 mcnt = rdmsr(MSR_MPERF);
632 acnt = rdmsr(MSR_APERF);
633 tsc2 = rdtsc();
634 intr_restore(reg);
635 perf = 1000 * acnt / mcnt;
636 *rate = (tsc2 - tsc1) * perf;
637 } else {
638 tsc1 = rdtsc();
639 DELAY(1000);
640 tsc2 = rdtsc();
641 intr_restore(reg);
642 *rate = (tsc2 - tsc1) * 1000;
643 }
644
645 #ifdef SMP
646 if (smp_cpus > 1) {
647 thread_lock(curthread);
648 sched_unbind(curthread);
649 thread_unlock(curthread);
650 }
651 #endif
652
653 return (0);
654 }
655
656 /*
657 * Shutdown the CPU as much as possible
658 */
659 void
660 cpu_halt(void)
661 {
662 for (;;)
663 __asm__ ("hlt");
664 }
665
666 void (*cpu_idle_hook)(void) = NULL; /* ACPI idle hook. */
667 static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */
668 static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */
669 TUNABLE_INT("machdep.idle_mwait", &idle_mwait);
670 SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait,
671 0, "Use MONITOR/MWAIT for short idle");
672
673 #define STATE_RUNNING 0x0
674 #define STATE_MWAIT 0x1
675 #define STATE_SLEEPING 0x2
676
677 static void
678 cpu_idle_acpi(int busy)
679 {
680 int *state;
681
682 state = (int *)PCPU_PTR(monitorbuf);
683 *state = STATE_SLEEPING;
684 disable_intr();
685 if (sched_runnable())
686 enable_intr();
687 else if (cpu_idle_hook)
688 cpu_idle_hook();
689 else
690 __asm __volatile("sti; hlt");
691 *state = STATE_RUNNING;
692 }
693
694 static void
695 cpu_idle_hlt(int busy)
696 {
697 int *state;
698
699 state = (int *)PCPU_PTR(monitorbuf);
700 *state = STATE_SLEEPING;
701 /*
702 * We must absolutely guarentee that hlt is the next instruction
703 * after sti or we introduce a timing window.
704 */
705 disable_intr();
706 if (sched_runnable())
707 enable_intr();
708 else
709 __asm __volatile("sti; hlt");
710 *state = STATE_RUNNING;
711 }
712
713 /*
714 * MWAIT cpu power states. Lower 4 bits are sub-states.
715 */
716 #define MWAIT_C0 0xf0
717 #define MWAIT_C1 0x00
718 #define MWAIT_C2 0x10
719 #define MWAIT_C3 0x20
720 #define MWAIT_C4 0x30
721
722 static void
723 cpu_idle_mwait(int busy)
724 {
725 int *state;
726
727 state = (int *)PCPU_PTR(monitorbuf);
728 *state = STATE_MWAIT;
729 if (!sched_runnable()) {
730 cpu_monitor(state, 0, 0);
731 if (*state == STATE_MWAIT)
732 cpu_mwait(0, MWAIT_C1);
733 }
734 *state = STATE_RUNNING;
735 }
736
737 static void
738 cpu_idle_spin(int busy)
739 {
740 int *state;
741 int i;
742
743 state = (int *)PCPU_PTR(monitorbuf);
744 *state = STATE_RUNNING;
745 for (i = 0; i < 1000; i++) {
746 if (sched_runnable())
747 return;
748 cpu_spinwait();
749 }
750 }
751
752 /*
753 * C1E renders the local APIC timer dead, so we disable it by
754 * reading the Interrupt Pending Message register and clearing
755 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
756 *
757 * Reference:
758 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors"
759 * #32559 revision 3.00+
760 */
761 #define MSR_AMDK8_IPM 0xc0010055
762 #define AMDK8_SMIONCMPHALT (1ULL << 27)
763 #define AMDK8_C1EONCMPHALT (1ULL << 28)
764 #define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT)
765
766 static void
767 cpu_probe_amdc1e(void)
768 {
769
770 /*
771 * Detect the presence of C1E capability mostly on latest
772 * dual-cores (or future) k8 family.
773 */
774 if (cpu_vendor_id == CPU_VENDOR_AMD &&
775 (cpu_id & 0x00000f00) == 0x00000f00 &&
776 (cpu_id & 0x0fff0000) >= 0x00040000) {
777 cpu_ident_amdc1e = 1;
778 }
779 }
780
781 void (*cpu_idle_fn)(int) = cpu_idle_acpi;
782
783 void
784 cpu_idle(int busy)
785 {
786 uint64_t msr;
787
788 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d",
789 busy, curcpu);
790 #ifdef MP_WATCHDOG
791 ap_watchdog(PCPU_GET(cpuid));
792 #endif
793 /* If we are busy - try to use fast methods. */
794 if (busy) {
795 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) {
796 cpu_idle_mwait(busy);
797 goto out;
798 }
799 }
800
801 /* If we have time - switch timers into idle mode. */
802 if (!busy) {
803 critical_enter();
804 cpu_idleclock();
805 }
806
807 /* Apply AMD APIC timer C1E workaround. */
808 if (cpu_ident_amdc1e && cpu_disable_deep_sleep) {
809 msr = rdmsr(MSR_AMDK8_IPM);
810 if (msr & AMDK8_CMPHALT)
811 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT);
812 }
813
814 /* Call main idle method. */
815 cpu_idle_fn(busy);
816
817 /* Switch timers mack into active mode. */
818 if (!busy) {
819 cpu_activeclock();
820 critical_exit();
821 }
822 out:
823 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done",
824 busy, curcpu);
825 }
826
827 int
828 cpu_idle_wakeup(int cpu)
829 {
830 struct pcpu *pcpu;
831 int *state;
832
833 pcpu = pcpu_find(cpu);
834 state = (int *)pcpu->pc_monitorbuf;
835 /*
836 * This doesn't need to be atomic since missing the race will
837 * simply result in unnecessary IPIs.
838 */
839 if (*state == STATE_SLEEPING)
840 return (0);
841 if (*state == STATE_MWAIT)
842 *state = STATE_RUNNING;
843 return (1);
844 }
845
846 /*
847 * Ordered by speed/power consumption.
848 */
849 struct {
850 void *id_fn;
851 char *id_name;
852 } idle_tbl[] = {
853 { cpu_idle_spin, "spin" },
854 { cpu_idle_mwait, "mwait" },
855 { cpu_idle_hlt, "hlt" },
856 { cpu_idle_acpi, "acpi" },
857 { NULL, NULL }
858 };
859
860 static int
861 idle_sysctl_available(SYSCTL_HANDLER_ARGS)
862 {
863 char *avail, *p;
864 int error;
865 int i;
866
867 avail = malloc(256, M_TEMP, M_WAITOK);
868 p = avail;
869 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
870 if (strstr(idle_tbl[i].id_name, "mwait") &&
871 (cpu_feature2 & CPUID2_MON) == 0)
872 continue;
873 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
874 cpu_idle_hook == NULL)
875 continue;
876 p += sprintf(p, "%s%s", p != avail ? ", " : "",
877 idle_tbl[i].id_name);
878 }
879 error = sysctl_handle_string(oidp, avail, 0, req);
880 free(avail, M_TEMP);
881 return (error);
882 }
883
884 SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD,
885 0, 0, idle_sysctl_available, "A", "list of available idle functions");
886
887 static int
888 idle_sysctl(SYSCTL_HANDLER_ARGS)
889 {
890 char buf[16];
891 int error;
892 char *p;
893 int i;
894
895 p = "unknown";
896 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
897 if (idle_tbl[i].id_fn == cpu_idle_fn) {
898 p = idle_tbl[i].id_name;
899 break;
900 }
901 }
902 strncpy(buf, p, sizeof(buf));
903 error = sysctl_handle_string(oidp, buf, sizeof(buf), req);
904 if (error != 0 || req->newptr == NULL)
905 return (error);
906 for (i = 0; idle_tbl[i].id_name != NULL; i++) {
907 if (strstr(idle_tbl[i].id_name, "mwait") &&
908 (cpu_feature2 & CPUID2_MON) == 0)
909 continue;
910 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 &&
911 cpu_idle_hook == NULL)
912 continue;
913 if (strcmp(idle_tbl[i].id_name, buf))
914 continue;
915 cpu_idle_fn = idle_tbl[i].id_fn;
916 return (0);
917 }
918 return (EINVAL);
919 }
920
921 SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0,
922 idle_sysctl, "A", "currently selected idle function");
923
924 /*
925 * Reset registers to default values on exec.
926 */
927 void
928 exec_setregs(struct thread *td, struct image_params *imgp, u_long stack)
929 {
930 struct trapframe *regs = td->td_frame;
931 struct pcb *pcb = td->td_pcb;
932
933 mtx_lock(&dt_lock);
934 if (td->td_proc->p_md.md_ldt != NULL)
935 user_ldt_free(td);
936 else
937 mtx_unlock(&dt_lock);
938
939 pcb->pcb_fsbase = 0;
940 pcb->pcb_gsbase = 0;
941 clear_pcb_flags(pcb, PCB_32BIT);
942 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__;
943 set_pcb_flags(pcb, PCB_FULL_IRET);
944
945 bzero((char *)regs, sizeof(struct trapframe));
946 regs->tf_rip = imgp->entry_addr;
947 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8;
948 regs->tf_rdi = stack; /* argv */
949 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
950 regs->tf_ss = _udatasel;
951 regs->tf_cs = _ucodesel;
952 regs->tf_ds = _udatasel;
953 regs->tf_es = _udatasel;
954 regs->tf_fs = _ufssel;
955 regs->tf_gs = _ugssel;
956 regs->tf_flags = TF_HASSEGS;
957 td->td_retval[1] = 0;
958
959 /*
960 * Reset the hardware debug registers if they were in use.
961 * They won't have any meaning for the newly exec'd process.
962 */
963 if (pcb->pcb_flags & PCB_DBREGS) {
964 pcb->pcb_dr0 = 0;
965 pcb->pcb_dr1 = 0;
966 pcb->pcb_dr2 = 0;
967 pcb->pcb_dr3 = 0;
968 pcb->pcb_dr6 = 0;
969 pcb->pcb_dr7 = 0;
970 if (pcb == curpcb) {
971 /*
972 * Clear the debug registers on the running
973 * CPU, otherwise they will end up affecting
974 * the next process we switch to.
975 */
976 reset_dbregs();
977 }
978 clear_pcb_flags(pcb, PCB_DBREGS);
979 }
980
981 /*
982 * Drop the FP state if we hold it, so that the process gets a
983 * clean FP state if it uses the FPU again.
984 */
985 fpstate_drop(td);
986 }
987
988 void
989 cpu_setregs(void)
990 {
991 register_t cr0;
992
993 cr0 = rcr0();
994 /*
995 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the
996 * BSP. See the comments there about why we set them.
997 */
998 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM;
999 load_cr0(cr0);
1000 }
1001
1002 /*
1003 * Initialize amd64 and configure to run kernel
1004 */
1005
1006 /*
1007 * Initialize segments & interrupt table
1008 */
1009
1010 struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */
1011 static struct gate_descriptor idt0[NIDT];
1012 struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */
1013
1014 static char dblfault_stack[PAGE_SIZE] __aligned(16);
1015
1016 static char nmi0_stack[PAGE_SIZE] __aligned(16);
1017 CTASSERT(sizeof(struct nmi_pcpu) == 16);
1018
1019 struct amd64tss common_tss[MAXCPU];
1020
1021 /*
1022 * Software prototypes -- in more palatable form.
1023 *
1024 * Keep GUFS32, GUGS32, GUCODE32 and GUDATA at the same
1025 * slots as corresponding segments for i386 kernel.
1026 */
1027 struct soft_segment_descriptor gdt_segs[] = {
1028 /* GNULL_SEL 0 Null Descriptor */
1029 { .ssd_base = 0x0,
1030 .ssd_limit = 0x0,
1031 .ssd_type = 0,
1032 .ssd_dpl = 0,
1033 .ssd_p = 0,
1034 .ssd_long = 0,
1035 .ssd_def32 = 0,
1036 .ssd_gran = 0 },
1037 /* GNULL2_SEL 1 Null Descriptor */
1038 { .ssd_base = 0x0,
1039 .ssd_limit = 0x0,
1040 .ssd_type = 0,
1041 .ssd_dpl = 0,
1042 .ssd_p = 0,
1043 .ssd_long = 0,
1044 .ssd_def32 = 0,
1045 .ssd_gran = 0 },
1046 /* GUFS32_SEL 2 32 bit %gs Descriptor for user */
1047 { .ssd_base = 0x0,
1048 .ssd_limit = 0xfffff,
1049 .ssd_type = SDT_MEMRWA,
1050 .ssd_dpl = SEL_UPL,
1051 .ssd_p = 1,
1052 .ssd_long = 0,
1053 .ssd_def32 = 1,
1054 .ssd_gran = 1 },
1055 /* GUGS32_SEL 3 32 bit %fs Descriptor for user */
1056 { .ssd_base = 0x0,
1057 .ssd_limit = 0xfffff,
1058 .ssd_type = SDT_MEMRWA,
1059 .ssd_dpl = SEL_UPL,
1060 .ssd_p = 1,
1061 .ssd_long = 0,
1062 .ssd_def32 = 1,
1063 .ssd_gran = 1 },
1064 /* GCODE_SEL 4 Code Descriptor for kernel */
1065 { .ssd_base = 0x0,
1066 .ssd_limit = 0xfffff,
1067 .ssd_type = SDT_MEMERA,
1068 .ssd_dpl = SEL_KPL,
1069 .ssd_p = 1,
1070 .ssd_long = 1,
1071 .ssd_def32 = 0,
1072 .ssd_gran = 1 },
1073 /* GDATA_SEL 5 Data Descriptor for kernel */
1074 { .ssd_base = 0x0,
1075 .ssd_limit = 0xfffff,
1076 .ssd_type = SDT_MEMRWA,
1077 .ssd_dpl = SEL_KPL,
1078 .ssd_p = 1,
1079 .ssd_long = 1,
1080 .ssd_def32 = 0,
1081 .ssd_gran = 1 },
1082 /* GUCODE32_SEL 6 32 bit Code Descriptor for user */
1083 { .ssd_base = 0x0,
1084 .ssd_limit = 0xfffff,
1085 .ssd_type = SDT_MEMERA,
1086 .ssd_dpl = SEL_UPL,
1087 .ssd_p = 1,
1088 .ssd_long = 0,
1089 .ssd_def32 = 1,
1090 .ssd_gran = 1 },
1091 /* GUDATA_SEL 7 32/64 bit Data Descriptor for user */
1092 { .ssd_base = 0x0,
1093 .ssd_limit = 0xfffff,
1094 .ssd_type = SDT_MEMRWA,
1095 .ssd_dpl = SEL_UPL,
1096 .ssd_p = 1,
1097 .ssd_long = 0,
1098 .ssd_def32 = 1,
1099 .ssd_gran = 1 },
1100 /* GUCODE_SEL 8 64 bit Code Descriptor for user */
1101 { .ssd_base = 0x0,
1102 .ssd_limit = 0xfffff,
1103 .ssd_type = SDT_MEMERA,
1104 .ssd_dpl = SEL_UPL,
1105 .ssd_p = 1,
1106 .ssd_long = 1,
1107 .ssd_def32 = 0,
1108 .ssd_gran = 1 },
1109 /* GPROC0_SEL 9 Proc 0 Tss Descriptor */
1110 { .ssd_base = 0x0,
1111 .ssd_limit = sizeof(struct amd64tss) + IOPAGES * PAGE_SIZE - 1,
1112 .ssd_type = SDT_SYSTSS,
1113 .ssd_dpl = SEL_KPL,
1114 .ssd_p = 1,
1115 .ssd_long = 0,
1116 .ssd_def32 = 0,
1117 .ssd_gran = 0 },
1118 /* Actually, the TSS is a system descriptor which is double size */
1119 { .ssd_base = 0x0,
1120 .ssd_limit = 0x0,
1121 .ssd_type = 0,
1122 .ssd_dpl = 0,
1123 .ssd_p = 0,
1124 .ssd_long = 0,
1125 .ssd_def32 = 0,
1126 .ssd_gran = 0 },
1127 /* GUSERLDT_SEL 11 LDT Descriptor */
1128 { .ssd_base = 0x0,
1129 .ssd_limit = 0x0,
1130 .ssd_type = 0,
1131 .ssd_dpl = 0,
1132 .ssd_p = 0,
1133 .ssd_long = 0,
1134 .ssd_def32 = 0,
1135 .ssd_gran = 0 },
1136 /* GUSERLDT_SEL 12 LDT Descriptor, double size */
1137 { .ssd_base = 0x0,
1138 .ssd_limit = 0x0,
1139 .ssd_type = 0,
1140 .ssd_dpl = 0,
1141 .ssd_p = 0,
1142 .ssd_long = 0,
1143 .ssd_def32 = 0,
1144 .ssd_gran = 0 },
1145 };
1146
1147 void
1148 setidt(idx, func, typ, dpl, ist)
1149 int idx;
1150 inthand_t *func;
1151 int typ;
1152 int dpl;
1153 int ist;
1154 {
1155 struct gate_descriptor *ip;
1156
1157 ip = idt + idx;
1158 ip->gd_looffset = (uintptr_t)func;
1159 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1160 ip->gd_ist = ist;
1161 ip->gd_xx = 0;
1162 ip->gd_type = typ;
1163 ip->gd_dpl = dpl;
1164 ip->gd_p = 1;
1165 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1166 }
1167
1168 extern inthand_t
1169 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1170 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1171 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1172 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1173 IDTVEC(xmm), IDTVEC(dblfault),
1174 #ifdef KDTRACE_HOOKS
1175 IDTVEC(dtrace_ret),
1176 #endif
1177 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1178
1179 #ifdef DDB
1180 /*
1181 * Display the index and function name of any IDT entries that don't use
1182 * the default 'rsvd' entry point.
1183 */
1184 DB_SHOW_COMMAND(idt, db_show_idt)
1185 {
1186 struct gate_descriptor *ip;
1187 int idx;
1188 uintptr_t func;
1189
1190 ip = idt;
1191 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) {
1192 func = ((long)ip->gd_hioffset << 16 | ip->gd_looffset);
1193 if (func != (uintptr_t)&IDTVEC(rsvd)) {
1194 db_printf("%3d\t", idx);
1195 db_printsym(func, DB_STGY_PROC);
1196 db_printf("\n");
1197 }
1198 ip++;
1199 }
1200 }
1201 #endif
1202
1203 void
1204 sdtossd(sd, ssd)
1205 struct user_segment_descriptor *sd;
1206 struct soft_segment_descriptor *ssd;
1207 {
1208
1209 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1210 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1211 ssd->ssd_type = sd->sd_type;
1212 ssd->ssd_dpl = sd->sd_dpl;
1213 ssd->ssd_p = sd->sd_p;
1214 ssd->ssd_long = sd->sd_long;
1215 ssd->ssd_def32 = sd->sd_def32;
1216 ssd->ssd_gran = sd->sd_gran;
1217 }
1218
1219 void
1220 ssdtosd(ssd, sd)
1221 struct soft_segment_descriptor *ssd;
1222 struct user_segment_descriptor *sd;
1223 {
1224
1225 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1226 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1227 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1228 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1229 sd->sd_type = ssd->ssd_type;
1230 sd->sd_dpl = ssd->ssd_dpl;
1231 sd->sd_p = ssd->ssd_p;
1232 sd->sd_long = ssd->ssd_long;
1233 sd->sd_def32 = ssd->ssd_def32;
1234 sd->sd_gran = ssd->ssd_gran;
1235 }
1236
1237 void
1238 ssdtosyssd(ssd, sd)
1239 struct soft_segment_descriptor *ssd;
1240 struct system_segment_descriptor *sd;
1241 {
1242
1243 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1244 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1245 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1246 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1247 sd->sd_type = ssd->ssd_type;
1248 sd->sd_dpl = ssd->ssd_dpl;
1249 sd->sd_p = ssd->ssd_p;
1250 sd->sd_gran = ssd->ssd_gran;
1251 }
1252
1253 #if !defined(DEV_ATPIC) && defined(DEV_ISA)
1254 #include <isa/isavar.h>
1255 #include <isa/isareg.h>
1256 /*
1257 * Return a bitmap of the current interrupt requests. This is 8259-specific
1258 * and is only suitable for use at probe time.
1259 * This is only here to pacify sio. It is NOT FATAL if this doesn't work.
1260 * It shouldn't be here. There should probably be an APIC centric
1261 * implementation in the apic driver code, if at all.
1262 */
1263 intrmask_t
1264 isa_irq_pending(void)
1265 {
1266 u_char irr1;
1267 u_char irr2;
1268
1269 irr1 = inb(IO_ICU1);
1270 irr2 = inb(IO_ICU2);
1271 return ((irr2 << 8) | irr1);
1272 }
1273 #endif
1274
1275 u_int basemem;
1276
1277 static int
1278 add_smap_entry(struct bios_smap *smap, vm_paddr_t *physmap, int *physmap_idxp)
1279 {
1280 int i, insert_idx, physmap_idx;
1281
1282 physmap_idx = *physmap_idxp;
1283
1284 if (boothowto & RB_VERBOSE)
1285 printf("SMAP type=%02x base=%016lx len=%016lx\n",
1286 smap->type, smap->base, smap->length);
1287
1288 if (smap->type != SMAP_TYPE_MEMORY)
1289 return (1);
1290
1291 if (smap->length == 0)
1292 return (0);
1293
1294 /*
1295 * Find insertion point while checking for overlap. Start off by
1296 * assuming the new entry will be added to the end.
1297 */
1298 insert_idx = physmap_idx + 2;
1299 for (i = 0; i <= physmap_idx; i += 2) {
1300 if (smap->base < physmap[i + 1]) {
1301 if (smap->base + smap->length <= physmap[i]) {
1302 insert_idx = i;
1303 break;
1304 }
1305 if (boothowto & RB_VERBOSE)
1306 printf(
1307 "Overlapping memory regions, ignoring second region\n");
1308 return (1);
1309 }
1310 }
1311
1312 /* See if we can prepend to the next entry. */
1313 if (insert_idx <= physmap_idx &&
1314 smap->base + smap->length == physmap[insert_idx]) {
1315 physmap[insert_idx] = smap->base;
1316 return (1);
1317 }
1318
1319 /* See if we can append to the previous entry. */
1320 if (insert_idx > 0 && smap->base == physmap[insert_idx - 1]) {
1321 physmap[insert_idx - 1] += smap->length;
1322 return (1);
1323 }
1324
1325 physmap_idx += 2;
1326 *physmap_idxp = physmap_idx;
1327 if (physmap_idx == PHYSMAP_SIZE) {
1328 printf(
1329 "Too many segments in the physical address map, giving up\n");
1330 return (0);
1331 }
1332
1333 /*
1334 * Move the last 'N' entries down to make room for the new
1335 * entry if needed.
1336 */
1337 for (i = physmap_idx; i > insert_idx; i -= 2) {
1338 physmap[i] = physmap[i - 2];
1339 physmap[i + 1] = physmap[i - 1];
1340 }
1341
1342 /* Insert the new entry. */
1343 physmap[insert_idx] = smap->base;
1344 physmap[insert_idx + 1] = smap->base + smap->length;
1345 return (1);
1346 }
1347
1348 /*
1349 * Populate the (physmap) array with base/bound pairs describing the
1350 * available physical memory in the system, then test this memory and
1351 * build the phys_avail array describing the actually-available memory.
1352 *
1353 * Total memory size may be set by the kernel environment variable
1354 * hw.physmem or the compile-time define MAXMEM.
1355 *
1356 * XXX first should be vm_paddr_t.
1357 */
1358 static void
1359 getmemsize(caddr_t kmdp, u_int64_t first)
1360 {
1361 int i, physmap_idx, pa_indx, da_indx;
1362 vm_paddr_t pa, physmap[PHYSMAP_SIZE];
1363 u_long physmem_start, physmem_tunable, memtest;
1364 pt_entry_t *pte;
1365 struct bios_smap *smapbase, *smap, *smapend;
1366 u_int32_t smapsize;
1367 quad_t dcons_addr, dcons_size;
1368
1369 bzero(physmap, sizeof(physmap));
1370 basemem = 0;
1371 physmap_idx = 0;
1372
1373 /*
1374 * get memory map from INT 15:E820, kindly supplied by the loader.
1375 *
1376 * subr_module.c says:
1377 * "Consumer may safely assume that size value precedes data."
1378 * ie: an int32_t immediately precedes smap.
1379 */
1380 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1381 MODINFO_METADATA | MODINFOMD_SMAP);
1382 if (smapbase == NULL)
1383 panic("No BIOS smap info from loader!");
1384
1385 smapsize = *((u_int32_t *)smapbase - 1);
1386 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1387
1388 for (smap = smapbase; smap < smapend; smap++)
1389 if (!add_smap_entry(smap, physmap, &physmap_idx))
1390 break;
1391
1392 /*
1393 * Find the 'base memory' segment for SMP
1394 */
1395 basemem = 0;
1396 for (i = 0; i <= physmap_idx; i += 2) {
1397 if (physmap[i] == 0x00000000) {
1398 basemem = physmap[i + 1] / 1024;
1399 break;
1400 }
1401 }
1402 if (basemem == 0)
1403 panic("BIOS smap did not include a basemem segment!");
1404
1405 #ifdef SMP
1406 /* make hole for AP bootstrap code */
1407 physmap[1] = mp_bootaddress(physmap[1] / 1024);
1408 #endif
1409
1410 /*
1411 * Maxmem isn't the "maximum memory", it's one larger than the
1412 * highest page of the physical address space. It should be
1413 * called something like "Maxphyspage". We may adjust this
1414 * based on ``hw.physmem'' and the results of the memory test.
1415 */
1416 Maxmem = atop(physmap[physmap_idx + 1]);
1417
1418 #ifdef MAXMEM
1419 Maxmem = MAXMEM / 4;
1420 #endif
1421
1422 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1423 Maxmem = atop(physmem_tunable);
1424
1425 /*
1426 * By default enable the memory test on real hardware, and disable
1427 * it if we appear to be running in a VM. This avoids touching all
1428 * pages unnecessarily, which doesn't matter on real hardware but is
1429 * bad for shared VM hosts. Use a general name so that
1430 * one could eventually do more with the code than just disable it.
1431 */
1432 memtest = (vm_guest > VM_GUEST_NO) ? 0 : 1;
1433 TUNABLE_ULONG_FETCH("hw.memtest.tests", &memtest);
1434
1435 /*
1436 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1437 * in the system.
1438 */
1439 if (Maxmem > atop(physmap[physmap_idx + 1]))
1440 Maxmem = atop(physmap[physmap_idx + 1]);
1441
1442 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1443 (boothowto & RB_VERBOSE))
1444 printf("Physical memory use set to %ldK\n", Maxmem * 4);
1445
1446 /* call pmap initialization to make new kernel address space */
1447 pmap_bootstrap(&first);
1448
1449 /*
1450 * Size up each available chunk of physical memory.
1451 *
1452 * XXX Some BIOSes corrupt low 64KB between suspend and resume.
1453 * By default, mask off the first 16 pages unless we appear to be
1454 * running in a VM.
1455 */
1456 physmem_start = (vm_guest > VM_GUEST_NO ? 1 : 16) << PAGE_SHIFT;
1457 TUNABLE_ULONG_FETCH("hw.physmem.start", &physmem_start);
1458 if (physmem_start < PAGE_SIZE)
1459 physmap[0] = PAGE_SIZE;
1460 else if (physmem_start >= physmap[1])
1461 physmap[0] = round_page(physmap[1] - PAGE_SIZE);
1462 else
1463 physmap[0] = round_page(physmem_start);
1464 pa_indx = 0;
1465 da_indx = 1;
1466 phys_avail[pa_indx++] = physmap[0];
1467 phys_avail[pa_indx] = physmap[0];
1468 dump_avail[da_indx] = physmap[0];
1469 pte = CMAP1;
1470
1471 /*
1472 * Get dcons buffer address
1473 */
1474 if (getenv_quad("dcons.addr", &dcons_addr) == 0 ||
1475 getenv_quad("dcons.size", &dcons_size) == 0)
1476 dcons_addr = 0;
1477
1478 /*
1479 * physmap is in bytes, so when converting to page boundaries,
1480 * round up the start address and round down the end address.
1481 */
1482 for (i = 0; i <= physmap_idx; i += 2) {
1483 vm_paddr_t end;
1484
1485 end = ptoa((vm_paddr_t)Maxmem);
1486 if (physmap[i + 1] < end)
1487 end = trunc_page(physmap[i + 1]);
1488 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) {
1489 int tmp, page_bad, full;
1490 int *ptr = (int *)CADDR1;
1491
1492 full = FALSE;
1493 /*
1494 * block out kernel memory as not available.
1495 */
1496 if (pa >= (vm_paddr_t)kernphys && pa < first)
1497 goto do_dump_avail;
1498
1499 /*
1500 * block out dcons buffer
1501 */
1502 if (dcons_addr > 0
1503 && pa >= trunc_page(dcons_addr)
1504 && pa < dcons_addr + dcons_size)
1505 goto do_dump_avail;
1506
1507 page_bad = FALSE;
1508 if (memtest == 0)
1509 goto skip_memtest;
1510
1511 /*
1512 * map page into kernel: valid, read/write,non-cacheable
1513 */
1514 *pte = pa | PG_V | PG_RW | PG_N;
1515 invltlb();
1516
1517 tmp = *(int *)ptr;
1518 /*
1519 * Test for alternating 1's and 0's
1520 */
1521 *(volatile int *)ptr = 0xaaaaaaaa;
1522 if (*(volatile int *)ptr != 0xaaaaaaaa)
1523 page_bad = TRUE;
1524 /*
1525 * Test for alternating 0's and 1's
1526 */
1527 *(volatile int *)ptr = 0x55555555;
1528 if (*(volatile int *)ptr != 0x55555555)
1529 page_bad = TRUE;
1530 /*
1531 * Test for all 1's
1532 */
1533 *(volatile int *)ptr = 0xffffffff;
1534 if (*(volatile int *)ptr != 0xffffffff)
1535 page_bad = TRUE;
1536 /*
1537 * Test for all 0's
1538 */
1539 *(volatile int *)ptr = 0x0;
1540 if (*(volatile int *)ptr != 0x0)
1541 page_bad = TRUE;
1542 /*
1543 * Restore original value.
1544 */
1545 *(int *)ptr = tmp;
1546
1547 skip_memtest:
1548 /*
1549 * Adjust array of valid/good pages.
1550 */
1551 if (page_bad == TRUE)
1552 continue;
1553 /*
1554 * If this good page is a continuation of the
1555 * previous set of good pages, then just increase
1556 * the end pointer. Otherwise start a new chunk.
1557 * Note that "end" points one higher than end,
1558 * making the range >= start and < end.
1559 * If we're also doing a speculative memory
1560 * test and we at or past the end, bump up Maxmem
1561 * so that we keep going. The first bad page
1562 * will terminate the loop.
1563 */
1564 if (phys_avail[pa_indx] == pa) {
1565 phys_avail[pa_indx] += PAGE_SIZE;
1566 } else {
1567 pa_indx++;
1568 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
1569 printf(
1570 "Too many holes in the physical address space, giving up\n");
1571 pa_indx--;
1572 full = TRUE;
1573 goto do_dump_avail;
1574 }
1575 phys_avail[pa_indx++] = pa; /* start */
1576 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */
1577 }
1578 physmem++;
1579 do_dump_avail:
1580 if (dump_avail[da_indx] == pa) {
1581 dump_avail[da_indx] += PAGE_SIZE;
1582 } else {
1583 da_indx++;
1584 if (da_indx == DUMP_AVAIL_ARRAY_END) {
1585 da_indx--;
1586 goto do_next;
1587 }
1588 dump_avail[da_indx++] = pa; /* start */
1589 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */
1590 }
1591 do_next:
1592 if (full)
1593 break;
1594 }
1595 }
1596 *pte = 0;
1597 invltlb();
1598
1599 /*
1600 * XXX
1601 * The last chunk must contain at least one page plus the message
1602 * buffer to avoid complicating other code (message buffer address
1603 * calculation, etc.).
1604 */
1605 while (phys_avail[pa_indx - 1] + PAGE_SIZE +
1606 round_page(msgbufsize) >= phys_avail[pa_indx]) {
1607 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1608 phys_avail[pa_indx--] = 0;
1609 phys_avail[pa_indx--] = 0;
1610 }
1611
1612 Maxmem = atop(phys_avail[pa_indx]);
1613
1614 /* Trim off space for the message buffer. */
1615 phys_avail[pa_indx] -= round_page(msgbufsize);
1616
1617 /* Map the message buffer. */
1618 msgbufp = (struct msgbuf *)PHYS_TO_DMAP(phys_avail[pa_indx]);
1619 }
1620
1621 u_int64_t
1622 hammer_time(u_int64_t modulep, u_int64_t physfree)
1623 {
1624 caddr_t kmdp;
1625 int gsel_tss, x;
1626 struct pcpu *pc;
1627 struct nmi_pcpu *np;
1628 struct xstate_hdr *xhdr;
1629 u_int64_t msr;
1630 char *env;
1631 size_t kstack0_sz;
1632
1633 thread0.td_kstack = physfree + KERNBASE;
1634 thread0.td_kstack_pages = KSTACK_PAGES;
1635 kstack0_sz = thread0.td_kstack_pages * PAGE_SIZE;
1636 bzero((void *)thread0.td_kstack, kstack0_sz);
1637 physfree += kstack0_sz;
1638
1639 /*
1640 * This may be done better later if it gets more high level
1641 * components in it. If so just link td->td_proc here.
1642 */
1643 proc_linkup0(&proc0, &thread0);
1644
1645 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE);
1646 preload_bootstrap_relocate(KERNBASE);
1647 kmdp = preload_search_by_type("elf kernel");
1648 if (kmdp == NULL)
1649 kmdp = preload_search_by_type("elf64 kernel");
1650 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
1651 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE;
1652 #ifdef DDB
1653 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
1654 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
1655 #endif
1656
1657 /* Init basic tunables, hz etc */
1658 init_param1();
1659
1660 /*
1661 * make gdt memory segments
1662 */
1663 for (x = 0; x < NGDT; x++) {
1664 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) &&
1665 x != GUSERLDT_SEL && x != (GUSERLDT_SEL) + 1)
1666 ssdtosd(&gdt_segs[x], &gdt[x]);
1667 }
1668 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0];
1669 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1670 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
1671
1672 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1673 r_gdt.rd_base = (long) gdt;
1674 lgdt(&r_gdt);
1675 pc = &__pcpu[0];
1676
1677 wrmsr(MSR_FSBASE, 0); /* User value */
1678 wrmsr(MSR_GSBASE, (u_int64_t)pc);
1679 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
1680
1681 pcpu_init(pc, 0, sizeof(struct pcpu));
1682 dpcpu_init((void *)(physfree + KERNBASE), 0);
1683 physfree += DPCPU_SIZE;
1684 PCPU_SET(prvspace, pc);
1685 PCPU_SET(curthread, &thread0);
1686 PCPU_SET(tssp, &common_tss[0]);
1687 PCPU_SET(commontssp, &common_tss[0]);
1688 PCPU_SET(tss, (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
1689 PCPU_SET(ldt, (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL]);
1690 PCPU_SET(fs32p, &gdt[GUFS32_SEL]);
1691 PCPU_SET(gs32p, &gdt[GUGS32_SEL]);
1692
1693 /*
1694 * Initialize mutexes.
1695 *
1696 * icu_lock: in order to allow an interrupt to occur in a critical
1697 * section, to set pcpu->ipending (etc...) properly, we
1698 * must be able to get the icu lock, so it can't be
1699 * under witness.
1700 */
1701 mutex_init();
1702 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS);
1703 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_DEF);
1704
1705 /* exceptions */
1706 for (x = 0; x < NIDT; x++)
1707 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
1708 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
1709 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
1710 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2);
1711 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
1712 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
1713 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
1714 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
1715 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
1716 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
1717 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
1718 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
1719 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
1720 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
1721 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
1722 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
1723 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
1724 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
1725 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
1726 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
1727 #ifdef KDTRACE_HOOKS
1728 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret), SDT_SYSIGT, SEL_UPL, 0);
1729 #endif
1730
1731 r_idt.rd_limit = sizeof(idt0) - 1;
1732 r_idt.rd_base = (long) idt;
1733 lidt(&r_idt);
1734
1735 /*
1736 * Initialize the i8254 before the console so that console
1737 * initialization can use DELAY().
1738 */
1739 i8254_init();
1740
1741 /*
1742 * Initialize the console before we print anything out.
1743 */
1744 cninit();
1745
1746 #ifdef DEV_ISA
1747 #ifdef DEV_ATPIC
1748 elcr_probe();
1749 atpic_startup();
1750 #else
1751 /* Reset and mask the atpics and leave them shut down. */
1752 atpic_reset();
1753
1754 /*
1755 * Point the ICU spurious interrupt vectors at the APIC spurious
1756 * interrupt handler.
1757 */
1758 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0);
1759 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0);
1760 #endif
1761 #else
1762 #error "have you forgotten the isa device?";
1763 #endif
1764
1765 kdb_init();
1766
1767 #ifdef KDB
1768 if (boothowto & RB_KDB)
1769 kdb_enter(KDB_WHY_BOOTFLAGS,
1770 "Boot flags requested debugger");
1771 #endif
1772
1773 identify_cpu(); /* Final stage of CPU initialization */
1774 initializecpu(); /* Initialize CPU registers */
1775 initializecpucache();
1776
1777 /* doublefault stack space, runs on ist1 */
1778 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)];
1779
1780 /*
1781 * NMI stack, runs on ist2. The pcpu pointer is stored just
1782 * above the start of the ist2 stack.
1783 */
1784 np = ((struct nmi_pcpu *) &nmi0_stack[sizeof(nmi0_stack)]) - 1;
1785 np->np_pcpu = (register_t) pc;
1786 common_tss[0].tss_ist2 = (long) np;
1787
1788 /* Set the IO permission bitmap (empty due to tss seg limit) */
1789 common_tss[0].tss_iobase = sizeof(struct amd64tss) +
1790 IOPAGES * PAGE_SIZE;
1791
1792 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
1793 ltr(gsel_tss);
1794
1795 /* Set up the fast syscall stuff */
1796 msr = rdmsr(MSR_EFER) | EFER_SCE;
1797 wrmsr(MSR_EFER, msr);
1798 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
1799 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
1800 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
1801 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
1802 wrmsr(MSR_STAR, msr);
1803 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
1804
1805 getmemsize(kmdp, physfree);
1806 init_param2(physmem);
1807
1808 /* now running on new page tables, configured,and u/iom is accessible */
1809
1810 msgbufinit(msgbufp, msgbufsize);
1811 fpuinit();
1812
1813 /*
1814 * Set up thread0 pcb after fpuinit calculated pcb + fpu save
1815 * area size. Zero out the extended state header in fpu save
1816 * area.
1817 */
1818 thread0.td_pcb = get_pcb_td(&thread0);
1819 bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size);
1820 if (use_xsave) {
1821 xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) +
1822 1);
1823 xhdr->xstate_bv = xsave_mask;
1824 }
1825 /* make an initial tss so cpu can get interrupt stack on syscall! */
1826 common_tss[0].tss_rsp0 = (vm_offset_t)thread0.td_pcb;
1827 /* Ensure the stack is aligned to 16 bytes */
1828 common_tss[0].tss_rsp0 &= ~0xFul;
1829 PCPU_SET(rsp0, common_tss[0].tss_rsp0);
1830 PCPU_SET(curpcb, thread0.td_pcb);
1831
1832 /* transfer to user mode */
1833
1834 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
1835 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
1836 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
1837 _ufssel = GSEL(GUFS32_SEL, SEL_UPL);
1838 _ugssel = GSEL(GUGS32_SEL, SEL_UPL);
1839
1840 load_ds(_udatasel);
1841 load_es(_udatasel);
1842 load_fs(_ufssel);
1843
1844 /* setup proc 0's pcb */
1845 thread0.td_pcb->pcb_flags = 0;
1846 thread0.td_pcb->pcb_cr3 = KPML4phys;
1847 thread0.td_frame = &proc0_tf;
1848
1849 env = getenv("kernelname");
1850 if (env != NULL)
1851 strlcpy(kernelname, env, sizeof(kernelname));
1852
1853 #ifdef XENHVM
1854 if (inw(0x10) == 0x49d2) {
1855 if (bootverbose)
1856 printf("Xen detected: disabling emulated block and network devices\n");
1857 outw(0x10, 3);
1858 }
1859 #endif
1860
1861 cpu_probe_amdc1e();
1862
1863 /* Location of kernel stack for locore */
1864 return ((u_int64_t)thread0.td_pcb);
1865 }
1866
1867 void
1868 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size)
1869 {
1870
1871 pcpu->pc_acpi_id = 0xffffffff;
1872 }
1873
1874 void
1875 spinlock_enter(void)
1876 {
1877 struct thread *td;
1878 register_t flags;
1879
1880 td = curthread;
1881 if (td->td_md.md_spinlock_count == 0) {
1882 flags = intr_disable();
1883 td->td_md.md_spinlock_count = 1;
1884 td->td_md.md_saved_flags = flags;
1885 } else
1886 td->td_md.md_spinlock_count++;
1887 critical_enter();
1888 }
1889
1890 void
1891 spinlock_exit(void)
1892 {
1893 struct thread *td;
1894 register_t flags;
1895
1896 td = curthread;
1897 critical_exit();
1898 flags = td->td_md.md_saved_flags;
1899 td->td_md.md_spinlock_count--;
1900 if (td->td_md.md_spinlock_count == 0)
1901 intr_restore(flags);
1902 }
1903
1904 /*
1905 * Construct a PCB from a trapframe. This is called from kdb_trap() where
1906 * we want to start a backtrace from the function that caused us to enter
1907 * the debugger. We have the context in the trapframe, but base the trace
1908 * on the PCB. The PCB doesn't have to be perfect, as long as it contains
1909 * enough for a backtrace.
1910 */
1911 void
1912 makectx(struct trapframe *tf, struct pcb *pcb)
1913 {
1914
1915 pcb->pcb_r12 = tf->tf_r12;
1916 pcb->pcb_r13 = tf->tf_r13;
1917 pcb->pcb_r14 = tf->tf_r14;
1918 pcb->pcb_r15 = tf->tf_r15;
1919 pcb->pcb_rbp = tf->tf_rbp;
1920 pcb->pcb_rbx = tf->tf_rbx;
1921 pcb->pcb_rip = tf->tf_rip;
1922 pcb->pcb_rsp = tf->tf_rsp;
1923 }
1924
1925 int
1926 ptrace_set_pc(struct thread *td, unsigned long addr)
1927 {
1928 td->td_frame->tf_rip = addr;
1929 return (0);
1930 }
1931
1932 int
1933 ptrace_single_step(struct thread *td)
1934 {
1935 td->td_frame->tf_rflags |= PSL_T;
1936 return (0);
1937 }
1938
1939 int
1940 ptrace_clear_single_step(struct thread *td)
1941 {
1942 td->td_frame->tf_rflags &= ~PSL_T;
1943 return (0);
1944 }
1945
1946 int
1947 fill_regs(struct thread *td, struct reg *regs)
1948 {
1949 struct trapframe *tp;
1950
1951 tp = td->td_frame;
1952 return (fill_frame_regs(tp, regs));
1953 }
1954
1955 int
1956 fill_frame_regs(struct trapframe *tp, struct reg *regs)
1957 {
1958 regs->r_r15 = tp->tf_r15;
1959 regs->r_r14 = tp->tf_r14;
1960 regs->r_r13 = tp->tf_r13;
1961 regs->r_r12 = tp->tf_r12;
1962 regs->r_r11 = tp->tf_r11;
1963 regs->r_r10 = tp->tf_r10;
1964 regs->r_r9 = tp->tf_r9;
1965 regs->r_r8 = tp->tf_r8;
1966 regs->r_rdi = tp->tf_rdi;
1967 regs->r_rsi = tp->tf_rsi;
1968 regs->r_rbp = tp->tf_rbp;
1969 regs->r_rbx = tp->tf_rbx;
1970 regs->r_rdx = tp->tf_rdx;
1971 regs->r_rcx = tp->tf_rcx;
1972 regs->r_rax = tp->tf_rax;
1973 regs->r_rip = tp->tf_rip;
1974 regs->r_cs = tp->tf_cs;
1975 regs->r_rflags = tp->tf_rflags;
1976 regs->r_rsp = tp->tf_rsp;
1977 regs->r_ss = tp->tf_ss;
1978 if (tp->tf_flags & TF_HASSEGS) {
1979 regs->r_ds = tp->tf_ds;
1980 regs->r_es = tp->tf_es;
1981 regs->r_fs = tp->tf_fs;
1982 regs->r_gs = tp->tf_gs;
1983 } else {
1984 regs->r_ds = 0;
1985 regs->r_es = 0;
1986 regs->r_fs = 0;
1987 regs->r_gs = 0;
1988 }
1989 return (0);
1990 }
1991
1992 int
1993 set_regs(struct thread *td, struct reg *regs)
1994 {
1995 struct trapframe *tp;
1996 register_t rflags;
1997
1998 tp = td->td_frame;
1999 rflags = regs->r_rflags & 0xffffffff;
2000 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs))
2001 return (EINVAL);
2002 tp->tf_r15 = regs->r_r15;
2003 tp->tf_r14 = regs->r_r14;
2004 tp->tf_r13 = regs->r_r13;
2005 tp->tf_r12 = regs->r_r12;
2006 tp->tf_r11 = regs->r_r11;
2007 tp->tf_r10 = regs->r_r10;
2008 tp->tf_r9 = regs->r_r9;
2009 tp->tf_r8 = regs->r_r8;
2010 tp->tf_rdi = regs->r_rdi;
2011 tp->tf_rsi = regs->r_rsi;
2012 tp->tf_rbp = regs->r_rbp;
2013 tp->tf_rbx = regs->r_rbx;
2014 tp->tf_rdx = regs->r_rdx;
2015 tp->tf_rcx = regs->r_rcx;
2016 tp->tf_rax = regs->r_rax;
2017 tp->tf_rip = regs->r_rip;
2018 tp->tf_cs = regs->r_cs;
2019 tp->tf_rflags = rflags;
2020 tp->tf_rsp = regs->r_rsp;
2021 tp->tf_ss = regs->r_ss;
2022 if (0) { /* XXXKIB */
2023 tp->tf_ds = regs->r_ds;
2024 tp->tf_es = regs->r_es;
2025 tp->tf_fs = regs->r_fs;
2026 tp->tf_gs = regs->r_gs;
2027 tp->tf_flags = TF_HASSEGS;
2028 set_pcb_flags(td->td_pcb, PCB_FULL_IRET);
2029 }
2030 return (0);
2031 }
2032
2033 /* XXX check all this stuff! */
2034 /* externalize from sv_xmm */
2035 static void
2036 fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs)
2037 {
2038 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env;
2039 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2040 int i;
2041
2042 /* pcb -> fpregs */
2043 bzero(fpregs, sizeof(*fpregs));
2044
2045 /* FPU control/status */
2046 penv_fpreg->en_cw = penv_xmm->en_cw;
2047 penv_fpreg->en_sw = penv_xmm->en_sw;
2048 penv_fpreg->en_tw = penv_xmm->en_tw;
2049 penv_fpreg->en_opcode = penv_xmm->en_opcode;
2050 penv_fpreg->en_rip = penv_xmm->en_rip;
2051 penv_fpreg->en_rdp = penv_xmm->en_rdp;
2052 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr;
2053 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask;
2054
2055 /* FPU registers */
2056 for (i = 0; i < 8; ++i)
2057 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10);
2058
2059 /* SSE registers */
2060 for (i = 0; i < 16; ++i)
2061 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16);
2062 }
2063
2064 /* internalize from fpregs into sv_xmm */
2065 static void
2066 set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm)
2067 {
2068 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2069 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env;
2070 int i;
2071
2072 /* fpregs -> pcb */
2073 /* FPU control/status */
2074 penv_xmm->en_cw = penv_fpreg->en_cw;
2075 penv_xmm->en_sw = penv_fpreg->en_sw;
2076 penv_xmm->en_tw = penv_fpreg->en_tw;
2077 penv_xmm->en_opcode = penv_fpreg->en_opcode;
2078 penv_xmm->en_rip = penv_fpreg->en_rip;
2079 penv_xmm->en_rdp = penv_fpreg->en_rdp;
2080 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr;
2081 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask;
2082
2083 /* FPU registers */
2084 for (i = 0; i < 8; ++i)
2085 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10);
2086
2087 /* SSE registers */
2088 for (i = 0; i < 16; ++i)
2089 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16);
2090 }
2091
2092 /* externalize from td->pcb */
2093 int
2094 fill_fpregs(struct thread *td, struct fpreg *fpregs)
2095 {
2096
2097 KASSERT(td == curthread || TD_IS_SUSPENDED(td) ||
2098 P_SHOULDSTOP(td->td_proc),
2099 ("not suspended thread %p", td));
2100 fpugetregs(td);
2101 fill_fpregs_xmm(get_pcb_user_save_td(td), fpregs);
2102 return (0);
2103 }
2104
2105 /* internalize to td->pcb */
2106 int
2107 set_fpregs(struct thread *td, struct fpreg *fpregs)
2108 {
2109
2110 set_fpregs_xmm(fpregs, get_pcb_user_save_td(td));
2111 fpuuserinited(td);
2112 return (0);
2113 }
2114
2115 /*
2116 * Get machine context.
2117 */
2118 int
2119 get_mcontext(struct thread *td, mcontext_t *mcp, int flags)
2120 {
2121 struct pcb *pcb;
2122 struct trapframe *tp;
2123
2124 pcb = td->td_pcb;
2125 tp = td->td_frame;
2126 PROC_LOCK(curthread->td_proc);
2127 mcp->mc_onstack = sigonstack(tp->tf_rsp);
2128 PROC_UNLOCK(curthread->td_proc);
2129 mcp->mc_r15 = tp->tf_r15;
2130 mcp->mc_r14 = tp->tf_r14;
2131 mcp->mc_r13 = tp->tf_r13;
2132 mcp->mc_r12 = tp->tf_r12;
2133 mcp->mc_r11 = tp->tf_r11;
2134 mcp->mc_r10 = tp->tf_r10;
2135 mcp->mc_r9 = tp->tf_r9;
2136 mcp->mc_r8 = tp->tf_r8;
2137 mcp->mc_rdi = tp->tf_rdi;
2138 mcp->mc_rsi = tp->tf_rsi;
2139 mcp->mc_rbp = tp->tf_rbp;
2140 mcp->mc_rbx = tp->tf_rbx;
2141 mcp->mc_rcx = tp->tf_rcx;
2142 mcp->mc_rflags = tp->tf_rflags;
2143 if (flags & GET_MC_CLEAR_RET) {
2144 mcp->mc_rax = 0;
2145 mcp->mc_rdx = 0;
2146 mcp->mc_rflags &= ~PSL_C;
2147 } else {
2148 mcp->mc_rax = tp->tf_rax;
2149 mcp->mc_rdx = tp->tf_rdx;
2150 }
2151 mcp->mc_rip = tp->tf_rip;
2152 mcp->mc_cs = tp->tf_cs;
2153 mcp->mc_rsp = tp->tf_rsp;
2154 mcp->mc_ss = tp->tf_ss;
2155 mcp->mc_ds = tp->tf_ds;
2156 mcp->mc_es = tp->tf_es;
2157 mcp->mc_fs = tp->tf_fs;
2158 mcp->mc_gs = tp->tf_gs;
2159 mcp->mc_flags = tp->tf_flags;
2160 mcp->mc_len = sizeof(*mcp);
2161 get_fpcontext(td, mcp, NULL, 0);
2162 mcp->mc_fsbase = pcb->pcb_fsbase;
2163 mcp->mc_gsbase = pcb->pcb_gsbase;
2164 mcp->mc_xfpustate = 0;
2165 mcp->mc_xfpustate_len = 0;
2166 bzero(mcp->mc_spare, sizeof(mcp->mc_spare));
2167 return (0);
2168 }
2169
2170 /*
2171 * Set machine context.
2172 *
2173 * However, we don't set any but the user modifiable flags, and we won't
2174 * touch the cs selector.
2175 */
2176 int
2177 set_mcontext(struct thread *td, const mcontext_t *mcp)
2178 {
2179 struct pcb *pcb;
2180 struct trapframe *tp;
2181 char *xfpustate;
2182 long rflags;
2183 int ret;
2184
2185 pcb = td->td_pcb;
2186 tp = td->td_frame;
2187 if (mcp->mc_len != sizeof(*mcp) ||
2188 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0)
2189 return (EINVAL);
2190 rflags = (mcp->mc_rflags & PSL_USERCHANGE) |
2191 (tp->tf_rflags & ~PSL_USERCHANGE);
2192 if (mcp->mc_flags & _MC_HASFPXSTATE) {
2193 if (mcp->mc_xfpustate_len > cpu_max_ext_state_size -
2194 sizeof(struct savefpu))
2195 return (EINVAL);
2196 xfpustate = __builtin_alloca(mcp->mc_xfpustate_len);
2197 ret = copyin((void *)mcp->mc_xfpustate, xfpustate,
2198 mcp->mc_xfpustate_len);
2199 if (ret != 0)
2200 return (ret);
2201 } else
2202 xfpustate = NULL;
2203 ret = set_fpcontext(td, mcp, xfpustate, mcp->mc_xfpustate_len);
2204 if (ret != 0)
2205 return (ret);
2206 tp->tf_r15 = mcp->mc_r15;
2207 tp->tf_r14 = mcp->mc_r14;
2208 tp->tf_r13 = mcp->mc_r13;
2209 tp->tf_r12 = mcp->mc_r12;
2210 tp->tf_r11 = mcp->mc_r11;
2211 tp->tf_r10 = mcp->mc_r10;
2212 tp->tf_r9 = mcp->mc_r9;
2213 tp->tf_r8 = mcp->mc_r8;
2214 tp->tf_rdi = mcp->mc_rdi;
2215 tp->tf_rsi = mcp->mc_rsi;
2216 tp->tf_rbp = mcp->mc_rbp;
2217 tp->tf_rbx = mcp->mc_rbx;
2218 tp->tf_rdx = mcp->mc_rdx;
2219 tp->tf_rcx = mcp->mc_rcx;
2220 tp->tf_rax = mcp->mc_rax;
2221 tp->tf_rip = mcp->mc_rip;
2222 tp->tf_rflags = rflags;
2223 tp->tf_rsp = mcp->mc_rsp;
2224 tp->tf_ss = mcp->mc_ss;
2225 tp->tf_flags = mcp->mc_flags;
2226 if (tp->tf_flags & TF_HASSEGS) {
2227 tp->tf_ds = mcp->mc_ds;
2228 tp->tf_es = mcp->mc_es;
2229 tp->tf_fs = mcp->mc_fs;
2230 tp->tf_gs = mcp->mc_gs;
2231 }
2232 if (mcp->mc_flags & _MC_HASBASES) {
2233 pcb->pcb_fsbase = mcp->mc_fsbase;
2234 pcb->pcb_gsbase = mcp->mc_gsbase;
2235 }
2236 set_pcb_flags(pcb, PCB_FULL_IRET);
2237 return (0);
2238 }
2239
2240 static void
2241 get_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpusave,
2242 size_t xfpusave_len)
2243 {
2244 size_t max_len, len;
2245
2246 mcp->mc_ownedfp = fpugetregs(td);
2247 bcopy(get_pcb_user_save_td(td), &mcp->mc_fpstate[0],
2248 sizeof(mcp->mc_fpstate));
2249 mcp->mc_fpformat = fpuformat();
2250 if (!use_xsave || xfpusave_len == 0)
2251 return;
2252 max_len = cpu_max_ext_state_size - sizeof(struct savefpu);
2253 len = xfpusave_len;
2254 if (len > max_len) {
2255 len = max_len;
2256 bzero(xfpusave + max_len, len - max_len);
2257 }
2258 mcp->mc_flags |= _MC_HASFPXSTATE;
2259 mcp->mc_xfpustate_len = len;
2260 bcopy(get_pcb_user_save_td(td) + 1, xfpusave, len);
2261 }
2262
2263 static int
2264 set_fpcontext(struct thread *td, const mcontext_t *mcp, char *xfpustate,
2265 size_t xfpustate_len)
2266 {
2267 struct savefpu *fpstate;
2268 int error;
2269
2270 if (mcp->mc_fpformat == _MC_FPFMT_NODEV)
2271 return (0);
2272 else if (mcp->mc_fpformat != _MC_FPFMT_XMM)
2273 return (EINVAL);
2274 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) {
2275 /* We don't care what state is left in the FPU or PCB. */
2276 fpstate_drop(td);
2277 error = 0;
2278 } else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU ||
2279 mcp->mc_ownedfp == _MC_FPOWNED_PCB) {
2280 fpstate = (struct savefpu *)&mcp->mc_fpstate;
2281 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask;
2282 error = fpusetregs(td, fpstate, xfpustate, xfpustate_len);
2283 } else
2284 return (EINVAL);
2285 return (error);
2286 }
2287
2288 void
2289 fpstate_drop(struct thread *td)
2290 {
2291
2292 KASSERT(PCB_USER_FPU(td->td_pcb), ("fpstate_drop: kernel-owned fpu"));
2293 critical_enter();
2294 if (PCPU_GET(fpcurthread) == td)
2295 fpudrop();
2296 /*
2297 * XXX force a full drop of the fpu. The above only drops it if we
2298 * owned it.
2299 *
2300 * XXX I don't much like fpugetuserregs()'s semantics of doing a full
2301 * drop. Dropping only to the pcb matches fnsave's behaviour.
2302 * We only need to drop to !PCB_INITDONE in sendsig(). But
2303 * sendsig() is the only caller of fpugetuserregs()... perhaps we just
2304 * have too many layers.
2305 */
2306 clear_pcb_flags(curthread->td_pcb,
2307 PCB_FPUINITDONE | PCB_USERFPUINITDONE);
2308 critical_exit();
2309 }
2310
2311 int
2312 fill_dbregs(struct thread *td, struct dbreg *dbregs)
2313 {
2314 struct pcb *pcb;
2315
2316 if (td == NULL) {
2317 dbregs->dr[0] = rdr0();
2318 dbregs->dr[1] = rdr1();
2319 dbregs->dr[2] = rdr2();
2320 dbregs->dr[3] = rdr3();
2321 dbregs->dr[6] = rdr6();
2322 dbregs->dr[7] = rdr7();
2323 } else {
2324 pcb = td->td_pcb;
2325 dbregs->dr[0] = pcb->pcb_dr0;
2326 dbregs->dr[1] = pcb->pcb_dr1;
2327 dbregs->dr[2] = pcb->pcb_dr2;
2328 dbregs->dr[3] = pcb->pcb_dr3;
2329 dbregs->dr[6] = pcb->pcb_dr6;
2330 dbregs->dr[7] = pcb->pcb_dr7;
2331 }
2332 dbregs->dr[4] = 0;
2333 dbregs->dr[5] = 0;
2334 dbregs->dr[8] = 0;
2335 dbregs->dr[9] = 0;
2336 dbregs->dr[10] = 0;
2337 dbregs->dr[11] = 0;
2338 dbregs->dr[12] = 0;
2339 dbregs->dr[13] = 0;
2340 dbregs->dr[14] = 0;
2341 dbregs->dr[15] = 0;
2342 return (0);
2343 }
2344
2345 int
2346 set_dbregs(struct thread *td, struct dbreg *dbregs)
2347 {
2348 struct pcb *pcb;
2349 int i;
2350
2351 if (td == NULL) {
2352 load_dr0(dbregs->dr[0]);
2353 load_dr1(dbregs->dr[1]);
2354 load_dr2(dbregs->dr[2]);
2355 load_dr3(dbregs->dr[3]);
2356 load_dr6(dbregs->dr[6]);
2357 load_dr7(dbregs->dr[7]);
2358 } else {
2359 /*
2360 * Don't let an illegal value for dr7 get set. Specifically,
2361 * check for undefined settings. Setting these bit patterns
2362 * result in undefined behaviour and can lead to an unexpected
2363 * TRCTRAP or a general protection fault right here.
2364 * Upper bits of dr6 and dr7 must not be set
2365 */
2366 for (i = 0; i < 4; i++) {
2367 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02)
2368 return (EINVAL);
2369 if (td->td_frame->tf_cs == _ucode32sel &&
2370 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8)
2371 return (EINVAL);
2372 }
2373 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 ||
2374 (dbregs->dr[7] & 0xffffffff00000000ul) != 0)
2375 return (EINVAL);
2376
2377 pcb = td->td_pcb;
2378
2379 /*
2380 * Don't let a process set a breakpoint that is not within the
2381 * process's address space. If a process could do this, it
2382 * could halt the system by setting a breakpoint in the kernel
2383 * (if ddb was enabled). Thus, we need to check to make sure
2384 * that no breakpoints are being enabled for addresses outside
2385 * process's address space.
2386 *
2387 * XXX - what about when the watched area of the user's
2388 * address space is written into from within the kernel
2389 * ... wouldn't that still cause a breakpoint to be generated
2390 * from within kernel mode?
2391 */
2392
2393 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) {
2394 /* dr0 is enabled */
2395 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS)
2396 return (EINVAL);
2397 }
2398 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) {
2399 /* dr1 is enabled */
2400 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS)
2401 return (EINVAL);
2402 }
2403 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) {
2404 /* dr2 is enabled */
2405 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS)
2406 return (EINVAL);
2407 }
2408 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) {
2409 /* dr3 is enabled */
2410 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS)
2411 return (EINVAL);
2412 }
2413
2414 pcb->pcb_dr0 = dbregs->dr[0];
2415 pcb->pcb_dr1 = dbregs->dr[1];
2416 pcb->pcb_dr2 = dbregs->dr[2];
2417 pcb->pcb_dr3 = dbregs->dr[3];
2418 pcb->pcb_dr6 = dbregs->dr[6];
2419 pcb->pcb_dr7 = dbregs->dr[7];
2420
2421 set_pcb_flags(pcb, PCB_DBREGS);
2422 }
2423
2424 return (0);
2425 }
2426
2427 void
2428 reset_dbregs(void)
2429 {
2430
2431 load_dr7(0); /* Turn off the control bits first */
2432 load_dr0(0);
2433 load_dr1(0);
2434 load_dr2(0);
2435 load_dr3(0);
2436 load_dr6(0);
2437 }
2438
2439 /*
2440 * Return > 0 if a hardware breakpoint has been hit, and the
2441 * breakpoint was in user space. Return 0, otherwise.
2442 */
2443 int
2444 user_dbreg_trap(void)
2445 {
2446 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2447 u_int64_t bp; /* breakpoint bits extracted from dr6 */
2448 int nbp; /* number of breakpoints that triggered */
2449 caddr_t addr[4]; /* breakpoint addresses */
2450 int i;
2451
2452 dr7 = rdr7();
2453 if ((dr7 & 0x000000ff) == 0) {
2454 /*
2455 * all GE and LE bits in the dr7 register are zero,
2456 * thus the trap couldn't have been caused by the
2457 * hardware debug registers
2458 */
2459 return 0;
2460 }
2461
2462 nbp = 0;
2463 dr6 = rdr6();
2464 bp = dr6 & 0x0000000f;
2465
2466 if (!bp) {
2467 /*
2468 * None of the breakpoint bits are set meaning this
2469 * trap was not caused by any of the debug registers
2470 */
2471 return 0;
2472 }
2473
2474 /*
2475 * at least one of the breakpoints were hit, check to see
2476 * which ones and if any of them are user space addresses
2477 */
2478
2479 if (bp & 0x01) {
2480 addr[nbp++] = (caddr_t)rdr0();
2481 }
2482 if (bp & 0x02) {
2483 addr[nbp++] = (caddr_t)rdr1();
2484 }
2485 if (bp & 0x04) {
2486 addr[nbp++] = (caddr_t)rdr2();
2487 }
2488 if (bp & 0x08) {
2489 addr[nbp++] = (caddr_t)rdr3();
2490 }
2491
2492 for (i = 0; i < nbp; i++) {
2493 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) {
2494 /*
2495 * addr[i] is in user space
2496 */
2497 return nbp;
2498 }
2499 }
2500
2501 /*
2502 * None of the breakpoints are in user space.
2503 */
2504 return 0;
2505 }
2506
2507 #ifdef KDB
2508
2509 /*
2510 * Provide inb() and outb() as functions. They are normally only available as
2511 * inline functions, thus cannot be called from the debugger.
2512 */
2513
2514 /* silence compiler warnings */
2515 u_char inb_(u_short);
2516 void outb_(u_short, u_char);
2517
2518 u_char
2519 inb_(u_short port)
2520 {
2521 return inb(port);
2522 }
2523
2524 void
2525 outb_(u_short port, u_char data)
2526 {
2527 outb(port, data);
2528 }
2529
2530 #endif /* KDB */
Cache object: e975051d6a5c36ab2ac68284e1206ea5
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