Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/amd64/amd64/machdep.c
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1 /*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1992 Terrence R. Lambert. 4 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include "opt_atalk.h" 45 #include "opt_atpic.h" 46 #include "opt_compat.h" 47 #include "opt_cpu.h" 48 #include "opt_ddb.h" 49 #include "opt_inet.h" 50 #include "opt_ipx.h" 51 #include "opt_isa.h" 52 #include "opt_kstack_pages.h" 53 #include "opt_maxmem.h" 54 #include "opt_mp_watchdog.h" 55 #include "opt_perfmon.h" 56 #include "opt_sched.h" 57 #include "opt_kdtrace.h" 58 59 #include <sys/param.h> 60 #include <sys/proc.h> 61 #include <sys/systm.h> 62 #include <sys/bio.h> 63 #include <sys/buf.h> 64 #include <sys/bus.h> 65 #include <sys/callout.h> 66 #include <sys/cons.h> 67 #include <sys/cpu.h> 68 #include <sys/eventhandler.h> 69 #include <sys/exec.h> 70 #include <sys/imgact.h> 71 #include <sys/kdb.h> 72 #include <sys/kernel.h> 73 #include <sys/ktr.h> 74 #include <sys/linker.h> 75 #include <sys/lock.h> 76 #include <sys/malloc.h> 77 #include <sys/memrange.h> 78 #include <sys/msgbuf.h> 79 #include <sys/mutex.h> 80 #include <sys/pcpu.h> 81 #include <sys/ptrace.h> 82 #include <sys/reboot.h> 83 #include <sys/sched.h> 84 #include <sys/signalvar.h> 85 #ifdef SMP 86 #include <sys/smp.h> 87 #endif 88 #include <sys/syscallsubr.h> 89 #include <sys/sysctl.h> 90 #include <sys/sysent.h> 91 #include <sys/sysproto.h> 92 #include <sys/ucontext.h> 93 #include <sys/vmmeter.h> 94 95 #include <vm/vm.h> 96 #include <vm/vm_extern.h> 97 #include <vm/vm_kern.h> 98 #include <vm/vm_page.h> 99 #include <vm/vm_map.h> 100 #include <vm/vm_object.h> 101 #include <vm/vm_pager.h> 102 #include <vm/vm_param.h> 103 104 #ifdef DDB 105 #ifndef KDB 106 #error KDB must be enabled in order for DDB to work! 107 #endif 108 #include <ddb/ddb.h> 109 #include <ddb/db_sym.h> 110 #endif 111 112 #include <net/netisr.h> 113 114 #include <machine/clock.h> 115 #include <machine/cpu.h> 116 #include <machine/cputypes.h> 117 #include <machine/intr_machdep.h> 118 #include <x86/mca.h> 119 #include <machine/md_var.h> 120 #include <machine/metadata.h> 121 #include <machine/mp_watchdog.h> 122 #include <machine/pc/bios.h> 123 #include <machine/pcb.h> 124 #include <machine/proc.h> 125 #include <machine/reg.h> 126 #include <machine/sigframe.h> 127 #include <machine/specialreg.h> 128 #ifdef PERFMON 129 #include <machine/perfmon.h> 130 #endif 131 #include <machine/tss.h> 132 #ifdef SMP 133 #include <machine/smp.h> 134 #endif 135 136 #ifdef DEV_ATPIC 137 #include <x86/isa/icu.h> 138 #else 139 #include <machine/apicvar.h> 140 #endif 141 142 #include <isa/isareg.h> 143 #include <isa/rtc.h> 144 145 /* Sanity check for __curthread() */ 146 CTASSERT(offsetof(struct pcpu, pc_curthread) == 0); 147 148 extern u_int64_t hammer_time(u_int64_t, u_int64_t); 149 150 extern void printcpuinfo(void); /* XXX header file */ 151 extern void identify_cpu(void); 152 extern void panicifcpuunsupported(void); 153 154 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL) 155 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0) 156 157 static void cpu_startup(void *); 158 static void get_fpcontext(struct thread *td, mcontext_t *mcp, 159 char *xfpusave, size_t xfpusave_len); 160 static int set_fpcontext(struct thread *td, const mcontext_t *mcp, 161 char *xfpustate, size_t xfpustate_len); 162 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL); 163 164 /* 165 * The file "conf/ldscript.amd64" defines the symbol "kernphys". Its value is 166 * the physical address at which the kernel is loaded. 167 */ 168 extern char kernphys[]; 169 #ifdef DDB 170 extern vm_offset_t ksym_start, ksym_end; 171 #endif 172 173 struct msgbuf *msgbufp; 174 175 /* Intel ICH registers */ 176 #define ICH_PMBASE 0x400 177 #define ICH_SMI_EN ICH_PMBASE + 0x30 178 179 int _udatasel, _ucodesel, _ucode32sel, _ufssel, _ugssel; 180 181 int cold = 1; 182 183 long Maxmem = 0; 184 long realmem = 0; 185 186 /* 187 * The number of PHYSMAP entries must be one less than the number of 188 * PHYSSEG entries because the PHYSMAP entry that spans the largest 189 * physical address that is accessible by ISA DMA is split into two 190 * PHYSSEG entries. 191 */ 192 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1)) 193 194 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2]; 195 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2]; 196 197 /* must be 2 less so 0 0 can signal end of chunks */ 198 #define PHYS_AVAIL_ARRAY_END ((sizeof(phys_avail) / sizeof(phys_avail[0])) - 2) 199 #define DUMP_AVAIL_ARRAY_END ((sizeof(dump_avail) / sizeof(dump_avail[0])) - 2) 200 201 struct kva_md_info kmi; 202 203 static struct trapframe proc0_tf; 204 struct region_descriptor r_gdt, r_idt; 205 206 struct pcpu __pcpu[MAXCPU]; 207 208 struct mtx icu_lock; 209 210 struct mem_range_softc mem_range_softc; 211 212 struct mtx dt_lock; /* lock for GDT and LDT */ 213 214 static void 215 cpu_startup(dummy) 216 void *dummy; 217 { 218 uintmax_t memsize; 219 char *sysenv; 220 221 /* 222 * On MacBooks, we need to disallow the legacy USB circuit to 223 * generate an SMI# because this can cause several problems, 224 * namely: incorrect CPU frequency detection and failure to 225 * start the APs. 226 * We do this by disabling a bit in the SMI_EN (SMI Control and 227 * Enable register) of the Intel ICH LPC Interface Bridge. 228 */ 229 sysenv = getenv("smbios.system.product"); 230 if (sysenv != NULL) { 231 if (strncmp(sysenv, "MacBook1,1", 10) == 0 || 232 strncmp(sysenv, "MacBook3,1", 10) == 0 || 233 strncmp(sysenv, "MacBook4,1", 10) == 0 || 234 strncmp(sysenv, "MacBookPro1,1", 13) == 0 || 235 strncmp(sysenv, "MacBookPro1,2", 13) == 0 || 236 strncmp(sysenv, "MacBookPro3,1", 13) == 0 || 237 strncmp(sysenv, "MacBookPro4,1", 13) == 0 || 238 strncmp(sysenv, "Macmini1,1", 10) == 0) { 239 if (bootverbose) 240 printf("Disabling LEGACY_USB_EN bit on " 241 "Intel ICH.\n"); 242 outl(ICH_SMI_EN, inl(ICH_SMI_EN) & ~0x8); 243 } 244 freeenv(sysenv); 245 } 246 247 /* 248 * Good {morning,afternoon,evening,night}. 249 */ 250 startrtclock(); 251 printcpuinfo(); 252 panicifcpuunsupported(); 253 #ifdef PERFMON 254 perfmon_init(); 255 #endif 256 realmem = Maxmem; 257 258 /* 259 * Display physical memory if SMBIOS reports reasonable amount. 260 */ 261 memsize = 0; 262 sysenv = getenv("smbios.memory.enabled"); 263 if (sysenv != NULL) { 264 memsize = (uintmax_t)strtoul(sysenv, (char **)NULL, 10) << 10; 265 freeenv(sysenv); 266 } 267 if (memsize < ptoa((uintmax_t)cnt.v_free_count)) 268 memsize = ptoa((uintmax_t)Maxmem); 269 printf("real memory = %ju (%ju MB)\n", memsize, memsize >> 20); 270 271 /* 272 * Display any holes after the first chunk of extended memory. 273 */ 274 if (bootverbose) { 275 int indx; 276 277 printf("Physical memory chunk(s):\n"); 278 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) { 279 vm_paddr_t size; 280 281 size = phys_avail[indx + 1] - phys_avail[indx]; 282 printf( 283 "0x%016jx - 0x%016jx, %ju bytes (%ju pages)\n", 284 (uintmax_t)phys_avail[indx], 285 (uintmax_t)phys_avail[indx + 1] - 1, 286 (uintmax_t)size, (uintmax_t)size / PAGE_SIZE); 287 } 288 } 289 290 vm_ksubmap_init(&kmi); 291 292 printf("avail memory = %ju (%ju MB)\n", 293 ptoa((uintmax_t)cnt.v_free_count), 294 ptoa((uintmax_t)cnt.v_free_count) / 1048576); 295 296 /* 297 * Set up buffers, so they can be used to read disk labels. 298 */ 299 bufinit(); 300 vm_pager_bufferinit(); 301 302 cpu_setregs(); 303 304 /* 305 * Add BSP as an interrupt target. 306 */ 307 intr_add_cpu(0); 308 } 309 310 /* 311 * Send an interrupt to process. 312 * 313 * Stack is set up to allow sigcode stored 314 * at top to call routine, followed by call 315 * to sigreturn routine below. After sigreturn 316 * resets the signal mask, the stack, and the 317 * frame pointer, it returns to the user 318 * specified pc, psl. 319 */ 320 void 321 sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask) 322 { 323 struct sigframe sf, *sfp; 324 struct pcb *pcb; 325 struct proc *p; 326 struct thread *td; 327 struct sigacts *psp; 328 char *sp; 329 struct trapframe *regs; 330 char *xfpusave; 331 size_t xfpusave_len; 332 int sig; 333 int oonstack; 334 335 td = curthread; 336 pcb = td->td_pcb; 337 p = td->td_proc; 338 PROC_LOCK_ASSERT(p, MA_OWNED); 339 sig = ksi->ksi_signo; 340 psp = p->p_sigacts; 341 mtx_assert(&psp->ps_mtx, MA_OWNED); 342 regs = td->td_frame; 343 oonstack = sigonstack(regs->tf_rsp); 344 345 if (cpu_max_ext_state_size > sizeof(struct savefpu) && use_xsave) { 346 xfpusave_len = cpu_max_ext_state_size - sizeof(struct savefpu); 347 xfpusave = __builtin_alloca(xfpusave_len); 348 } else { 349 xfpusave_len = 0; 350 xfpusave = NULL; 351 } 352 353 /* Save user context. */ 354 bzero(&sf, sizeof(sf)); 355 sf.sf_uc.uc_sigmask = *mask; 356 sf.sf_uc.uc_stack = td->td_sigstk; 357 sf.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) 358 ? ((oonstack) ? SS_ONSTACK : 0) : SS_DISABLE; 359 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0; 360 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(*regs)); 361 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext); /* magic */ 362 get_fpcontext(td, &sf.sf_uc.uc_mcontext, xfpusave, xfpusave_len); 363 fpstate_drop(td); 364 sf.sf_uc.uc_mcontext.mc_fsbase = pcb->pcb_fsbase; 365 sf.sf_uc.uc_mcontext.mc_gsbase = pcb->pcb_gsbase; 366 bzero(sf.sf_uc.uc_mcontext.mc_spare, 367 sizeof(sf.sf_uc.uc_mcontext.mc_spare)); 368 bzero(sf.sf_uc.__spare__, sizeof(sf.sf_uc.__spare__)); 369 370 /* Allocate space for the signal handler context. */ 371 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack && 372 SIGISMEMBER(psp->ps_sigonstack, sig)) { 373 sp = td->td_sigstk.ss_sp + td->td_sigstk.ss_size; 374 #if defined(COMPAT_43) 375 td->td_sigstk.ss_flags |= SS_ONSTACK; 376 #endif 377 } else 378 sp = (char *)regs->tf_rsp - 128; 379 if (xfpusave != NULL) { 380 sp -= xfpusave_len; 381 sp = (char *)((unsigned long)sp & ~0x3Ful); 382 sf.sf_uc.uc_mcontext.mc_xfpustate = (register_t)sp; 383 } 384 sp -= sizeof(struct sigframe); 385 /* Align to 16 bytes. */ 386 sfp = (struct sigframe *)((unsigned long)sp & ~0xFul); 387 388 /* Translate the signal if appropriate. */ 389 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize) 390 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)]; 391 392 /* Build the argument list for the signal handler. */ 393 regs->tf_rdi = sig; /* arg 1 in %rdi */ 394 regs->tf_rdx = (register_t)&sfp->sf_uc; /* arg 3 in %rdx */ 395 bzero(&sf.sf_si, sizeof(sf.sf_si)); 396 if (SIGISMEMBER(psp->ps_siginfo, sig)) { 397 /* Signal handler installed with SA_SIGINFO. */ 398 regs->tf_rsi = (register_t)&sfp->sf_si; /* arg 2 in %rsi */ 399 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; 400 401 /* Fill in POSIX parts */ 402 sf.sf_si = ksi->ksi_info; 403 sf.sf_si.si_signo = sig; /* maybe a translated signal */ 404 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 405 } else { 406 /* Old FreeBSD-style arguments. */ 407 regs->tf_rsi = ksi->ksi_code; /* arg 2 in %rsi */ 408 regs->tf_rcx = (register_t)ksi->ksi_addr; /* arg 4 in %rcx */ 409 sf.sf_ahu.sf_handler = catcher; 410 } 411 mtx_unlock(&psp->ps_mtx); 412 PROC_UNLOCK(p); 413 414 /* 415 * Copy the sigframe out to the user's stack. 416 */ 417 if (copyout(&sf, sfp, sizeof(*sfp)) != 0 || 418 (xfpusave != NULL && copyout(xfpusave, 419 (void *)sf.sf_uc.uc_mcontext.mc_xfpustate, xfpusave_len) 420 != 0)) { 421 #ifdef DEBUG 422 printf("process %ld has trashed its stack\n", (long)p->p_pid); 423 #endif 424 PROC_LOCK(p); 425 sigexit(td, SIGILL); 426 } 427 428 regs->tf_rsp = (long)sfp; 429 regs->tf_rip = p->p_sysent->sv_sigcode_base; 430 regs->tf_rflags &= ~(PSL_T | PSL_D); 431 regs->tf_cs = _ucodesel; 432 regs->tf_ds = _udatasel; 433 regs->tf_ss = _udatasel; 434 regs->tf_es = _udatasel; 435 regs->tf_fs = _ufssel; 436 regs->tf_gs = _ugssel; 437 regs->tf_flags = TF_HASSEGS; 438 set_pcb_flags(pcb, PCB_FULL_IRET); 439 PROC_LOCK(p); 440 mtx_lock(&psp->ps_mtx); 441 } 442 443 /* 444 * System call to cleanup state after a signal 445 * has been taken. Reset signal mask and 446 * stack state from context left by sendsig (above). 447 * Return to previous pc and psl as specified by 448 * context left by sendsig. Check carefully to 449 * make sure that the user has not modified the 450 * state to gain improper privileges. 451 * 452 * MPSAFE 453 */ 454 int 455 sys_sigreturn(td, uap) 456 struct thread *td; 457 struct sigreturn_args /* { 458 const struct __ucontext *sigcntxp; 459 } */ *uap; 460 { 461 ucontext_t uc; 462 struct pcb *pcb; 463 struct proc *p; 464 struct trapframe *regs; 465 ucontext_t *ucp; 466 char *xfpustate; 467 size_t xfpustate_len; 468 long rflags; 469 int cs, error, ret; 470 ksiginfo_t ksi; 471 472 pcb = td->td_pcb; 473 p = td->td_proc; 474 475 error = copyin(uap->sigcntxp, &uc, sizeof(uc)); 476 if (error != 0) { 477 uprintf("pid %d (%s): sigreturn copyin failed\n", 478 p->p_pid, td->td_name); 479 return (error); 480 } 481 ucp = &uc; 482 if ((ucp->uc_mcontext.mc_flags & ~_MC_FLAG_MASK) != 0) { 483 uprintf("pid %d (%s): sigreturn mc_flags %x\n", p->p_pid, 484 td->td_name, ucp->uc_mcontext.mc_flags); 485 return (EINVAL); 486 } 487 regs = td->td_frame; 488 rflags = ucp->uc_mcontext.mc_rflags; 489 /* 490 * Don't allow users to change privileged or reserved flags. 491 */ 492 if (!EFL_SECURE(rflags, regs->tf_rflags)) { 493 uprintf("pid %d (%s): sigreturn rflags = 0x%lx\n", p->p_pid, 494 td->td_name, rflags); 495 return (EINVAL); 496 } 497 498 /* 499 * Don't allow users to load a valid privileged %cs. Let the 500 * hardware check for invalid selectors, excess privilege in 501 * other selectors, invalid %eip's and invalid %esp's. 502 */ 503 cs = ucp->uc_mcontext.mc_cs; 504 if (!CS_SECURE(cs)) { 505 uprintf("pid %d (%s): sigreturn cs = 0x%x\n", p->p_pid, 506 td->td_name, cs); 507 ksiginfo_init_trap(&ksi); 508 ksi.ksi_signo = SIGBUS; 509 ksi.ksi_code = BUS_OBJERR; 510 ksi.ksi_trapno = T_PROTFLT; 511 ksi.ksi_addr = (void *)regs->tf_rip; 512 trapsignal(td, &ksi); 513 return (EINVAL); 514 } 515 516 if ((uc.uc_mcontext.mc_flags & _MC_HASFPXSTATE) != 0) { 517 xfpustate_len = uc.uc_mcontext.mc_xfpustate_len; 518 if (xfpustate_len > cpu_max_ext_state_size - 519 sizeof(struct savefpu)) { 520 uprintf("pid %d (%s): sigreturn xfpusave_len = 0x%zx\n", 521 p->p_pid, td->td_name, xfpustate_len); 522 return (EINVAL); 523 } 524 xfpustate = __builtin_alloca(xfpustate_len); 525 error = copyin((const void *)uc.uc_mcontext.mc_xfpustate, 526 xfpustate, xfpustate_len); 527 if (error != 0) { 528 uprintf( 529 "pid %d (%s): sigreturn copying xfpustate failed\n", 530 p->p_pid, td->td_name); 531 return (error); 532 } 533 } else { 534 xfpustate = NULL; 535 xfpustate_len = 0; 536 } 537 ret = set_fpcontext(td, &ucp->uc_mcontext, xfpustate, xfpustate_len); 538 if (ret != 0) { 539 uprintf("pid %d (%s): sigreturn set_fpcontext err %d\n", 540 p->p_pid, td->td_name, ret); 541 return (ret); 542 } 543 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(*regs)); 544 pcb->pcb_fsbase = ucp->uc_mcontext.mc_fsbase; 545 pcb->pcb_gsbase = ucp->uc_mcontext.mc_gsbase; 546 547 #if defined(COMPAT_43) 548 if (ucp->uc_mcontext.mc_onstack & 1) 549 td->td_sigstk.ss_flags |= SS_ONSTACK; 550 else 551 td->td_sigstk.ss_flags &= ~SS_ONSTACK; 552 #endif 553 554 kern_sigprocmask(td, SIG_SETMASK, &ucp->uc_sigmask, NULL, 0); 555 set_pcb_flags(pcb, PCB_FULL_IRET); 556 return (EJUSTRETURN); 557 } 558 559 #ifdef COMPAT_FREEBSD4 560 int 561 freebsd4_sigreturn(struct thread *td, struct freebsd4_sigreturn_args *uap) 562 { 563 564 return sys_sigreturn(td, (struct sigreturn_args *)uap); 565 } 566 #endif 567 568 569 /* 570 * Machine dependent boot() routine 571 * 572 * I haven't seen anything to put here yet 573 * Possibly some stuff might be grafted back here from boot() 574 */ 575 void 576 cpu_boot(int howto) 577 { 578 } 579 580 /* 581 * Flush the D-cache for non-DMA I/O so that the I-cache can 582 * be made coherent later. 583 */ 584 void 585 cpu_flush_dcache(void *ptr, size_t len) 586 { 587 /* Not applicable */ 588 } 589 590 /* Get current clock frequency for the given cpu id. */ 591 int 592 cpu_est_clockrate(int cpu_id, uint64_t *rate) 593 { 594 uint64_t tsc1, tsc2; 595 uint64_t acnt, mcnt, perf; 596 register_t reg; 597 598 if (pcpu_find(cpu_id) == NULL || rate == NULL) 599 return (EINVAL); 600 601 /* 602 * If TSC is P-state invariant and APERF/MPERF MSRs do not exist, 603 * DELAY(9) based logic fails. 604 */ 605 if (tsc_is_invariant && !tsc_perf_stat) 606 return (EOPNOTSUPP); 607 608 #ifdef SMP 609 if (smp_cpus > 1) { 610 /* Schedule ourselves on the indicated cpu. */ 611 thread_lock(curthread); 612 sched_bind(curthread, cpu_id); 613 thread_unlock(curthread); 614 } 615 #endif 616 617 /* Calibrate by measuring a short delay. */ 618 reg = intr_disable(); 619 if (tsc_is_invariant) { 620 wrmsr(MSR_MPERF, 0); 621 wrmsr(MSR_APERF, 0); 622 tsc1 = rdtsc(); 623 DELAY(1000); 624 mcnt = rdmsr(MSR_MPERF); 625 acnt = rdmsr(MSR_APERF); 626 tsc2 = rdtsc(); 627 intr_restore(reg); 628 perf = 1000 * acnt / mcnt; 629 *rate = (tsc2 - tsc1) * perf; 630 } else { 631 tsc1 = rdtsc(); 632 DELAY(1000); 633 tsc2 = rdtsc(); 634 intr_restore(reg); 635 *rate = (tsc2 - tsc1) * 1000; 636 } 637 638 #ifdef SMP 639 if (smp_cpus > 1) { 640 thread_lock(curthread); 641 sched_unbind(curthread); 642 thread_unlock(curthread); 643 } 644 #endif 645 646 return (0); 647 } 648 649 /* 650 * Shutdown the CPU as much as possible 651 */ 652 void 653 cpu_halt(void) 654 { 655 for (;;) 656 __asm__ ("hlt"); 657 } 658 659 void (*cpu_idle_hook)(void) = NULL; /* ACPI idle hook. */ 660 static int cpu_ident_amdc1e = 0; /* AMD C1E supported. */ 661 static int idle_mwait = 1; /* Use MONITOR/MWAIT for short idle. */ 662 TUNABLE_INT("machdep.idle_mwait", &idle_mwait); 663 SYSCTL_INT(_machdep, OID_AUTO, idle_mwait, CTLFLAG_RW, &idle_mwait, 664 0, "Use MONITOR/MWAIT for short idle"); 665 666 #define STATE_RUNNING 0x0 667 #define STATE_MWAIT 0x1 668 #define STATE_SLEEPING 0x2 669 670 static void 671 cpu_idle_acpi(int busy) 672 { 673 int *state; 674 675 state = (int *)PCPU_PTR(monitorbuf); 676 *state = STATE_SLEEPING; 677 disable_intr(); 678 if (sched_runnable()) 679 enable_intr(); 680 else if (cpu_idle_hook) 681 cpu_idle_hook(); 682 else 683 __asm __volatile("sti; hlt"); 684 *state = STATE_RUNNING; 685 } 686 687 static void 688 cpu_idle_hlt(int busy) 689 { 690 int *state; 691 692 state = (int *)PCPU_PTR(monitorbuf); 693 *state = STATE_SLEEPING; 694 /* 695 * We must absolutely guarentee that hlt is the next instruction 696 * after sti or we introduce a timing window. 697 */ 698 disable_intr(); 699 if (sched_runnable()) 700 enable_intr(); 701 else 702 __asm __volatile("sti; hlt"); 703 *state = STATE_RUNNING; 704 } 705 706 /* 707 * MWAIT cpu power states. Lower 4 bits are sub-states. 708 */ 709 #define MWAIT_C0 0xf0 710 #define MWAIT_C1 0x00 711 #define MWAIT_C2 0x10 712 #define MWAIT_C3 0x20 713 #define MWAIT_C4 0x30 714 715 static void 716 cpu_idle_mwait(int busy) 717 { 718 int *state; 719 720 state = (int *)PCPU_PTR(monitorbuf); 721 *state = STATE_MWAIT; 722 if (!sched_runnable()) { 723 cpu_monitor(state, 0, 0); 724 if (*state == STATE_MWAIT) 725 cpu_mwait(0, MWAIT_C1); 726 } 727 *state = STATE_RUNNING; 728 } 729 730 static void 731 cpu_idle_spin(int busy) 732 { 733 int *state; 734 int i; 735 736 state = (int *)PCPU_PTR(monitorbuf); 737 *state = STATE_RUNNING; 738 for (i = 0; i < 1000; i++) { 739 if (sched_runnable()) 740 return; 741 cpu_spinwait(); 742 } 743 } 744 745 /* 746 * C1E renders the local APIC timer dead, so we disable it by 747 * reading the Interrupt Pending Message register and clearing 748 * both C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 749 * 750 * Reference: 751 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" 752 * #32559 revision 3.00+ 753 */ 754 #define MSR_AMDK8_IPM 0xc0010055 755 #define AMDK8_SMIONCMPHALT (1ULL << 27) 756 #define AMDK8_C1EONCMPHALT (1ULL << 28) 757 #define AMDK8_CMPHALT (AMDK8_SMIONCMPHALT | AMDK8_C1EONCMPHALT) 758 759 static void 760 cpu_probe_amdc1e(void) 761 { 762 763 /* 764 * Detect the presence of C1E capability mostly on latest 765 * dual-cores (or future) k8 family. 766 */ 767 if (cpu_vendor_id == CPU_VENDOR_AMD && 768 (cpu_id & 0x00000f00) == 0x00000f00 && 769 (cpu_id & 0x0fff0000) >= 0x00040000) { 770 cpu_ident_amdc1e = 1; 771 } 772 } 773 774 void (*cpu_idle_fn)(int) = cpu_idle_acpi; 775 776 void 777 cpu_idle(int busy) 778 { 779 uint64_t msr; 780 781 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", 782 busy, curcpu); 783 #ifdef MP_WATCHDOG 784 ap_watchdog(PCPU_GET(cpuid)); 785 #endif 786 /* If we are busy - try to use fast methods. */ 787 if (busy) { 788 if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { 789 cpu_idle_mwait(busy); 790 goto out; 791 } 792 } 793 794 /* If we have time - switch timers into idle mode. */ 795 if (!busy) { 796 critical_enter(); 797 cpu_idleclock(); 798 } 799 800 /* Apply AMD APIC timer C1E workaround. */ 801 if (cpu_ident_amdc1e && cpu_disable_c3_sleep) { 802 msr = rdmsr(MSR_AMDK8_IPM); 803 if (msr & AMDK8_CMPHALT) 804 wrmsr(MSR_AMDK8_IPM, msr & ~AMDK8_CMPHALT); 805 } 806 807 /* Call main idle method. */ 808 cpu_idle_fn(busy); 809 810 /* Switch timers mack into active mode. */ 811 if (!busy) { 812 cpu_activeclock(); 813 critical_exit(); 814 } 815 out: 816 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", 817 busy, curcpu); 818 } 819 820 int 821 cpu_idle_wakeup(int cpu) 822 { 823 struct pcpu *pcpu; 824 int *state; 825 826 pcpu = pcpu_find(cpu); 827 state = (int *)pcpu->pc_monitorbuf; 828 /* 829 * This doesn't need to be atomic since missing the race will 830 * simply result in unnecessary IPIs. 831 */ 832 if (*state == STATE_SLEEPING) 833 return (0); 834 if (*state == STATE_MWAIT) 835 *state = STATE_RUNNING; 836 return (1); 837 } 838 839 /* 840 * Ordered by speed/power consumption. 841 */ 842 struct { 843 void *id_fn; 844 char *id_name; 845 } idle_tbl[] = { 846 { cpu_idle_spin, "spin" }, 847 { cpu_idle_mwait, "mwait" }, 848 { cpu_idle_hlt, "hlt" }, 849 { cpu_idle_acpi, "acpi" }, 850 { NULL, NULL } 851 }; 852 853 static int 854 idle_sysctl_available(SYSCTL_HANDLER_ARGS) 855 { 856 char *avail, *p; 857 int error; 858 int i; 859 860 avail = malloc(256, M_TEMP, M_WAITOK); 861 p = avail; 862 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 863 if (strstr(idle_tbl[i].id_name, "mwait") && 864 (cpu_feature2 & CPUID2_MON) == 0) 865 continue; 866 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 867 cpu_idle_hook == NULL) 868 continue; 869 p += sprintf(p, "%s%s", p != avail ? ", " : "", 870 idle_tbl[i].id_name); 871 } 872 error = sysctl_handle_string(oidp, avail, 0, req); 873 free(avail, M_TEMP); 874 return (error); 875 } 876 877 SYSCTL_PROC(_machdep, OID_AUTO, idle_available, CTLTYPE_STRING | CTLFLAG_RD, 878 0, 0, idle_sysctl_available, "A", "list of available idle functions"); 879 880 static int 881 idle_sysctl(SYSCTL_HANDLER_ARGS) 882 { 883 char buf[16]; 884 int error; 885 char *p; 886 int i; 887 888 p = "unknown"; 889 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 890 if (idle_tbl[i].id_fn == cpu_idle_fn) { 891 p = idle_tbl[i].id_name; 892 break; 893 } 894 } 895 strncpy(buf, p, sizeof(buf)); 896 error = sysctl_handle_string(oidp, buf, sizeof(buf), req); 897 if (error != 0 || req->newptr == NULL) 898 return (error); 899 for (i = 0; idle_tbl[i].id_name != NULL; i++) { 900 if (strstr(idle_tbl[i].id_name, "mwait") && 901 (cpu_feature2 & CPUID2_MON) == 0) 902 continue; 903 if (strcmp(idle_tbl[i].id_name, "acpi") == 0 && 904 cpu_idle_hook == NULL) 905 continue; 906 if (strcmp(idle_tbl[i].id_name, buf)) 907 continue; 908 cpu_idle_fn = idle_tbl[i].id_fn; 909 return (0); 910 } 911 return (EINVAL); 912 } 913 914 SYSCTL_PROC(_machdep, OID_AUTO, idle, CTLTYPE_STRING | CTLFLAG_RW, 0, 0, 915 idle_sysctl, "A", "currently selected idle function"); 916 917 /* 918 * Reset registers to default values on exec. 919 */ 920 void 921 exec_setregs(struct thread *td, struct image_params *imgp, u_long stack) 922 { 923 struct trapframe *regs = td->td_frame; 924 struct pcb *pcb = td->td_pcb; 925 926 mtx_lock(&dt_lock); 927 if (td->td_proc->p_md.md_ldt != NULL) 928 user_ldt_free(td); 929 else 930 mtx_unlock(&dt_lock); 931 932 pcb->pcb_fsbase = 0; 933 pcb->pcb_gsbase = 0; 934 clear_pcb_flags(pcb, PCB_32BIT); 935 pcb->pcb_initial_fpucw = __INITIAL_FPUCW__; 936 set_pcb_flags(pcb, PCB_FULL_IRET); 937 938 bzero((char *)regs, sizeof(struct trapframe)); 939 regs->tf_rip = imgp->entry_addr; 940 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; 941 regs->tf_rdi = stack; /* argv */ 942 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T); 943 regs->tf_ss = _udatasel; 944 regs->tf_cs = _ucodesel; 945 regs->tf_ds = _udatasel; 946 regs->tf_es = _udatasel; 947 regs->tf_fs = _ufssel; 948 regs->tf_gs = _ugssel; 949 regs->tf_flags = TF_HASSEGS; 950 td->td_retval[1] = 0; 951 952 /* 953 * Reset the hardware debug registers if they were in use. 954 * They won't have any meaning for the newly exec'd process. 955 */ 956 if (pcb->pcb_flags & PCB_DBREGS) { 957 pcb->pcb_dr0 = 0; 958 pcb->pcb_dr1 = 0; 959 pcb->pcb_dr2 = 0; 960 pcb->pcb_dr3 = 0; 961 pcb->pcb_dr6 = 0; 962 pcb->pcb_dr7 = 0; 963 if (pcb == curpcb) { 964 /* 965 * Clear the debug registers on the running 966 * CPU, otherwise they will end up affecting 967 * the next process we switch to. 968 */ 969 reset_dbregs(); 970 } 971 clear_pcb_flags(pcb, PCB_DBREGS); 972 } 973 974 /* 975 * Drop the FP state if we hold it, so that the process gets a 976 * clean FP state if it uses the FPU again. 977 */ 978 fpstate_drop(td); 979 } 980 981 void 982 cpu_setregs(void) 983 { 984 register_t cr0; 985 986 cr0 = rcr0(); 987 /* 988 * CR0_MP, CR0_NE and CR0_TS are also set by npx_probe() for the 989 * BSP. See the comments there about why we set them. 990 */ 991 cr0 |= CR0_MP | CR0_NE | CR0_TS | CR0_WP | CR0_AM; 992 load_cr0(cr0); 993 } 994 995 /* 996 * Initialize amd64 and configure to run kernel 997 */ 998 999 /* 1000 * Initialize segments & interrupt table 1001 */ 1002 1003 struct user_segment_descriptor gdt[NGDT * MAXCPU];/* global descriptor tables */ 1004 static struct gate_descriptor idt0[NIDT]; 1005 struct gate_descriptor *idt = &idt0[0]; /* interrupt descriptor table */ 1006 1007 static char dblfault_stack[PAGE_SIZE] __aligned(16); 1008 1009 static char nmi0_stack[PAGE_SIZE] __aligned(16); 1010 CTASSERT(sizeof(struct nmi_pcpu) == 16); 1011 1012 struct amd64tss common_tss[MAXCPU]; 1013 1014 /* 1015 * Software prototypes -- in more palatable form. 1016 * 1017 * Keep GUFS32, GUGS32, GUCODE32 and GUDATA at the same 1018 * slots as corresponding segments for i386 kernel. 1019 */ 1020 struct soft_segment_descriptor gdt_segs[] = { 1021 /* GNULL_SEL 0 Null Descriptor */ 1022 { .ssd_base = 0x0, 1023 .ssd_limit = 0x0, 1024 .ssd_type = 0, 1025 .ssd_dpl = 0, 1026 .ssd_p = 0, 1027 .ssd_long = 0, 1028 .ssd_def32 = 0, 1029 .ssd_gran = 0 }, 1030 /* GNULL2_SEL 1 Null Descriptor */ 1031 { .ssd_base = 0x0, 1032 .ssd_limit = 0x0, 1033 .ssd_type = 0, 1034 .ssd_dpl = 0, 1035 .ssd_p = 0, 1036 .ssd_long = 0, 1037 .ssd_def32 = 0, 1038 .ssd_gran = 0 }, 1039 /* GUFS32_SEL 2 32 bit %gs Descriptor for user */ 1040 { .ssd_base = 0x0, 1041 .ssd_limit = 0xfffff, 1042 .ssd_type = SDT_MEMRWA, 1043 .ssd_dpl = SEL_UPL, 1044 .ssd_p = 1, 1045 .ssd_long = 0, 1046 .ssd_def32 = 1, 1047 .ssd_gran = 1 }, 1048 /* GUGS32_SEL 3 32 bit %fs Descriptor for user */ 1049 { .ssd_base = 0x0, 1050 .ssd_limit = 0xfffff, 1051 .ssd_type = SDT_MEMRWA, 1052 .ssd_dpl = SEL_UPL, 1053 .ssd_p = 1, 1054 .ssd_long = 0, 1055 .ssd_def32 = 1, 1056 .ssd_gran = 1 }, 1057 /* GCODE_SEL 4 Code Descriptor for kernel */ 1058 { .ssd_base = 0x0, 1059 .ssd_limit = 0xfffff, 1060 .ssd_type = SDT_MEMERA, 1061 .ssd_dpl = SEL_KPL, 1062 .ssd_p = 1, 1063 .ssd_long = 1, 1064 .ssd_def32 = 0, 1065 .ssd_gran = 1 }, 1066 /* GDATA_SEL 5 Data Descriptor for kernel */ 1067 { .ssd_base = 0x0, 1068 .ssd_limit = 0xfffff, 1069 .ssd_type = SDT_MEMRWA, 1070 .ssd_dpl = SEL_KPL, 1071 .ssd_p = 1, 1072 .ssd_long = 1, 1073 .ssd_def32 = 0, 1074 .ssd_gran = 1 }, 1075 /* GUCODE32_SEL 6 32 bit Code Descriptor for user */ 1076 { .ssd_base = 0x0, 1077 .ssd_limit = 0xfffff, 1078 .ssd_type = SDT_MEMERA, 1079 .ssd_dpl = SEL_UPL, 1080 .ssd_p = 1, 1081 .ssd_long = 0, 1082 .ssd_def32 = 1, 1083 .ssd_gran = 1 }, 1084 /* GUDATA_SEL 7 32/64 bit Data Descriptor for user */ 1085 { .ssd_base = 0x0, 1086 .ssd_limit = 0xfffff, 1087 .ssd_type = SDT_MEMRWA, 1088 .ssd_dpl = SEL_UPL, 1089 .ssd_p = 1, 1090 .ssd_long = 0, 1091 .ssd_def32 = 1, 1092 .ssd_gran = 1 }, 1093 /* GUCODE_SEL 8 64 bit Code Descriptor for user */ 1094 { .ssd_base = 0x0, 1095 .ssd_limit = 0xfffff, 1096 .ssd_type = SDT_MEMERA, 1097 .ssd_dpl = SEL_UPL, 1098 .ssd_p = 1, 1099 .ssd_long = 1, 1100 .ssd_def32 = 0, 1101 .ssd_gran = 1 }, 1102 /* GPROC0_SEL 9 Proc 0 Tss Descriptor */ 1103 { .ssd_base = 0x0, 1104 .ssd_limit = sizeof(struct amd64tss) + IOPAGES * PAGE_SIZE - 1, 1105 .ssd_type = SDT_SYSTSS, 1106 .ssd_dpl = SEL_KPL, 1107 .ssd_p = 1, 1108 .ssd_long = 0, 1109 .ssd_def32 = 0, 1110 .ssd_gran = 0 }, 1111 /* Actually, the TSS is a system descriptor which is double size */ 1112 { .ssd_base = 0x0, 1113 .ssd_limit = 0x0, 1114 .ssd_type = 0, 1115 .ssd_dpl = 0, 1116 .ssd_p = 0, 1117 .ssd_long = 0, 1118 .ssd_def32 = 0, 1119 .ssd_gran = 0 }, 1120 /* GUSERLDT_SEL 11 LDT Descriptor */ 1121 { .ssd_base = 0x0, 1122 .ssd_limit = 0x0, 1123 .ssd_type = 0, 1124 .ssd_dpl = 0, 1125 .ssd_p = 0, 1126 .ssd_long = 0, 1127 .ssd_def32 = 0, 1128 .ssd_gran = 0 }, 1129 /* GUSERLDT_SEL 12 LDT Descriptor, double size */ 1130 { .ssd_base = 0x0, 1131 .ssd_limit = 0x0, 1132 .ssd_type = 0, 1133 .ssd_dpl = 0, 1134 .ssd_p = 0, 1135 .ssd_long = 0, 1136 .ssd_def32 = 0, 1137 .ssd_gran = 0 }, 1138 }; 1139 1140 void 1141 setidt(idx, func, typ, dpl, ist) 1142 int idx; 1143 inthand_t *func; 1144 int typ; 1145 int dpl; 1146 int ist; 1147 { 1148 struct gate_descriptor *ip; 1149 1150 ip = idt + idx; 1151 ip->gd_looffset = (uintptr_t)func; 1152 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL); 1153 ip->gd_ist = ist; 1154 ip->gd_xx = 0; 1155 ip->gd_type = typ; 1156 ip->gd_dpl = dpl; 1157 ip->gd_p = 1; 1158 ip->gd_hioffset = ((uintptr_t)func)>>16 ; 1159 } 1160 1161 extern inthand_t 1162 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl), 1163 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm), 1164 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot), 1165 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align), 1166 IDTVEC(xmm), IDTVEC(dblfault), 1167 #ifdef KDTRACE_HOOKS 1168 IDTVEC(dtrace_ret), 1169 #endif 1170 IDTVEC(fast_syscall), IDTVEC(fast_syscall32); 1171 1172 #ifdef DDB 1173 /* 1174 * Display the index and function name of any IDT entries that don't use 1175 * the default 'rsvd' entry point. 1176 */ 1177 DB_SHOW_COMMAND(idt, db_show_idt) 1178 { 1179 struct gate_descriptor *ip; 1180 int idx; 1181 uintptr_t func; 1182 1183 ip = idt; 1184 for (idx = 0; idx < NIDT && !db_pager_quit; idx++) { 1185 func = ((long)ip->gd_hioffset << 16 | ip->gd_looffset); 1186 if (func != (uintptr_t)&IDTVEC(rsvd)) { 1187 db_printf("%3d\t", idx); 1188 db_printsym(func, DB_STGY_PROC); 1189 db_printf("\n"); 1190 } 1191 ip++; 1192 } 1193 } 1194 1195 /* Show privileged registers. */ 1196 DB_SHOW_COMMAND(sysregs, db_show_sysregs) 1197 { 1198 struct { 1199 uint16_t limit; 1200 uint64_t base; 1201 } __packed idtr, gdtr; 1202 uint16_t ldt, tr; 1203 1204 __asm __volatile("sidt %0" : "=m" (idtr)); 1205 db_printf("idtr\t0x%016lx/%04x\n", 1206 (u_long)idtr.base, (u_int)idtr.limit); 1207 __asm __volatile("sgdt %0" : "=m" (gdtr)); 1208 db_printf("gdtr\t0x%016lx/%04x\n", 1209 (u_long)gdtr.base, (u_int)gdtr.limit); 1210 __asm __volatile("sldt %0" : "=r" (ldt)); 1211 db_printf("ldtr\t0x%04x\n", ldt); 1212 __asm __volatile("str %0" : "=r" (tr)); 1213 db_printf("tr\t0x%04x\n", tr); 1214 db_printf("cr0\t0x%016lx\n", rcr0()); 1215 db_printf("cr2\t0x%016lx\n", rcr2()); 1216 db_printf("cr3\t0x%016lx\n", rcr3()); 1217 db_printf("cr4\t0x%016lx\n", rcr4()); 1218 if (rcr4() & CR4_XSAVE) 1219 db_printf("xcr0\t0x%016lx\n", rxcr(0)); 1220 db_printf("EFER\t0x%016lx\n", rdmsr(MSR_EFER)); 1221 if (cpu_feature2 & (CPUID2_VMX | CPUID2_SMX)) 1222 db_printf("FEATURES_CTL\t%016lx\n", 1223 rdmsr(MSR_IA32_FEATURE_CONTROL)); 1224 db_printf("DEBUG_CTL\t0x%016lx\n", rdmsr(MSR_DEBUGCTLMSR)); 1225 db_printf("PAT\t0x%016lx\n", rdmsr(MSR_PAT)); 1226 db_printf("GSBASE\t0x%016lx\n", rdmsr(MSR_GSBASE)); 1227 } 1228 1229 DB_SHOW_COMMAND(dbregs, db_show_dbregs) 1230 { 1231 1232 db_printf("dr0\t0x%016lx\n", rdr0()); 1233 db_printf("dr1\t0x%016lx\n", rdr1()); 1234 db_printf("dr2\t0x%016lx\n", rdr2()); 1235 db_printf("dr3\t0x%016lx\n", rdr3()); 1236 db_printf("dr6\t0x%016lx\n", rdr6()); 1237 db_printf("dr7\t0x%016lx\n", rdr7()); 1238 } 1239 #endif 1240 1241 void 1242 sdtossd(sd, ssd) 1243 struct user_segment_descriptor *sd; 1244 struct soft_segment_descriptor *ssd; 1245 { 1246 1247 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase; 1248 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit; 1249 ssd->ssd_type = sd->sd_type; 1250 ssd->ssd_dpl = sd->sd_dpl; 1251 ssd->ssd_p = sd->sd_p; 1252 ssd->ssd_long = sd->sd_long; 1253 ssd->ssd_def32 = sd->sd_def32; 1254 ssd->ssd_gran = sd->sd_gran; 1255 } 1256 1257 void 1258 ssdtosd(ssd, sd) 1259 struct soft_segment_descriptor *ssd; 1260 struct user_segment_descriptor *sd; 1261 { 1262 1263 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1264 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff; 1265 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1266 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1267 sd->sd_type = ssd->ssd_type; 1268 sd->sd_dpl = ssd->ssd_dpl; 1269 sd->sd_p = ssd->ssd_p; 1270 sd->sd_long = ssd->ssd_long; 1271 sd->sd_def32 = ssd->ssd_def32; 1272 sd->sd_gran = ssd->ssd_gran; 1273 } 1274 1275 void 1276 ssdtosyssd(ssd, sd) 1277 struct soft_segment_descriptor *ssd; 1278 struct system_segment_descriptor *sd; 1279 { 1280 1281 sd->sd_lobase = (ssd->ssd_base) & 0xffffff; 1282 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful; 1283 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff; 1284 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf; 1285 sd->sd_type = ssd->ssd_type; 1286 sd->sd_dpl = ssd->ssd_dpl; 1287 sd->sd_p = ssd->ssd_p; 1288 sd->sd_gran = ssd->ssd_gran; 1289 } 1290 1291 #if !defined(DEV_ATPIC) && defined(DEV_ISA) 1292 #include <isa/isavar.h> 1293 #include <isa/isareg.h> 1294 /* 1295 * Return a bitmap of the current interrupt requests. This is 8259-specific 1296 * and is only suitable for use at probe time. 1297 * This is only here to pacify sio. It is NOT FATAL if this doesn't work. 1298 * It shouldn't be here. There should probably be an APIC centric 1299 * implementation in the apic driver code, if at all. 1300 */ 1301 intrmask_t 1302 isa_irq_pending(void) 1303 { 1304 u_char irr1; 1305 u_char irr2; 1306 1307 irr1 = inb(IO_ICU1); 1308 irr2 = inb(IO_ICU2); 1309 return ((irr2 << 8) | irr1); 1310 } 1311 #endif 1312 1313 u_int basemem; 1314 1315 static int 1316 add_smap_entry(struct bios_smap *smap, vm_paddr_t *physmap, int *physmap_idxp) 1317 { 1318 int i, insert_idx, physmap_idx; 1319 1320 physmap_idx = *physmap_idxp; 1321 1322 if (boothowto & RB_VERBOSE) 1323 printf("SMAP type=%02x base=%016lx len=%016lx\n", 1324 smap->type, smap->base, smap->length); 1325 1326 if (smap->type != SMAP_TYPE_MEMORY) 1327 return (1); 1328 1329 if (smap->length == 0) 1330 return (0); 1331 1332 /* 1333 * Find insertion point while checking for overlap. Start off by 1334 * assuming the new entry will be added to the end. 1335 */ 1336 insert_idx = physmap_idx + 2; 1337 for (i = 0; i <= physmap_idx; i += 2) { 1338 if (smap->base < physmap[i + 1]) { 1339 if (smap->base + smap->length <= physmap[i]) { 1340 insert_idx = i; 1341 break; 1342 } 1343 if (boothowto & RB_VERBOSE) 1344 printf( 1345 "Overlapping memory regions, ignoring second region\n"); 1346 return (1); 1347 } 1348 } 1349 1350 /* See if we can prepend to the next entry. */ 1351 if (insert_idx <= physmap_idx && 1352 smap->base + smap->length == physmap[insert_idx]) { 1353 physmap[insert_idx] = smap->base; 1354 return (1); 1355 } 1356 1357 /* See if we can append to the previous entry. */ 1358 if (insert_idx > 0 && smap->base == physmap[insert_idx - 1]) { 1359 physmap[insert_idx - 1] += smap->length; 1360 return (1); 1361 } 1362 1363 physmap_idx += 2; 1364 *physmap_idxp = physmap_idx; 1365 if (physmap_idx == PHYSMAP_SIZE) { 1366 printf( 1367 "Too many segments in the physical address map, giving up\n"); 1368 return (0); 1369 } 1370 1371 /* 1372 * Move the last 'N' entries down to make room for the new 1373 * entry if needed. 1374 */ 1375 for (i = physmap_idx; i > insert_idx; i -= 2) { 1376 physmap[i] = physmap[i - 2]; 1377 physmap[i + 1] = physmap[i - 1]; 1378 } 1379 1380 /* Insert the new entry. */ 1381 physmap[insert_idx] = smap->base; 1382 physmap[insert_idx + 1] = smap->base + smap->length; 1383 return (1); 1384 } 1385 1386 #define PAGES_PER_GB (1024 * 1024 * 1024 / PAGE_SIZE) 1387 1388 /* 1389 * Populate the (physmap) array with base/bound pairs describing the 1390 * available physical memory in the system, then test this memory and 1391 * build the phys_avail array describing the actually-available memory. 1392 * 1393 * Total memory size may be set by the kernel environment variable 1394 * hw.physmem or the compile-time define MAXMEM. 1395 * 1396 * XXX first should be vm_paddr_t. 1397 */ 1398 static void 1399 getmemsize(caddr_t kmdp, u_int64_t first) 1400 { 1401 int i, physmap_idx, pa_indx, da_indx; 1402 vm_paddr_t pa, physmap[PHYSMAP_SIZE]; 1403 u_long physmem_start, physmem_tunable, memtest; 1404 pt_entry_t *pte; 1405 struct bios_smap *smapbase, *smap, *smapend; 1406 u_int32_t smapsize; 1407 quad_t dcons_addr, dcons_size; 1408 int page_counter; 1409 1410 bzero(physmap, sizeof(physmap)); 1411 basemem = 0; 1412 physmap_idx = 0; 1413 1414 /* 1415 * get memory map from INT 15:E820, kindly supplied by the loader. 1416 * 1417 * subr_module.c says: 1418 * "Consumer may safely assume that size value precedes data." 1419 * ie: an int32_t immediately precedes smap. 1420 */ 1421 smapbase = (struct bios_smap *)preload_search_info(kmdp, 1422 MODINFO_METADATA | MODINFOMD_SMAP); 1423 if (smapbase == NULL) 1424 panic("No BIOS smap info from loader!"); 1425 1426 smapsize = *((u_int32_t *)smapbase - 1); 1427 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize); 1428 1429 for (smap = smapbase; smap < smapend; smap++) 1430 if (!add_smap_entry(smap, physmap, &physmap_idx)) 1431 break; 1432 1433 /* 1434 * Find the 'base memory' segment for SMP 1435 */ 1436 basemem = 0; 1437 for (i = 0; i <= physmap_idx; i += 2) { 1438 if (physmap[i] == 0x00000000) { 1439 basemem = physmap[i + 1] / 1024; 1440 break; 1441 } 1442 } 1443 if (basemem == 0) 1444 panic("BIOS smap did not include a basemem segment!"); 1445 1446 #ifdef SMP 1447 /* make hole for AP bootstrap code */ 1448 physmap[1] = mp_bootaddress(physmap[1] / 1024); 1449 #endif 1450 1451 /* 1452 * Maxmem isn't the "maximum memory", it's one larger than the 1453 * highest page of the physical address space. It should be 1454 * called something like "Maxphyspage". We may adjust this 1455 * based on ``hw.physmem'' and the results of the memory test. 1456 */ 1457 Maxmem = atop(physmap[physmap_idx + 1]); 1458 1459 #ifdef MAXMEM 1460 Maxmem = MAXMEM / 4; 1461 #endif 1462 1463 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable)) 1464 Maxmem = atop(physmem_tunable); 1465 1466 /* 1467 * By default enable the memory test on real hardware, and disable 1468 * it if we appear to be running in a VM. This avoids touching all 1469 * pages unnecessarily, which doesn't matter on real hardware but is 1470 * bad for shared VM hosts. Use a general name so that 1471 * one could eventually do more with the code than just disable it. 1472 */ 1473 memtest = (vm_guest > VM_GUEST_NO) ? 0 : 1; 1474 TUNABLE_ULONG_FETCH("hw.memtest.tests", &memtest); 1475 1476 /* 1477 * Don't allow MAXMEM or hw.physmem to extend the amount of memory 1478 * in the system. 1479 */ 1480 if (Maxmem > atop(physmap[physmap_idx + 1])) 1481 Maxmem = atop(physmap[physmap_idx + 1]); 1482 1483 if (atop(physmap[physmap_idx + 1]) != Maxmem && 1484 (boothowto & RB_VERBOSE)) 1485 printf("Physical memory use set to %ldK\n", Maxmem * 4); 1486 1487 /* call pmap initialization to make new kernel address space */ 1488 pmap_bootstrap(&first); 1489 1490 /* 1491 * Size up each available chunk of physical memory. 1492 * 1493 * XXX Some BIOSes corrupt low 64KB between suspend and resume. 1494 * By default, mask off the first 16 pages unless we appear to be 1495 * running in a VM. 1496 */ 1497 physmem_start = (vm_guest > VM_GUEST_NO ? 1 : 16) << PAGE_SHIFT; 1498 TUNABLE_ULONG_FETCH("hw.physmem.start", &physmem_start); 1499 if (physmem_start < PAGE_SIZE) 1500 physmap[0] = PAGE_SIZE; 1501 else if (physmem_start >= physmap[1]) 1502 physmap[0] = round_page(physmap[1] - PAGE_SIZE); 1503 else 1504 physmap[0] = round_page(physmem_start); 1505 pa_indx = 0; 1506 da_indx = 1; 1507 phys_avail[pa_indx++] = physmap[0]; 1508 phys_avail[pa_indx] = physmap[0]; 1509 dump_avail[da_indx] = physmap[0]; 1510 pte = CMAP1; 1511 1512 /* 1513 * Get dcons buffer address 1514 */ 1515 if (getenv_quad("dcons.addr", &dcons_addr) == 0 || 1516 getenv_quad("dcons.size", &dcons_size) == 0) 1517 dcons_addr = 0; 1518 1519 /* 1520 * physmap is in bytes, so when converting to page boundaries, 1521 * round up the start address and round down the end address. 1522 */ 1523 page_counter = 0; 1524 if (memtest != 0) 1525 printf("Testing system memory"); 1526 for (i = 0; i <= physmap_idx; i += 2) { 1527 vm_paddr_t end; 1528 1529 end = ptoa((vm_paddr_t)Maxmem); 1530 if (physmap[i + 1] < end) 1531 end = trunc_page(physmap[i + 1]); 1532 for (pa = round_page(physmap[i]); pa < end; pa += PAGE_SIZE) { 1533 int tmp, page_bad, full; 1534 int *ptr = (int *)CADDR1; 1535 1536 full = FALSE; 1537 /* 1538 * block out kernel memory as not available. 1539 */ 1540 if (pa >= (vm_paddr_t)kernphys && pa < first) 1541 goto do_dump_avail; 1542 1543 /* 1544 * block out dcons buffer 1545 */ 1546 if (dcons_addr > 0 1547 && pa >= trunc_page(dcons_addr) 1548 && pa < dcons_addr + dcons_size) 1549 goto do_dump_avail; 1550 1551 page_bad = FALSE; 1552 if (memtest == 0) 1553 goto skip_memtest; 1554 1555 /* 1556 * Print a "." every GB to show we're making 1557 * progress. 1558 */ 1559 page_counter++; 1560 if ((page_counter % PAGES_PER_GB) == 0) 1561 printf("."); 1562 1563 /* 1564 * map page into kernel: valid, read/write,non-cacheable 1565 */ 1566 *pte = pa | PG_V | PG_RW | PG_N; 1567 invltlb(); 1568 1569 tmp = *(int *)ptr; 1570 /* 1571 * Test for alternating 1's and 0's 1572 */ 1573 *(volatile int *)ptr = 0xaaaaaaaa; 1574 if (*(volatile int *)ptr != 0xaaaaaaaa) 1575 page_bad = TRUE; 1576 /* 1577 * Test for alternating 0's and 1's 1578 */ 1579 *(volatile int *)ptr = 0x55555555; 1580 if (*(volatile int *)ptr != 0x55555555) 1581 page_bad = TRUE; 1582 /* 1583 * Test for all 1's 1584 */ 1585 *(volatile int *)ptr = 0xffffffff; 1586 if (*(volatile int *)ptr != 0xffffffff) 1587 page_bad = TRUE; 1588 /* 1589 * Test for all 0's 1590 */ 1591 *(volatile int *)ptr = 0x0; 1592 if (*(volatile int *)ptr != 0x0) 1593 page_bad = TRUE; 1594 /* 1595 * Restore original value. 1596 */ 1597 *(int *)ptr = tmp; 1598 1599 skip_memtest: 1600 /* 1601 * Adjust array of valid/good pages. 1602 */ 1603 if (page_bad == TRUE) 1604 continue; 1605 /* 1606 * If this good page is a continuation of the 1607 * previous set of good pages, then just increase 1608 * the end pointer. Otherwise start a new chunk. 1609 * Note that "end" points one higher than end, 1610 * making the range >= start and < end. 1611 * If we're also doing a speculative memory 1612 * test and we at or past the end, bump up Maxmem 1613 * so that we keep going. The first bad page 1614 * will terminate the loop. 1615 */ 1616 if (phys_avail[pa_indx] == pa) { 1617 phys_avail[pa_indx] += PAGE_SIZE; 1618 } else { 1619 pa_indx++; 1620 if (pa_indx == PHYS_AVAIL_ARRAY_END) { 1621 printf( 1622 "Too many holes in the physical address space, giving up\n"); 1623 pa_indx--; 1624 full = TRUE; 1625 goto do_dump_avail; 1626 } 1627 phys_avail[pa_indx++] = pa; /* start */ 1628 phys_avail[pa_indx] = pa + PAGE_SIZE; /* end */ 1629 } 1630 physmem++; 1631 do_dump_avail: 1632 if (dump_avail[da_indx] == pa) { 1633 dump_avail[da_indx] += PAGE_SIZE; 1634 } else { 1635 da_indx++; 1636 if (da_indx == DUMP_AVAIL_ARRAY_END) { 1637 da_indx--; 1638 goto do_next; 1639 } 1640 dump_avail[da_indx++] = pa; /* start */ 1641 dump_avail[da_indx] = pa + PAGE_SIZE; /* end */ 1642 } 1643 do_next: 1644 if (full) 1645 break; 1646 } 1647 } 1648 *pte = 0; 1649 invltlb(); 1650 if (memtest != 0) 1651 printf("\n"); 1652 1653 /* 1654 * XXX 1655 * The last chunk must contain at least one page plus the message 1656 * buffer to avoid complicating other code (message buffer address 1657 * calculation, etc.). 1658 */ 1659 while (phys_avail[pa_indx - 1] + PAGE_SIZE + 1660 round_page(msgbufsize) >= phys_avail[pa_indx]) { 1661 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]); 1662 phys_avail[pa_indx--] = 0; 1663 phys_avail[pa_indx--] = 0; 1664 } 1665 1666 Maxmem = atop(phys_avail[pa_indx]); 1667 1668 /* Trim off space for the message buffer. */ 1669 phys_avail[pa_indx] -= round_page(msgbufsize); 1670 1671 /* Map the message buffer. */ 1672 msgbufp = (struct msgbuf *)PHYS_TO_DMAP(phys_avail[pa_indx]); 1673 } 1674 1675 u_int64_t 1676 hammer_time(u_int64_t modulep, u_int64_t physfree) 1677 { 1678 caddr_t kmdp; 1679 int gsel_tss, x; 1680 struct pcpu *pc; 1681 struct nmi_pcpu *np; 1682 struct xstate_hdr *xhdr; 1683 u_int64_t msr; 1684 char *env; 1685 size_t kstack0_sz; 1686 1687 thread0.td_kstack = physfree + KERNBASE; 1688 thread0.td_kstack_pages = KSTACK_PAGES; 1689 kstack0_sz = thread0.td_kstack_pages * PAGE_SIZE; 1690 bzero((void *)thread0.td_kstack, kstack0_sz); 1691 physfree += kstack0_sz; 1692 1693 /* 1694 * This may be done better later if it gets more high level 1695 * components in it. If so just link td->td_proc here. 1696 */ 1697 proc_linkup0(&proc0, &thread0); 1698 1699 preload_metadata = (caddr_t)(uintptr_t)(modulep + KERNBASE); 1700 preload_bootstrap_relocate(KERNBASE); 1701 kmdp = preload_search_by_type("elf kernel"); 1702 if (kmdp == NULL) 1703 kmdp = preload_search_by_type("elf64 kernel"); 1704 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int); 1705 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + KERNBASE; 1706 #ifdef DDB 1707 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t); 1708 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t); 1709 #endif 1710 1711 /* Init basic tunables, hz etc */ 1712 init_param1(); 1713 1714 /* 1715 * make gdt memory segments 1716 */ 1717 for (x = 0; x < NGDT; x++) { 1718 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) && 1719 x != GUSERLDT_SEL && x != (GUSERLDT_SEL) + 1) 1720 ssdtosd(&gdt_segs[x], &gdt[x]); 1721 } 1722 gdt_segs[GPROC0_SEL].ssd_base = (uintptr_t)&common_tss[0]; 1723 ssdtosyssd(&gdt_segs[GPROC0_SEL], 1724 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1725 1726 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 1727 r_gdt.rd_base = (long) gdt; 1728 lgdt(&r_gdt); 1729 pc = &__pcpu[0]; 1730 1731 wrmsr(MSR_FSBASE, 0); /* User value */ 1732 wrmsr(MSR_GSBASE, (u_int64_t)pc); 1733 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */ 1734 1735 pcpu_init(pc, 0, sizeof(struct pcpu)); 1736 dpcpu_init((void *)(physfree + KERNBASE), 0); 1737 physfree += DPCPU_SIZE; 1738 PCPU_SET(prvspace, pc); 1739 PCPU_SET(curthread, &thread0); 1740 PCPU_SET(tssp, &common_tss[0]); 1741 PCPU_SET(commontssp, &common_tss[0]); 1742 PCPU_SET(tss, (struct system_segment_descriptor *)&gdt[GPROC0_SEL]); 1743 PCPU_SET(ldt, (struct system_segment_descriptor *)&gdt[GUSERLDT_SEL]); 1744 PCPU_SET(fs32p, &gdt[GUFS32_SEL]); 1745 PCPU_SET(gs32p, &gdt[GUGS32_SEL]); 1746 1747 /* 1748 * Initialize mutexes. 1749 * 1750 * icu_lock: in order to allow an interrupt to occur in a critical 1751 * section, to set pcpu->ipending (etc...) properly, we 1752 * must be able to get the icu lock, so it can't be 1753 * under witness. 1754 */ 1755 mutex_init(); 1756 mtx_init(&icu_lock, "icu", NULL, MTX_SPIN | MTX_NOWITNESS); 1757 mtx_init(&dt_lock, "descriptor tables", NULL, MTX_DEF); 1758 1759 /* exceptions */ 1760 for (x = 0; x < NIDT; x++) 1761 setidt(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0); 1762 setidt(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0); 1763 setidt(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0); 1764 setidt(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 2); 1765 setidt(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0); 1766 setidt(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0); 1767 setidt(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0); 1768 setidt(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0); 1769 setidt(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0); 1770 setidt(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1); 1771 setidt(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0); 1772 setidt(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0); 1773 setidt(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0); 1774 setidt(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0); 1775 setidt(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0); 1776 setidt(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0); 1777 setidt(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0); 1778 setidt(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0); 1779 setidt(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0); 1780 setidt(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0); 1781 #ifdef KDTRACE_HOOKS 1782 setidt(IDT_DTRACE_RET, &IDTVEC(dtrace_ret), SDT_SYSIGT, SEL_UPL, 0); 1783 #endif 1784 1785 r_idt.rd_limit = sizeof(idt0) - 1; 1786 r_idt.rd_base = (long) idt; 1787 lidt(&r_idt); 1788 1789 /* 1790 * Initialize the i8254 before the console so that console 1791 * initialization can use DELAY(). 1792 */ 1793 i8254_init(); 1794 1795 /* 1796 * Initialize the console before we print anything out. 1797 */ 1798 cninit(); 1799 1800 #ifdef DEV_ISA 1801 #ifdef DEV_ATPIC 1802 elcr_probe(); 1803 atpic_startup(); 1804 #else 1805 /* Reset and mask the atpics and leave them shut down. */ 1806 atpic_reset(); 1807 1808 /* 1809 * Point the ICU spurious interrupt vectors at the APIC spurious 1810 * interrupt handler. 1811 */ 1812 setidt(IDT_IO_INTS + 7, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1813 setidt(IDT_IO_INTS + 15, IDTVEC(spuriousint), SDT_SYSIGT, SEL_KPL, 0); 1814 #endif 1815 #else 1816 #error "have you forgotten the isa device?"; 1817 #endif 1818 1819 kdb_init(); 1820 1821 #ifdef KDB 1822 if (boothowto & RB_KDB) 1823 kdb_enter(KDB_WHY_BOOTFLAGS, 1824 "Boot flags requested debugger"); 1825 #endif 1826 1827 identify_cpu(); /* Final stage of CPU initialization */ 1828 initializecpu(); /* Initialize CPU registers */ 1829 initializecpucache(); 1830 1831 /* doublefault stack space, runs on ist1 */ 1832 common_tss[0].tss_ist1 = (long)&dblfault_stack[sizeof(dblfault_stack)]; 1833 1834 /* 1835 * NMI stack, runs on ist2. The pcpu pointer is stored just 1836 * above the start of the ist2 stack. 1837 */ 1838 np = ((struct nmi_pcpu *) &nmi0_stack[sizeof(nmi0_stack)]) - 1; 1839 np->np_pcpu = (register_t) pc; 1840 common_tss[0].tss_ist2 = (long) np; 1841 1842 /* Set the IO permission bitmap (empty due to tss seg limit) */ 1843 common_tss[0].tss_iobase = sizeof(struct amd64tss) + 1844 IOPAGES * PAGE_SIZE; 1845 1846 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 1847 ltr(gsel_tss); 1848 1849 /* Set up the fast syscall stuff */ 1850 msr = rdmsr(MSR_EFER) | EFER_SCE; 1851 wrmsr(MSR_EFER, msr); 1852 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall)); 1853 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32)); 1854 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) | 1855 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48); 1856 wrmsr(MSR_STAR, msr); 1857 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D); 1858 1859 getmemsize(kmdp, physfree); 1860 init_param2(physmem); 1861 1862 /* now running on new page tables, configured,and u/iom is accessible */ 1863 1864 msgbufinit(msgbufp, msgbufsize); 1865 fpuinit(); 1866 1867 /* 1868 * Set up thread0 pcb after fpuinit calculated pcb + fpu save 1869 * area size. Zero out the extended state header in fpu save 1870 * area. 1871 */ 1872 thread0.td_pcb = get_pcb_td(&thread0); 1873 bzero(get_pcb_user_save_td(&thread0), cpu_max_ext_state_size); 1874 if (use_xsave) { 1875 xhdr = (struct xstate_hdr *)(get_pcb_user_save_td(&thread0) + 1876 1); 1877 xhdr->xstate_bv = xsave_mask; 1878 } 1879 /* make an initial tss so cpu can get interrupt stack on syscall! */ 1880 common_tss[0].tss_rsp0 = (vm_offset_t)thread0.td_pcb; 1881 /* Ensure the stack is aligned to 16 bytes */ 1882 common_tss[0].tss_rsp0 &= ~0xFul; 1883 PCPU_SET(rsp0, common_tss[0].tss_rsp0); 1884 PCPU_SET(curpcb, thread0.td_pcb); 1885 1886 /* transfer to user mode */ 1887 1888 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL); 1889 _udatasel = GSEL(GUDATA_SEL, SEL_UPL); 1890 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL); 1891 _ufssel = GSEL(GUFS32_SEL, SEL_UPL); 1892 _ugssel = GSEL(GUGS32_SEL, SEL_UPL); 1893 1894 load_ds(_udatasel); 1895 load_es(_udatasel); 1896 load_fs(_ufssel); 1897 1898 /* setup proc 0's pcb */ 1899 thread0.td_pcb->pcb_flags = 0; 1900 thread0.td_pcb->pcb_cr3 = KPML4phys; 1901 thread0.td_frame = &proc0_tf; 1902 1903 env = getenv("kernelname"); 1904 if (env != NULL) 1905 strlcpy(kernelname, env, sizeof(kernelname)); 1906 1907 #ifdef XENHVM 1908 if (inw(0x10) == 0x49d2) { 1909 if (bootverbose) 1910 printf("Xen detected: disabling emulated block and network devices\n"); 1911 outw(0x10, 3); 1912 } 1913 #endif 1914 1915 cpu_probe_amdc1e(); 1916 1917 /* Location of kernel stack for locore */ 1918 return ((u_int64_t)thread0.td_pcb); 1919 } 1920 1921 void 1922 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size) 1923 { 1924 1925 pcpu->pc_acpi_id = 0xffffffff; 1926 } 1927 1928 void 1929 spinlock_enter(void) 1930 { 1931 struct thread *td; 1932 register_t flags; 1933 1934 td = curthread; 1935 if (td->td_md.md_spinlock_count == 0) { 1936 flags = intr_disable(); 1937 td->td_md.md_spinlock_count = 1; 1938 td->td_md.md_saved_flags = flags; 1939 } else 1940 td->td_md.md_spinlock_count++; 1941 critical_enter(); 1942 } 1943 1944 void 1945 spinlock_exit(void) 1946 { 1947 struct thread *td; 1948 register_t flags; 1949 1950 td = curthread; 1951 critical_exit(); 1952 flags = td->td_md.md_saved_flags; 1953 td->td_md.md_spinlock_count--; 1954 if (td->td_md.md_spinlock_count == 0) 1955 intr_restore(flags); 1956 } 1957 1958 /* 1959 * Construct a PCB from a trapframe. This is called from kdb_trap() where 1960 * we want to start a backtrace from the function that caused us to enter 1961 * the debugger. We have the context in the trapframe, but base the trace 1962 * on the PCB. The PCB doesn't have to be perfect, as long as it contains 1963 * enough for a backtrace. 1964 */ 1965 void 1966 makectx(struct trapframe *tf, struct pcb *pcb) 1967 { 1968 1969 pcb->pcb_r12 = tf->tf_r12; 1970 pcb->pcb_r13 = tf->tf_r13; 1971 pcb->pcb_r14 = tf->tf_r14; 1972 pcb->pcb_r15 = tf->tf_r15; 1973 pcb->pcb_rbp = tf->tf_rbp; 1974 pcb->pcb_rbx = tf->tf_rbx; 1975 pcb->pcb_rip = tf->tf_rip; 1976 pcb->pcb_rsp = tf->tf_rsp; 1977 } 1978 1979 int 1980 ptrace_set_pc(struct thread *td, unsigned long addr) 1981 { 1982 1983 td->td_frame->tf_rip = addr; 1984 set_pcb_flags(td->td_pcb, PCB_FULL_IRET); 1985 return (0); 1986 } 1987 1988 int 1989 ptrace_single_step(struct thread *td) 1990 { 1991 td->td_frame->tf_rflags |= PSL_T; 1992 return (0); 1993 } 1994 1995 int 1996 ptrace_clear_single_step(struct thread *td) 1997 { 1998 td->td_frame->tf_rflags &= ~PSL_T; 1999 return (0); 2000 } 2001 2002 int 2003 fill_regs(struct thread *td, struct reg *regs) 2004 { 2005 struct trapframe *tp; 2006 2007 tp = td->td_frame; 2008 return (fill_frame_regs(tp, regs)); 2009 } 2010 2011 int 2012 fill_frame_regs(struct trapframe *tp, struct reg *regs) 2013 { 2014 regs->r_r15 = tp->tf_r15; 2015 regs->r_r14 = tp->tf_r14; 2016 regs->r_r13 = tp->tf_r13; 2017 regs->r_r12 = tp->tf_r12; 2018 regs->r_r11 = tp->tf_r11; 2019 regs->r_r10 = tp->tf_r10; 2020 regs->r_r9 = tp->tf_r9; 2021 regs->r_r8 = tp->tf_r8; 2022 regs->r_rdi = tp->tf_rdi; 2023 regs->r_rsi = tp->tf_rsi; 2024 regs->r_rbp = tp->tf_rbp; 2025 regs->r_rbx = tp->tf_rbx; 2026 regs->r_rdx = tp->tf_rdx; 2027 regs->r_rcx = tp->tf_rcx; 2028 regs->r_rax = tp->tf_rax; 2029 regs->r_rip = tp->tf_rip; 2030 regs->r_cs = tp->tf_cs; 2031 regs->r_rflags = tp->tf_rflags; 2032 regs->r_rsp = tp->tf_rsp; 2033 regs->r_ss = tp->tf_ss; 2034 if (tp->tf_flags & TF_HASSEGS) { 2035 regs->r_ds = tp->tf_ds; 2036 regs->r_es = tp->tf_es; 2037 regs->r_fs = tp->tf_fs; 2038 regs->r_gs = tp->tf_gs; 2039 } else { 2040 regs->r_ds = 0; 2041 regs->r_es = 0; 2042 regs->r_fs = 0; 2043 regs->r_gs = 0; 2044 } 2045 return (0); 2046 } 2047 2048 int 2049 set_regs(struct thread *td, struct reg *regs) 2050 { 2051 struct trapframe *tp; 2052 register_t rflags; 2053 2054 tp = td->td_frame; 2055 rflags = regs->r_rflags & 0xffffffff; 2056 if (!EFL_SECURE(rflags, tp->tf_rflags) || !CS_SECURE(regs->r_cs)) 2057 return (EINVAL); 2058 tp->tf_r15 = regs->r_r15; 2059 tp->tf_r14 = regs->r_r14; 2060 tp->tf_r13 = regs->r_r13; 2061 tp->tf_r12 = regs->r_r12; 2062 tp->tf_r11 = regs->r_r11; 2063 tp->tf_r10 = regs->r_r10; 2064 tp->tf_r9 = regs->r_r9; 2065 tp->tf_r8 = regs->r_r8; 2066 tp->tf_rdi = regs->r_rdi; 2067 tp->tf_rsi = regs->r_rsi; 2068 tp->tf_rbp = regs->r_rbp; 2069 tp->tf_rbx = regs->r_rbx; 2070 tp->tf_rdx = regs->r_rdx; 2071 tp->tf_rcx = regs->r_rcx; 2072 tp->tf_rax = regs->r_rax; 2073 tp->tf_rip = regs->r_rip; 2074 tp->tf_cs = regs->r_cs; 2075 tp->tf_rflags = rflags; 2076 tp->tf_rsp = regs->r_rsp; 2077 tp->tf_ss = regs->r_ss; 2078 if (0) { /* XXXKIB */ 2079 tp->tf_ds = regs->r_ds; 2080 tp->tf_es = regs->r_es; 2081 tp->tf_fs = regs->r_fs; 2082 tp->tf_gs = regs->r_gs; 2083 tp->tf_flags = TF_HASSEGS; 2084 } 2085 set_pcb_flags(td->td_pcb, PCB_FULL_IRET); 2086 return (0); 2087 } 2088 2089 /* XXX check all this stuff! */ 2090 /* externalize from sv_xmm */ 2091 static void 2092 fill_fpregs_xmm(struct savefpu *sv_xmm, struct fpreg *fpregs) 2093 { 2094 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2095 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2096 int i; 2097 2098 /* pcb -> fpregs */ 2099 bzero(fpregs, sizeof(*fpregs)); 2100 2101 /* FPU control/status */ 2102 penv_fpreg->en_cw = penv_xmm->en_cw; 2103 penv_fpreg->en_sw = penv_xmm->en_sw; 2104 penv_fpreg->en_tw = penv_xmm->en_tw; 2105 penv_fpreg->en_opcode = penv_xmm->en_opcode; 2106 penv_fpreg->en_rip = penv_xmm->en_rip; 2107 penv_fpreg->en_rdp = penv_xmm->en_rdp; 2108 penv_fpreg->en_mxcsr = penv_xmm->en_mxcsr; 2109 penv_fpreg->en_mxcsr_mask = penv_xmm->en_mxcsr_mask; 2110 2111 /* FPU registers */ 2112 for (i = 0; i < 8; ++i) 2113 bcopy(sv_xmm->sv_fp[i].fp_acc.fp_bytes, fpregs->fpr_acc[i], 10); 2114 2115 /* SSE registers */ 2116 for (i = 0; i < 16; ++i) 2117 bcopy(sv_xmm->sv_xmm[i].xmm_bytes, fpregs->fpr_xacc[i], 16); 2118 } 2119 2120 /* internalize from fpregs into sv_xmm */ 2121 static void 2122 set_fpregs_xmm(struct fpreg *fpregs, struct savefpu *sv_xmm) 2123 { 2124 struct envxmm *penv_xmm = &sv_xmm->sv_env; 2125 struct envxmm *penv_fpreg = (struct envxmm *)&fpregs->fpr_env; 2126 int i; 2127 2128 /* fpregs -> pcb */ 2129 /* FPU control/status */ 2130 penv_xmm->en_cw = penv_fpreg->en_cw; 2131 penv_xmm->en_sw = penv_fpreg->en_sw; 2132 penv_xmm->en_tw = penv_fpreg->en_tw; 2133 penv_xmm->en_opcode = penv_fpreg->en_opcode; 2134 penv_xmm->en_rip = penv_fpreg->en_rip; 2135 penv_xmm->en_rdp = penv_fpreg->en_rdp; 2136 penv_xmm->en_mxcsr = penv_fpreg->en_mxcsr; 2137 penv_xmm->en_mxcsr_mask = penv_fpreg->en_mxcsr_mask & cpu_mxcsr_mask; 2138 2139 /* FPU registers */ 2140 for (i = 0; i < 8; ++i) 2141 bcopy(fpregs->fpr_acc[i], sv_xmm->sv_fp[i].fp_acc.fp_bytes, 10); 2142 2143 /* SSE registers */ 2144 for (i = 0; i < 16; ++i) 2145 bcopy(fpregs->fpr_xacc[i], sv_xmm->sv_xmm[i].xmm_bytes, 16); 2146 } 2147 2148 /* externalize from td->pcb */ 2149 int 2150 fill_fpregs(struct thread *td, struct fpreg *fpregs) 2151 { 2152 2153 KASSERT(td == curthread || TD_IS_SUSPENDED(td) || 2154 P_SHOULDSTOP(td->td_proc), 2155 ("not suspended thread %p", td)); 2156 fpugetregs(td); 2157 fill_fpregs_xmm(get_pcb_user_save_td(td), fpregs); 2158 return (0); 2159 } 2160 2161 /* internalize to td->pcb */ 2162 int 2163 set_fpregs(struct thread *td, struct fpreg *fpregs) 2164 { 2165 2166 set_fpregs_xmm(fpregs, get_pcb_user_save_td(td)); 2167 fpuuserinited(td); 2168 return (0); 2169 } 2170 2171 /* 2172 * Get machine context. 2173 */ 2174 int 2175 get_mcontext(struct thread *td, mcontext_t *mcp, int flags) 2176 { 2177 struct pcb *pcb; 2178 struct trapframe *tp; 2179 2180 pcb = td->td_pcb; 2181 tp = td->td_frame; 2182 PROC_LOCK(curthread->td_proc); 2183 mcp->mc_onstack = sigonstack(tp->tf_rsp); 2184 PROC_UNLOCK(curthread->td_proc); 2185 mcp->mc_r15 = tp->tf_r15; 2186 mcp->mc_r14 = tp->tf_r14; 2187 mcp->mc_r13 = tp->tf_r13; 2188 mcp->mc_r12 = tp->tf_r12; 2189 mcp->mc_r11 = tp->tf_r11; 2190 mcp->mc_r10 = tp->tf_r10; 2191 mcp->mc_r9 = tp->tf_r9; 2192 mcp->mc_r8 = tp->tf_r8; 2193 mcp->mc_rdi = tp->tf_rdi; 2194 mcp->mc_rsi = tp->tf_rsi; 2195 mcp->mc_rbp = tp->tf_rbp; 2196 mcp->mc_rbx = tp->tf_rbx; 2197 mcp->mc_rcx = tp->tf_rcx; 2198 mcp->mc_rflags = tp->tf_rflags; 2199 if (flags & GET_MC_CLEAR_RET) { 2200 mcp->mc_rax = 0; 2201 mcp->mc_rdx = 0; 2202 mcp->mc_rflags &= ~PSL_C; 2203 } else { 2204 mcp->mc_rax = tp->tf_rax; 2205 mcp->mc_rdx = tp->tf_rdx; 2206 } 2207 mcp->mc_rip = tp->tf_rip; 2208 mcp->mc_cs = tp->tf_cs; 2209 mcp->mc_rsp = tp->tf_rsp; 2210 mcp->mc_ss = tp->tf_ss; 2211 mcp->mc_ds = tp->tf_ds; 2212 mcp->mc_es = tp->tf_es; 2213 mcp->mc_fs = tp->tf_fs; 2214 mcp->mc_gs = tp->tf_gs; 2215 mcp->mc_flags = tp->tf_flags; 2216 mcp->mc_len = sizeof(*mcp); 2217 get_fpcontext(td, mcp, NULL, 0); 2218 mcp->mc_fsbase = pcb->pcb_fsbase; 2219 mcp->mc_gsbase = pcb->pcb_gsbase; 2220 mcp->mc_xfpustate = 0; 2221 mcp->mc_xfpustate_len = 0; 2222 bzero(mcp->mc_spare, sizeof(mcp->mc_spare)); 2223 return (0); 2224 } 2225 2226 /* 2227 * Set machine context. 2228 * 2229 * However, we don't set any but the user modifiable flags, and we won't 2230 * touch the cs selector. 2231 */ 2232 int 2233 set_mcontext(struct thread *td, const mcontext_t *mcp) 2234 { 2235 struct pcb *pcb; 2236 struct trapframe *tp; 2237 char *xfpustate; 2238 long rflags; 2239 int ret; 2240 2241 pcb = td->td_pcb; 2242 tp = td->td_frame; 2243 if (mcp->mc_len != sizeof(*mcp) || 2244 (mcp->mc_flags & ~_MC_FLAG_MASK) != 0) 2245 return (EINVAL); 2246 rflags = (mcp->mc_rflags & PSL_USERCHANGE) | 2247 (tp->tf_rflags & ~PSL_USERCHANGE); 2248 if (mcp->mc_flags & _MC_HASFPXSTATE) { 2249 if (mcp->mc_xfpustate_len > cpu_max_ext_state_size - 2250 sizeof(struct savefpu)) 2251 return (EINVAL); 2252 xfpustate = __builtin_alloca(mcp->mc_xfpustate_len); 2253 ret = copyin((void *)mcp->mc_xfpustate, xfpustate, 2254 mcp->mc_xfpustate_len); 2255 if (ret != 0) 2256 return (ret); 2257 } else 2258 xfpustate = NULL; 2259 ret = set_fpcontext(td, mcp, xfpustate, mcp->mc_xfpustate_len); 2260 if (ret != 0) 2261 return (ret); 2262 tp->tf_r15 = mcp->mc_r15; 2263 tp->tf_r14 = mcp->mc_r14; 2264 tp->tf_r13 = mcp->mc_r13; 2265 tp->tf_r12 = mcp->mc_r12; 2266 tp->tf_r11 = mcp->mc_r11; 2267 tp->tf_r10 = mcp->mc_r10; 2268 tp->tf_r9 = mcp->mc_r9; 2269 tp->tf_r8 = mcp->mc_r8; 2270 tp->tf_rdi = mcp->mc_rdi; 2271 tp->tf_rsi = mcp->mc_rsi; 2272 tp->tf_rbp = mcp->mc_rbp; 2273 tp->tf_rbx = mcp->mc_rbx; 2274 tp->tf_rdx = mcp->mc_rdx; 2275 tp->tf_rcx = mcp->mc_rcx; 2276 tp->tf_rax = mcp->mc_rax; 2277 tp->tf_rip = mcp->mc_rip; 2278 tp->tf_rflags = rflags; 2279 tp->tf_rsp = mcp->mc_rsp; 2280 tp->tf_ss = mcp->mc_ss; 2281 tp->tf_flags = mcp->mc_flags; 2282 if (tp->tf_flags & TF_HASSEGS) { 2283 tp->tf_ds = mcp->mc_ds; 2284 tp->tf_es = mcp->mc_es; 2285 tp->tf_fs = mcp->mc_fs; 2286 tp->tf_gs = mcp->mc_gs; 2287 } 2288 if (mcp->mc_flags & _MC_HASBASES) { 2289 pcb->pcb_fsbase = mcp->mc_fsbase; 2290 pcb->pcb_gsbase = mcp->mc_gsbase; 2291 } 2292 set_pcb_flags(pcb, PCB_FULL_IRET); 2293 return (0); 2294 } 2295 2296 static void 2297 get_fpcontext(struct thread *td, mcontext_t *mcp, char *xfpusave, 2298 size_t xfpusave_len) 2299 { 2300 size_t max_len, len; 2301 2302 mcp->mc_ownedfp = fpugetregs(td); 2303 bcopy(get_pcb_user_save_td(td), &mcp->mc_fpstate[0], 2304 sizeof(mcp->mc_fpstate)); 2305 mcp->mc_fpformat = fpuformat(); 2306 if (!use_xsave || xfpusave_len == 0) 2307 return; 2308 max_len = cpu_max_ext_state_size - sizeof(struct savefpu); 2309 len = xfpusave_len; 2310 if (len > max_len) { 2311 len = max_len; 2312 bzero(xfpusave + max_len, len - max_len); 2313 } 2314 mcp->mc_flags |= _MC_HASFPXSTATE; 2315 mcp->mc_xfpustate_len = len; 2316 bcopy(get_pcb_user_save_td(td) + 1, xfpusave, len); 2317 } 2318 2319 static int 2320 set_fpcontext(struct thread *td, const mcontext_t *mcp, char *xfpustate, 2321 size_t xfpustate_len) 2322 { 2323 struct savefpu *fpstate; 2324 int error; 2325 2326 if (mcp->mc_fpformat == _MC_FPFMT_NODEV) 2327 return (0); 2328 else if (mcp->mc_fpformat != _MC_FPFMT_XMM) 2329 return (EINVAL); 2330 else if (mcp->mc_ownedfp == _MC_FPOWNED_NONE) { 2331 /* We don't care what state is left in the FPU or PCB. */ 2332 fpstate_drop(td); 2333 error = 0; 2334 } else if (mcp->mc_ownedfp == _MC_FPOWNED_FPU || 2335 mcp->mc_ownedfp == _MC_FPOWNED_PCB) { 2336 fpstate = (struct savefpu *)&mcp->mc_fpstate; 2337 fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask; 2338 error = fpusetregs(td, fpstate, xfpustate, xfpustate_len); 2339 } else 2340 return (EINVAL); 2341 return (error); 2342 } 2343 2344 void 2345 fpstate_drop(struct thread *td) 2346 { 2347 2348 KASSERT(PCB_USER_FPU(td->td_pcb), ("fpstate_drop: kernel-owned fpu")); 2349 critical_enter(); 2350 if (PCPU_GET(fpcurthread) == td) 2351 fpudrop(); 2352 /* 2353 * XXX force a full drop of the fpu. The above only drops it if we 2354 * owned it. 2355 * 2356 * XXX I don't much like fpugetuserregs()'s semantics of doing a full 2357 * drop. Dropping only to the pcb matches fnsave's behaviour. 2358 * We only need to drop to !PCB_INITDONE in sendsig(). But 2359 * sendsig() is the only caller of fpugetuserregs()... perhaps we just 2360 * have too many layers. 2361 */ 2362 clear_pcb_flags(curthread->td_pcb, 2363 PCB_FPUINITDONE | PCB_USERFPUINITDONE); 2364 critical_exit(); 2365 } 2366 2367 int 2368 fill_dbregs(struct thread *td, struct dbreg *dbregs) 2369 { 2370 struct pcb *pcb; 2371 2372 if (td == NULL) { 2373 dbregs->dr[0] = rdr0(); 2374 dbregs->dr[1] = rdr1(); 2375 dbregs->dr[2] = rdr2(); 2376 dbregs->dr[3] = rdr3(); 2377 dbregs->dr[6] = rdr6(); 2378 dbregs->dr[7] = rdr7(); 2379 } else { 2380 pcb = td->td_pcb; 2381 dbregs->dr[0] = pcb->pcb_dr0; 2382 dbregs->dr[1] = pcb->pcb_dr1; 2383 dbregs->dr[2] = pcb->pcb_dr2; 2384 dbregs->dr[3] = pcb->pcb_dr3; 2385 dbregs->dr[6] = pcb->pcb_dr6; 2386 dbregs->dr[7] = pcb->pcb_dr7; 2387 } 2388 dbregs->dr[4] = 0; 2389 dbregs->dr[5] = 0; 2390 dbregs->dr[8] = 0; 2391 dbregs->dr[9] = 0; 2392 dbregs->dr[10] = 0; 2393 dbregs->dr[11] = 0; 2394 dbregs->dr[12] = 0; 2395 dbregs->dr[13] = 0; 2396 dbregs->dr[14] = 0; 2397 dbregs->dr[15] = 0; 2398 return (0); 2399 } 2400 2401 int 2402 set_dbregs(struct thread *td, struct dbreg *dbregs) 2403 { 2404 struct pcb *pcb; 2405 int i; 2406 2407 if (td == NULL) { 2408 load_dr0(dbregs->dr[0]); 2409 load_dr1(dbregs->dr[1]); 2410 load_dr2(dbregs->dr[2]); 2411 load_dr3(dbregs->dr[3]); 2412 load_dr6(dbregs->dr[6]); 2413 load_dr7(dbregs->dr[7]); 2414 } else { 2415 /* 2416 * Don't let an illegal value for dr7 get set. Specifically, 2417 * check for undefined settings. Setting these bit patterns 2418 * result in undefined behaviour and can lead to an unexpected 2419 * TRCTRAP or a general protection fault right here. 2420 * Upper bits of dr6 and dr7 must not be set 2421 */ 2422 for (i = 0; i < 4; i++) { 2423 if (DBREG_DR7_ACCESS(dbregs->dr[7], i) == 0x02) 2424 return (EINVAL); 2425 if (td->td_frame->tf_cs == _ucode32sel && 2426 DBREG_DR7_LEN(dbregs->dr[7], i) == DBREG_DR7_LEN_8) 2427 return (EINVAL); 2428 } 2429 if ((dbregs->dr[6] & 0xffffffff00000000ul) != 0 || 2430 (dbregs->dr[7] & 0xffffffff00000000ul) != 0) 2431 return (EINVAL); 2432 2433 pcb = td->td_pcb; 2434 2435 /* 2436 * Don't let a process set a breakpoint that is not within the 2437 * process's address space. If a process could do this, it 2438 * could halt the system by setting a breakpoint in the kernel 2439 * (if ddb was enabled). Thus, we need to check to make sure 2440 * that no breakpoints are being enabled for addresses outside 2441 * process's address space. 2442 * 2443 * XXX - what about when the watched area of the user's 2444 * address space is written into from within the kernel 2445 * ... wouldn't that still cause a breakpoint to be generated 2446 * from within kernel mode? 2447 */ 2448 2449 if (DBREG_DR7_ENABLED(dbregs->dr[7], 0)) { 2450 /* dr0 is enabled */ 2451 if (dbregs->dr[0] >= VM_MAXUSER_ADDRESS) 2452 return (EINVAL); 2453 } 2454 if (DBREG_DR7_ENABLED(dbregs->dr[7], 1)) { 2455 /* dr1 is enabled */ 2456 if (dbregs->dr[1] >= VM_MAXUSER_ADDRESS) 2457 return (EINVAL); 2458 } 2459 if (DBREG_DR7_ENABLED(dbregs->dr[7], 2)) { 2460 /* dr2 is enabled */ 2461 if (dbregs->dr[2] >= VM_MAXUSER_ADDRESS) 2462 return (EINVAL); 2463 } 2464 if (DBREG_DR7_ENABLED(dbregs->dr[7], 3)) { 2465 /* dr3 is enabled */ 2466 if (dbregs->dr[3] >= VM_MAXUSER_ADDRESS) 2467 return (EINVAL); 2468 } 2469 2470 pcb->pcb_dr0 = dbregs->dr[0]; 2471 pcb->pcb_dr1 = dbregs->dr[1]; 2472 pcb->pcb_dr2 = dbregs->dr[2]; 2473 pcb->pcb_dr3 = dbregs->dr[3]; 2474 pcb->pcb_dr6 = dbregs->dr[6]; 2475 pcb->pcb_dr7 = dbregs->dr[7]; 2476 2477 set_pcb_flags(pcb, PCB_DBREGS); 2478 } 2479 2480 return (0); 2481 } 2482 2483 void 2484 reset_dbregs(void) 2485 { 2486 2487 load_dr7(0); /* Turn off the control bits first */ 2488 load_dr0(0); 2489 load_dr1(0); 2490 load_dr2(0); 2491 load_dr3(0); 2492 load_dr6(0); 2493 } 2494 2495 /* 2496 * Return > 0 if a hardware breakpoint has been hit, and the 2497 * breakpoint was in user space. Return 0, otherwise. 2498 */ 2499 int 2500 user_dbreg_trap(void) 2501 { 2502 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */ 2503 u_int64_t bp; /* breakpoint bits extracted from dr6 */ 2504 int nbp; /* number of breakpoints that triggered */ 2505 caddr_t addr[4]; /* breakpoint addresses */ 2506 int i; 2507 2508 dr7 = rdr7(); 2509 if ((dr7 & 0x000000ff) == 0) { 2510 /* 2511 * all GE and LE bits in the dr7 register are zero, 2512 * thus the trap couldn't have been caused by the 2513 * hardware debug registers 2514 */ 2515 return 0; 2516 } 2517 2518 nbp = 0; 2519 dr6 = rdr6(); 2520 bp = dr6 & 0x0000000f; 2521 2522 if (!bp) { 2523 /* 2524 * None of the breakpoint bits are set meaning this 2525 * trap was not caused by any of the debug registers 2526 */ 2527 return 0; 2528 } 2529 2530 /* 2531 * at least one of the breakpoints were hit, check to see 2532 * which ones and if any of them are user space addresses 2533 */ 2534 2535 if (bp & 0x01) { 2536 addr[nbp++] = (caddr_t)rdr0(); 2537 } 2538 if (bp & 0x02) { 2539 addr[nbp++] = (caddr_t)rdr1(); 2540 } 2541 if (bp & 0x04) { 2542 addr[nbp++] = (caddr_t)rdr2(); 2543 } 2544 if (bp & 0x08) { 2545 addr[nbp++] = (caddr_t)rdr3(); 2546 } 2547 2548 for (i = 0; i < nbp; i++) { 2549 if (addr[i] < (caddr_t)VM_MAXUSER_ADDRESS) { 2550 /* 2551 * addr[i] is in user space 2552 */ 2553 return nbp; 2554 } 2555 } 2556 2557 /* 2558 * None of the breakpoints are in user space. 2559 */ 2560 return 0; 2561 } 2562 2563 #ifdef KDB 2564 2565 /* 2566 * Provide inb() and outb() as functions. They are normally only available as 2567 * inline functions, thus cannot be called from the debugger. 2568 */ 2569 2570 /* silence compiler warnings */ 2571 u_char inb_(u_short); 2572 void outb_(u_short, u_char); 2573 2574 u_char 2575 inb_(u_short port) 2576 { 2577 return inb(port); 2578 } 2579 2580 void 2581 outb_(u_short port, u_char data) 2582 { 2583 outb(port, data); 2584 } 2585 2586 #endif /* KDB */
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