1 /*-
2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2003, by Peter Wemm
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: releng/11.0/sys/amd64/amd64/mp_machdep.c 297857 2016-04-12 13:30:39Z avg $");
29
30 #include "opt_cpu.h"
31 #include "opt_ddb.h"
32 #include "opt_kstack_pages.h"
33 #include "opt_sched.h"
34 #include "opt_smp.h"
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39 #include <sys/cpuset.h>
40 #ifdef GPROF
41 #include <sys/gmon.h>
42 #endif
43 #include <sys/kernel.h>
44 #include <sys/ktr.h>
45 #include <sys/lock.h>
46 #include <sys/malloc.h>
47 #include <sys/memrange.h>
48 #include <sys/mutex.h>
49 #include <sys/pcpu.h>
50 #include <sys/proc.h>
51 #include <sys/sched.h>
52 #include <sys/smp.h>
53 #include <sys/sysctl.h>
54
55 #include <vm/vm.h>
56 #include <vm/vm_param.h>
57 #include <vm/pmap.h>
58 #include <vm/vm_kern.h>
59 #include <vm/vm_extern.h>
60
61 #include <x86/apicreg.h>
62 #include <machine/clock.h>
63 #include <machine/cputypes.h>
64 #include <machine/cpufunc.h>
65 #include <x86/mca.h>
66 #include <machine/md_var.h>
67 #include <machine/pcb.h>
68 #include <machine/psl.h>
69 #include <machine/smp.h>
70 #include <machine/specialreg.h>
71 #include <machine/tss.h>
72 #include <machine/cpu.h>
73 #include <x86/init.h>
74
75 #define WARMBOOT_TARGET 0
76 #define WARMBOOT_OFF (KERNBASE + 0x0467)
77 #define WARMBOOT_SEG (KERNBASE + 0x0469)
78
79 #define CMOS_REG (0x70)
80 #define CMOS_DATA (0x71)
81 #define BIOS_RESET (0x0f)
82 #define BIOS_WARM (0x0a)
83
84 extern struct pcpu __pcpu[];
85
86 /* Temporary variables for init_secondary() */
87 char *doublefault_stack;
88 char *nmi_stack;
89
90 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
91
92 /*
93 * Local data and functions.
94 */
95
96 static int start_ap(int apic_id);
97
98 static u_int bootMP_size;
99 static u_int boot_address;
100
101 /*
102 * Calculate usable address in base memory for AP trampoline code.
103 */
104 u_int
105 mp_bootaddress(u_int basemem)
106 {
107
108 bootMP_size = mptramp_end - mptramp_start;
109 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
110 if (((basemem * 1024) - boot_address) < bootMP_size)
111 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
112 /* 3 levels of page table pages */
113 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
114
115 return mptramp_pagetables;
116 }
117
118 /*
119 * Initialize the IPI handlers and start up the AP's.
120 */
121 void
122 cpu_mp_start(void)
123 {
124 int i;
125
126 /* Initialize the logical ID to APIC ID table. */
127 for (i = 0; i < MAXCPU; i++) {
128 cpu_apic_ids[i] = -1;
129 cpu_ipi_pending[i] = 0;
130 }
131
132 /* Install an inter-CPU IPI for TLB invalidation */
133 if (pmap_pcid_enabled) {
134 if (invpcid_works) {
135 setidt(IPI_INVLTLB, IDTVEC(invltlb_invpcid),
136 SDT_SYSIGT, SEL_KPL, 0);
137 } else {
138 setidt(IPI_INVLTLB, IDTVEC(invltlb_pcid), SDT_SYSIGT,
139 SEL_KPL, 0);
140 }
141 } else {
142 setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0);
143 }
144 setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0);
145 setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0);
146
147 /* Install an inter-CPU IPI for cache invalidation. */
148 setidt(IPI_INVLCACHE, IDTVEC(invlcache), SDT_SYSIGT, SEL_KPL, 0);
149
150 /* Install an inter-CPU IPI for all-CPU rendezvous */
151 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
152
153 /* Install generic inter-CPU IPI handler */
154 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
155 SDT_SYSIGT, SEL_KPL, 0);
156
157 /* Install an inter-CPU IPI for CPU stop/restart */
158 setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0);
159
160 /* Install an inter-CPU IPI for CPU suspend/resume */
161 setidt(IPI_SUSPEND, IDTVEC(cpususpend), SDT_SYSIGT, SEL_KPL, 0);
162
163 /* Set boot_cpu_id if needed. */
164 if (boot_cpu_id == -1) {
165 boot_cpu_id = PCPU_GET(apic_id);
166 cpu_info[boot_cpu_id].cpu_bsp = 1;
167 } else
168 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
169 ("BSP's APIC ID doesn't match boot_cpu_id"));
170
171 /* Probe logical/physical core configuration. */
172 topo_probe();
173
174 assign_cpu_ids();
175
176 /* Start each Application Processor */
177 init_ops.start_all_aps();
178
179 set_interrupt_apic_ids();
180 }
181
182
183 /*
184 * AP CPU's call this to initialize themselves.
185 */
186 void
187 init_secondary(void)
188 {
189 struct pcpu *pc;
190 struct nmi_pcpu *np;
191 u_int64_t msr, cr0;
192 int cpu, gsel_tss, x;
193 struct region_descriptor ap_gdt;
194
195 /* Set by the startup code for us to use */
196 cpu = bootAP;
197
198 /* Init tss */
199 common_tss[cpu] = common_tss[0];
200 common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */
201 common_tss[cpu].tss_iobase = sizeof(struct amd64tss) +
202 IOPERM_BITMAP_SIZE;
203 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
204
205 /* The NMI stack runs on IST2. */
206 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
207 common_tss[cpu].tss_ist2 = (long) np;
208
209 /* Prepare private GDT */
210 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu];
211 for (x = 0; x < NGDT; x++) {
212 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) &&
213 x != GUSERLDT_SEL && x != (GUSERLDT_SEL + 1))
214 ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]);
215 }
216 ssdtosyssd(&gdt_segs[GPROC0_SEL],
217 (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]);
218 ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
219 ap_gdt.rd_base = (long) &gdt[NGDT * cpu];
220 lgdt(&ap_gdt); /* does magic intra-segment return */
221
222 /* Get per-cpu data */
223 pc = &__pcpu[cpu];
224
225 /* prime data page for it to use */
226 pcpu_init(pc, cpu, sizeof(struct pcpu));
227 dpcpu_init(dpcpu, cpu);
228 pc->pc_apic_id = cpu_apic_ids[cpu];
229 pc->pc_prvspace = pc;
230 pc->pc_curthread = 0;
231 pc->pc_tssp = &common_tss[cpu];
232 pc->pc_commontssp = &common_tss[cpu];
233 pc->pc_rsp0 = 0;
234 pc->pc_tss = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
235 GPROC0_SEL];
236 pc->pc_fs32p = &gdt[NGDT * cpu + GUFS32_SEL];
237 pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL];
238 pc->pc_ldt = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
239 GUSERLDT_SEL];
240 pc->pc_curpmap = kernel_pmap;
241 pc->pc_pcid_gen = 1;
242 pc->pc_pcid_next = PMAP_PCID_KERN + 1;
243
244 /* Save the per-cpu pointer for use by the NMI handler. */
245 np->np_pcpu = (register_t) pc;
246
247 wrmsr(MSR_FSBASE, 0); /* User value */
248 wrmsr(MSR_GSBASE, (u_int64_t)pc);
249 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */
250 fix_cpuid();
251
252 lidt(&r_idt);
253
254 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
255 ltr(gsel_tss);
256
257 /*
258 * Set to a known state:
259 * Set by mpboot.s: CR0_PG, CR0_PE
260 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
261 */
262 cr0 = rcr0();
263 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
264 load_cr0(cr0);
265
266 /* Set up the fast syscall stuff */
267 msr = rdmsr(MSR_EFER) | EFER_SCE;
268 wrmsr(MSR_EFER, msr);
269 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
270 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
271 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
272 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
273 wrmsr(MSR_STAR, msr);
274 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
275
276 /* signal our startup to the BSP. */
277 mp_naps++;
278
279 /* Spin until the BSP releases the AP's. */
280 while (atomic_load_acq_int(&aps_ready) == 0)
281 ia32_pause();
282
283 init_secondary_tail();
284 }
285
286 /*******************************************************************
287 * local functions and data
288 */
289
290 /*
291 * start each AP in our list
292 */
293 int
294 native_start_all_aps(void)
295 {
296 vm_offset_t va = boot_address + KERNBASE;
297 u_int64_t *pt4, *pt3, *pt2;
298 u_int32_t mpbioswarmvec;
299 int apic_id, cpu, i;
300 u_char mpbiosreason;
301
302 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
303
304 /* install the AP 1st level boot code */
305 pmap_kenter(va, boot_address);
306 pmap_invalidate_page(kernel_pmap, va);
307 bcopy(mptramp_start, (void *)va, bootMP_size);
308
309 /* Locate the page tables, they'll be below the trampoline */
310 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
311 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
312 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
313
314 /* Create the initial 1GB replicated page tables */
315 for (i = 0; i < 512; i++) {
316 /* Each slot of the level 4 pages points to the same level 3 page */
317 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
318 pt4[i] |= PG_V | PG_RW | PG_U;
319
320 /* Each slot of the level 3 pages points to the same level 2 page */
321 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
322 pt3[i] |= PG_V | PG_RW | PG_U;
323
324 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
325 pt2[i] = i * (2 * 1024 * 1024);
326 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
327 }
328
329 /* save the current value of the warm-start vector */
330 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
331 outb(CMOS_REG, BIOS_RESET);
332 mpbiosreason = inb(CMOS_DATA);
333
334 /* setup a vector to our boot code */
335 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
336 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
337 outb(CMOS_REG, BIOS_RESET);
338 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
339
340 /* start each AP */
341 for (cpu = 1; cpu < mp_ncpus; cpu++) {
342 apic_id = cpu_apic_ids[cpu];
343
344 /* allocate and set up an idle stack data page */
345 bootstacks[cpu] = (void *)kmem_malloc(kernel_arena,
346 kstack_pages * PAGE_SIZE, M_WAITOK | M_ZERO);
347 doublefault_stack = (char *)kmem_malloc(kernel_arena,
348 PAGE_SIZE, M_WAITOK | M_ZERO);
349 nmi_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE,
350 M_WAITOK | M_ZERO);
351 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
352 M_WAITOK | M_ZERO);
353
354 bootSTK = (char *)bootstacks[cpu] + kstack_pages * PAGE_SIZE - 8;
355 bootAP = cpu;
356
357 /* attempt to start the Application Processor */
358 if (!start_ap(apic_id)) {
359 /* restore the warmstart vector */
360 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
361 panic("AP #%d (PHY# %d) failed!", cpu, apic_id);
362 }
363
364 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */
365 }
366
367 /* restore the warmstart vector */
368 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
369
370 outb(CMOS_REG, BIOS_RESET);
371 outb(CMOS_DATA, mpbiosreason);
372
373 /* number of APs actually started */
374 return mp_naps;
375 }
376
377
378 /*
379 * This function starts the AP (application processor) identified
380 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
381 * to accomplish this. This is necessary because of the nuances
382 * of the different hardware we might encounter. It isn't pretty,
383 * but it seems to work.
384 */
385 static int
386 start_ap(int apic_id)
387 {
388 int vector, ms;
389 int cpus;
390
391 /* calculate the vector */
392 vector = (boot_address >> 12) & 0xff;
393
394 /* used as a watchpoint to signal AP startup */
395 cpus = mp_naps;
396
397 ipi_startup(apic_id, vector);
398
399 /* Wait up to 5 seconds for it to start. */
400 for (ms = 0; ms < 5000; ms++) {
401 if (mp_naps > cpus)
402 return 1; /* return SUCCESS */
403 DELAY(1000);
404 }
405 return 0; /* return FAILURE */
406 }
407
408 void
409 invltlb_invpcid_handler(void)
410 {
411 struct invpcid_descr d;
412
413 #ifdef COUNT_XINVLTLB_HITS
414 xhits_gbl[PCPU_GET(cpuid)]++;
415 #endif /* COUNT_XINVLTLB_HITS */
416 #ifdef COUNT_IPIS
417 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
418 #endif /* COUNT_IPIS */
419
420 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
421 d.pad = 0;
422 d.addr = 0;
423 invpcid(&d, smp_tlb_pmap == kernel_pmap ? INVPCID_CTXGLOB :
424 INVPCID_CTX);
425 atomic_add_int(&smp_tlb_wait, 1);
426 }
427
428 void
429 invltlb_pcid_handler(void)
430 {
431 #ifdef COUNT_XINVLTLB_HITS
432 xhits_gbl[PCPU_GET(cpuid)]++;
433 #endif /* COUNT_XINVLTLB_HITS */
434 #ifdef COUNT_IPIS
435 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
436 #endif /* COUNT_IPIS */
437
438 if (smp_tlb_pmap == kernel_pmap) {
439 invltlb_glob();
440 } else {
441 /*
442 * The current pmap might not be equal to
443 * smp_tlb_pmap. The clearing of the pm_gen in
444 * pmap_invalidate_all() takes care of TLB
445 * invalidation when switching to the pmap on this
446 * CPU.
447 */
448 if (PCPU_GET(curpmap) == smp_tlb_pmap) {
449 load_cr3(smp_tlb_pmap->pm_cr3 |
450 smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid);
451 }
452 }
453 atomic_add_int(&smp_tlb_wait, 1);
454 }
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