1 /*-
2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2003, by Peter Wemm
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: releng/11.1/sys/amd64/amd64/mp_machdep.c 333371 2018-05-08 17:12:10Z gordon $");
29
30 #include "opt_cpu.h"
31 #include "opt_ddb.h"
32 #include "opt_kstack_pages.h"
33 #include "opt_sched.h"
34 #include "opt_smp.h"
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39 #include <sys/cpuset.h>
40 #ifdef GPROF
41 #include <sys/gmon.h>
42 #endif
43 #include <sys/kernel.h>
44 #include <sys/ktr.h>
45 #include <sys/lock.h>
46 #include <sys/malloc.h>
47 #include <sys/memrange.h>
48 #include <sys/mutex.h>
49 #include <sys/pcpu.h>
50 #include <sys/proc.h>
51 #include <sys/sched.h>
52 #include <sys/smp.h>
53 #include <sys/sysctl.h>
54
55 #include <vm/vm.h>
56 #include <vm/vm_param.h>
57 #include <vm/pmap.h>
58 #include <vm/vm_kern.h>
59 #include <vm/vm_extern.h>
60
61 #include <x86/apicreg.h>
62 #include <machine/clock.h>
63 #include <machine/cputypes.h>
64 #include <machine/cpufunc.h>
65 #include <x86/mca.h>
66 #include <machine/md_var.h>
67 #include <machine/pcb.h>
68 #include <machine/psl.h>
69 #include <machine/smp.h>
70 #include <machine/specialreg.h>
71 #include <machine/tss.h>
72 #include <machine/cpu.h>
73 #include <x86/init.h>
74
75 #define WARMBOOT_TARGET 0
76 #define WARMBOOT_OFF (KERNBASE + 0x0467)
77 #define WARMBOOT_SEG (KERNBASE + 0x0469)
78
79 #define CMOS_REG (0x70)
80 #define CMOS_DATA (0x71)
81 #define BIOS_RESET (0x0f)
82 #define BIOS_WARM (0x0a)
83
84 extern struct pcpu __pcpu[];
85
86 /* Temporary variables for init_secondary() */
87 char *doublefault_stack;
88 char *mce_stack;
89 char *nmi_stack;
90 char *dbg_stack;
91
92 /*
93 * Local data and functions.
94 */
95
96 static int start_ap(int apic_id);
97
98 static u_int bootMP_size;
99 static u_int boot_address;
100
101 /*
102 * Calculate usable address in base memory for AP trampoline code.
103 */
104 u_int
105 mp_bootaddress(u_int basemem)
106 {
107
108 bootMP_size = mptramp_end - mptramp_start;
109 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
110 if (((basemem * 1024) - boot_address) < bootMP_size)
111 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
112 /* 3 levels of page table pages */
113 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
114
115 return mptramp_pagetables;
116 }
117
118 /*
119 * Initialize the IPI handlers and start up the AP's.
120 */
121 void
122 cpu_mp_start(void)
123 {
124 int i;
125
126 /* Initialize the logical ID to APIC ID table. */
127 for (i = 0; i < MAXCPU; i++) {
128 cpu_apic_ids[i] = -1;
129 cpu_ipi_pending[i] = 0;
130 }
131
132 /* Install an inter-CPU IPI for TLB invalidation */
133 if (pmap_pcid_enabled) {
134 if (invpcid_works) {
135 setidt(IPI_INVLTLB, pti ?
136 IDTVEC(invltlb_invpcid_pti_pti) :
137 IDTVEC(invltlb_invpcid_nopti), SDT_SYSIGT,
138 SEL_KPL, 0);
139 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_invpcid_pti) :
140 IDTVEC(invlpg_invpcid), SDT_SYSIGT, SEL_KPL, 0);
141 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_invpcid_pti) :
142 IDTVEC(invlrng_invpcid), SDT_SYSIGT, SEL_KPL, 0);
143 } else {
144 setidt(IPI_INVLTLB, pti ? IDTVEC(invltlb_pcid_pti) :
145 IDTVEC(invltlb_pcid), SDT_SYSIGT, SEL_KPL, 0);
146 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_pcid_pti) :
147 IDTVEC(invlpg_pcid), SDT_SYSIGT, SEL_KPL, 0);
148 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_pcid_pti) :
149 IDTVEC(invlrng_pcid), SDT_SYSIGT, SEL_KPL, 0);
150 }
151 } else {
152 setidt(IPI_INVLTLB, pti ? IDTVEC(invltlb_pti) : IDTVEC(invltlb),
153 SDT_SYSIGT, SEL_KPL, 0);
154 setidt(IPI_INVLPG, pti ? IDTVEC(invlpg_pti) : IDTVEC(invlpg),
155 SDT_SYSIGT, SEL_KPL, 0);
156 setidt(IPI_INVLRNG, pti ? IDTVEC(invlrng_pti) : IDTVEC(invlrng),
157 SDT_SYSIGT, SEL_KPL, 0);
158 }
159
160 /* Install an inter-CPU IPI for cache invalidation. */
161 setidt(IPI_INVLCACHE, pti ? IDTVEC(invlcache_pti) : IDTVEC(invlcache),
162 SDT_SYSIGT, SEL_KPL, 0);
163
164 /* Install an inter-CPU IPI for all-CPU rendezvous */
165 setidt(IPI_RENDEZVOUS, pti ? IDTVEC(rendezvous_pti) :
166 IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
167
168 /* Install generic inter-CPU IPI handler */
169 setidt(IPI_BITMAP_VECTOR, pti ? IDTVEC(ipi_intr_bitmap_handler_pti) :
170 IDTVEC(ipi_intr_bitmap_handler), SDT_SYSIGT, SEL_KPL, 0);
171
172 /* Install an inter-CPU IPI for CPU stop/restart */
173 setidt(IPI_STOP, pti ? IDTVEC(cpustop_pti) : IDTVEC(cpustop),
174 SDT_SYSIGT, SEL_KPL, 0);
175
176 /* Install an inter-CPU IPI for CPU suspend/resume */
177 setidt(IPI_SUSPEND, pti ? IDTVEC(cpususpend_pti) : IDTVEC(cpususpend),
178 SDT_SYSIGT, SEL_KPL, 0);
179
180 /* Set boot_cpu_id if needed. */
181 if (boot_cpu_id == -1) {
182 boot_cpu_id = PCPU_GET(apic_id);
183 cpu_info[boot_cpu_id].cpu_bsp = 1;
184 } else
185 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
186 ("BSP's APIC ID doesn't match boot_cpu_id"));
187
188 /* Probe logical/physical core configuration. */
189 topo_probe();
190
191 assign_cpu_ids();
192
193 /* Start each Application Processor */
194 init_ops.start_all_aps();
195
196 set_interrupt_apic_ids();
197 }
198
199
200 /*
201 * AP CPU's call this to initialize themselves.
202 */
203 void
204 init_secondary(void)
205 {
206 struct pcpu *pc;
207 struct nmi_pcpu *np;
208 u_int64_t cr0;
209 int cpu, gsel_tss, x;
210 struct region_descriptor ap_gdt;
211
212 /* Set by the startup code for us to use */
213 cpu = bootAP;
214
215 /* Init tss */
216 common_tss[cpu] = common_tss[0];
217 common_tss[cpu].tss_iobase = sizeof(struct amd64tss) +
218 IOPERM_BITMAP_SIZE;
219 common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
220
221 /* The NMI stack runs on IST2. */
222 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
223 common_tss[cpu].tss_ist2 = (long) np;
224
225 /* The MC# stack runs on IST3. */
226 np = ((struct nmi_pcpu *) &mce_stack[PAGE_SIZE]) - 1;
227 common_tss[cpu].tss_ist3 = (long) np;
228
229 /* The DB# stack runs on IST4. */
230 np = ((struct nmi_pcpu *) &dbg_stack[PAGE_SIZE]) - 1;
231 common_tss[cpu].tss_ist4 = (long) np;
232
233 /* Prepare private GDT */
234 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu];
235 for (x = 0; x < NGDT; x++) {
236 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) &&
237 x != GUSERLDT_SEL && x != (GUSERLDT_SEL + 1))
238 ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]);
239 }
240 ssdtosyssd(&gdt_segs[GPROC0_SEL],
241 (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]);
242 ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
243 ap_gdt.rd_base = (long) &gdt[NGDT * cpu];
244 lgdt(&ap_gdt); /* does magic intra-segment return */
245
246 /* Get per-cpu data */
247 pc = &__pcpu[cpu];
248
249 /* prime data page for it to use */
250 pcpu_init(pc, cpu, sizeof(struct pcpu));
251 dpcpu_init(dpcpu, cpu);
252 pc->pc_apic_id = cpu_apic_ids[cpu];
253 pc->pc_prvspace = pc;
254 pc->pc_curthread = 0;
255 pc->pc_tssp = &common_tss[cpu];
256 pc->pc_commontssp = &common_tss[cpu];
257 pc->pc_rsp0 = 0;
258 pc->pc_tss = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
259 GPROC0_SEL];
260 pc->pc_fs32p = &gdt[NGDT * cpu + GUFS32_SEL];
261 pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL];
262 pc->pc_ldt = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
263 GUSERLDT_SEL];
264 pc->pc_curpmap = kernel_pmap;
265 pc->pc_pcid_gen = 1;
266 pc->pc_pcid_next = PMAP_PCID_KERN + 1;
267 common_tss[cpu].tss_rsp0 = pti ? ((vm_offset_t)&pc->pc_pti_stack +
268 PC_PTI_STACK_SZ * sizeof(uint64_t)) & ~0xful : 0;
269
270 /* Save the per-cpu pointer for use by the NMI handler. */
271 np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
272 np->np_pcpu = (register_t) pc;
273
274 /* Save the per-cpu pointer for use by the MC# handler. */
275 np = ((struct nmi_pcpu *) &mce_stack[PAGE_SIZE]) - 1;
276 np->np_pcpu = (register_t) pc;
277
278 /* Save the per-cpu pointer for use by the DB# handler. */
279 np = ((struct nmi_pcpu *) &dbg_stack[PAGE_SIZE]) - 1;
280 np->np_pcpu = (register_t) pc;
281
282 wrmsr(MSR_FSBASE, 0); /* User value */
283 wrmsr(MSR_GSBASE, (u_int64_t)pc);
284 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */
285 fix_cpuid();
286
287 lidt(&r_idt);
288
289 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
290 ltr(gsel_tss);
291
292 /*
293 * Set to a known state:
294 * Set by mpboot.s: CR0_PG, CR0_PE
295 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
296 */
297 cr0 = rcr0();
298 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
299 load_cr0(cr0);
300
301 amd64_conf_fast_syscall();
302
303 /* signal our startup to the BSP. */
304 mp_naps++;
305
306 /* Spin until the BSP releases the AP's. */
307 while (atomic_load_acq_int(&aps_ready) == 0)
308 ia32_pause();
309
310 init_secondary_tail();
311 }
312
313 /*******************************************************************
314 * local functions and data
315 */
316
317 /*
318 * start each AP in our list
319 */
320 int
321 native_start_all_aps(void)
322 {
323 vm_offset_t va = boot_address + KERNBASE;
324 u_int64_t *pt4, *pt3, *pt2;
325 u_int32_t mpbioswarmvec;
326 int apic_id, cpu, i;
327 u_char mpbiosreason;
328
329 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
330
331 /* install the AP 1st level boot code */
332 pmap_kenter(va, boot_address);
333 pmap_invalidate_page(kernel_pmap, va);
334 bcopy(mptramp_start, (void *)va, bootMP_size);
335
336 /* Locate the page tables, they'll be below the trampoline */
337 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
338 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
339 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
340
341 /* Create the initial 1GB replicated page tables */
342 for (i = 0; i < 512; i++) {
343 /* Each slot of the level 4 pages points to the same level 3 page */
344 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
345 pt4[i] |= PG_V | PG_RW | PG_U;
346
347 /* Each slot of the level 3 pages points to the same level 2 page */
348 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
349 pt3[i] |= PG_V | PG_RW | PG_U;
350
351 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
352 pt2[i] = i * (2 * 1024 * 1024);
353 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
354 }
355
356 /* save the current value of the warm-start vector */
357 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
358 outb(CMOS_REG, BIOS_RESET);
359 mpbiosreason = inb(CMOS_DATA);
360
361 /* setup a vector to our boot code */
362 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
363 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
364 outb(CMOS_REG, BIOS_RESET);
365 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
366
367 /* start each AP */
368 for (cpu = 1; cpu < mp_ncpus; cpu++) {
369 apic_id = cpu_apic_ids[cpu];
370
371 /* allocate and set up an idle stack data page */
372 bootstacks[cpu] = (void *)kmem_malloc(kernel_arena,
373 kstack_pages * PAGE_SIZE, M_WAITOK | M_ZERO);
374 doublefault_stack = (char *)kmem_malloc(kernel_arena,
375 PAGE_SIZE, M_WAITOK | M_ZERO);
376 mce_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE,
377 M_WAITOK | M_ZERO);
378 nmi_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE,
379 M_WAITOK | M_ZERO);
380 dbg_stack = (char *)kmem_malloc(kernel_arena, PAGE_SIZE,
381 M_WAITOK | M_ZERO);
382 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
383 M_WAITOK | M_ZERO);
384
385 bootSTK = (char *)bootstacks[cpu] + kstack_pages * PAGE_SIZE - 8;
386 bootAP = cpu;
387
388 /* attempt to start the Application Processor */
389 if (!start_ap(apic_id)) {
390 /* restore the warmstart vector */
391 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
392 panic("AP #%d (PHY# %d) failed!", cpu, apic_id);
393 }
394
395 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */
396 }
397
398 /* restore the warmstart vector */
399 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
400
401 outb(CMOS_REG, BIOS_RESET);
402 outb(CMOS_DATA, mpbiosreason);
403
404 /* number of APs actually started */
405 return mp_naps;
406 }
407
408
409 /*
410 * This function starts the AP (application processor) identified
411 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
412 * to accomplish this. This is necessary because of the nuances
413 * of the different hardware we might encounter. It isn't pretty,
414 * but it seems to work.
415 */
416 static int
417 start_ap(int apic_id)
418 {
419 int vector, ms;
420 int cpus;
421
422 /* calculate the vector */
423 vector = (boot_address >> 12) & 0xff;
424
425 /* used as a watchpoint to signal AP startup */
426 cpus = mp_naps;
427
428 ipi_startup(apic_id, vector);
429
430 /* Wait up to 5 seconds for it to start. */
431 for (ms = 0; ms < 5000; ms++) {
432 if (mp_naps > cpus)
433 return 1; /* return SUCCESS */
434 DELAY(1000);
435 }
436 return 0; /* return FAILURE */
437 }
438
439 void
440 invltlb_invpcid_handler(void)
441 {
442 struct invpcid_descr d;
443 uint32_t generation;
444
445 #ifdef COUNT_XINVLTLB_HITS
446 xhits_gbl[PCPU_GET(cpuid)]++;
447 #endif /* COUNT_XINVLTLB_HITS */
448 #ifdef COUNT_IPIS
449 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
450 #endif /* COUNT_IPIS */
451
452 generation = smp_tlb_generation;
453 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
454 d.pad = 0;
455 d.addr = 0;
456 invpcid(&d, smp_tlb_pmap == kernel_pmap ? INVPCID_CTXGLOB :
457 INVPCID_CTX);
458 PCPU_SET(smp_tlb_done, generation);
459 }
460
461 void
462 invltlb_invpcid_pti_handler(void)
463 {
464 struct invpcid_descr d;
465 uint32_t generation;
466
467 #ifdef COUNT_XINVLTLB_HITS
468 xhits_gbl[PCPU_GET(cpuid)]++;
469 #endif /* COUNT_XINVLTLB_HITS */
470 #ifdef COUNT_IPIS
471 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
472 #endif /* COUNT_IPIS */
473
474 generation = smp_tlb_generation;
475 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
476 d.pad = 0;
477 d.addr = 0;
478 if (smp_tlb_pmap == kernel_pmap) {
479 /*
480 * This invalidation actually needs to clear kernel
481 * mappings from the TLB in the current pmap, but
482 * since we were asked for the flush in the kernel
483 * pmap, achieve it by performing global flush.
484 */
485 invpcid(&d, INVPCID_CTXGLOB);
486 } else {
487 invpcid(&d, INVPCID_CTX);
488 d.pcid |= PMAP_PCID_USER_PT;
489 invpcid(&d, INVPCID_CTX);
490 }
491 PCPU_SET(smp_tlb_done, generation);
492 }
493
494 void
495 invltlb_pcid_handler(void)
496 {
497 uint64_t kcr3, ucr3;
498 uint32_t generation, pcid;
499
500 #ifdef COUNT_XINVLTLB_HITS
501 xhits_gbl[PCPU_GET(cpuid)]++;
502 #endif /* COUNT_XINVLTLB_HITS */
503 #ifdef COUNT_IPIS
504 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++;
505 #endif /* COUNT_IPIS */
506
507 generation = smp_tlb_generation; /* Overlap with serialization */
508 if (smp_tlb_pmap == kernel_pmap) {
509 invltlb_glob();
510 } else {
511 /*
512 * The current pmap might not be equal to
513 * smp_tlb_pmap. The clearing of the pm_gen in
514 * pmap_invalidate_all() takes care of TLB
515 * invalidation when switching to the pmap on this
516 * CPU.
517 */
518 if (PCPU_GET(curpmap) == smp_tlb_pmap) {
519 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
520 kcr3 = smp_tlb_pmap->pm_cr3 | pcid;
521 ucr3 = smp_tlb_pmap->pm_ucr3;
522 if (ucr3 != PMAP_NO_CR3) {
523 ucr3 |= PMAP_PCID_USER_PT | pcid;
524 pmap_pti_pcid_invalidate(ucr3, kcr3);
525 } else
526 load_cr3(kcr3);
527 }
528 }
529 PCPU_SET(smp_tlb_done, generation);
530 }
531
532 void
533 invlpg_invpcid_handler(void)
534 {
535 struct invpcid_descr d;
536 uint32_t generation;
537
538 #ifdef COUNT_XINVLTLB_HITS
539 xhits_pg[PCPU_GET(cpuid)]++;
540 #endif /* COUNT_XINVLTLB_HITS */
541 #ifdef COUNT_IPIS
542 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
543 #endif /* COUNT_IPIS */
544
545 generation = smp_tlb_generation; /* Overlap with serialization */
546 invlpg(smp_tlb_addr1);
547 if (smp_tlb_pmap->pm_ucr3 != PMAP_NO_CR3) {
548 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid |
549 PMAP_PCID_USER_PT;
550 d.pad = 0;
551 d.addr = smp_tlb_addr1;
552 invpcid(&d, INVPCID_ADDR);
553 }
554 PCPU_SET(smp_tlb_done, generation);
555 }
556
557 void
558 invlpg_pcid_handler(void)
559 {
560 uint64_t kcr3, ucr3;
561 uint32_t generation;
562 uint32_t pcid;
563
564 #ifdef COUNT_XINVLTLB_HITS
565 xhits_pg[PCPU_GET(cpuid)]++;
566 #endif /* COUNT_XINVLTLB_HITS */
567 #ifdef COUNT_IPIS
568 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++;
569 #endif /* COUNT_IPIS */
570
571 generation = smp_tlb_generation; /* Overlap with serialization */
572 invlpg(smp_tlb_addr1);
573 if (smp_tlb_pmap == PCPU_GET(curpmap) &&
574 (ucr3 = smp_tlb_pmap->pm_ucr3) != PMAP_NO_CR3) {
575 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
576 kcr3 = smp_tlb_pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
577 ucr3 |= pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
578 pmap_pti_pcid_invlpg(ucr3, kcr3, smp_tlb_addr1);
579 }
580 PCPU_SET(smp_tlb_done, generation);
581 }
582
583 void
584 invlrng_invpcid_handler(void)
585 {
586 struct invpcid_descr d;
587 vm_offset_t addr, addr2;
588 uint32_t generation;
589
590 #ifdef COUNT_XINVLTLB_HITS
591 xhits_rng[PCPU_GET(cpuid)]++;
592 #endif /* COUNT_XINVLTLB_HITS */
593 #ifdef COUNT_IPIS
594 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
595 #endif /* COUNT_IPIS */
596
597 addr = smp_tlb_addr1;
598 addr2 = smp_tlb_addr2;
599 generation = smp_tlb_generation; /* Overlap with serialization */
600 do {
601 invlpg(addr);
602 addr += PAGE_SIZE;
603 } while (addr < addr2);
604 if (smp_tlb_pmap->pm_ucr3 != PMAP_NO_CR3) {
605 d.pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid |
606 PMAP_PCID_USER_PT;
607 d.pad = 0;
608 d.addr = smp_tlb_addr1;
609 do {
610 invpcid(&d, INVPCID_ADDR);
611 d.addr += PAGE_SIZE;
612 } while (d.addr < addr2);
613 }
614 PCPU_SET(smp_tlb_done, generation);
615 }
616
617 void
618 invlrng_pcid_handler(void)
619 {
620 vm_offset_t addr, addr2;
621 uint64_t kcr3, ucr3;
622 uint32_t generation;
623 uint32_t pcid;
624
625 #ifdef COUNT_XINVLTLB_HITS
626 xhits_rng[PCPU_GET(cpuid)]++;
627 #endif /* COUNT_XINVLTLB_HITS */
628 #ifdef COUNT_IPIS
629 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++;
630 #endif /* COUNT_IPIS */
631
632 addr = smp_tlb_addr1;
633 addr2 = smp_tlb_addr2;
634 generation = smp_tlb_generation; /* Overlap with serialization */
635 do {
636 invlpg(addr);
637 addr += PAGE_SIZE;
638 } while (addr < addr2);
639 if (smp_tlb_pmap == PCPU_GET(curpmap) &&
640 (ucr3 = smp_tlb_pmap->pm_ucr3) != PMAP_NO_CR3) {
641 pcid = smp_tlb_pmap->pm_pcids[PCPU_GET(cpuid)].pm_pcid;
642 kcr3 = smp_tlb_pmap->pm_cr3 | pcid | CR3_PCID_SAVE;
643 ucr3 |= pcid | PMAP_PCID_USER_PT | CR3_PCID_SAVE;
644 pmap_pti_pcid_invlrng(ucr3, kcr3, smp_tlb_addr1, addr2);
645 }
646 PCPU_SET(smp_tlb_done, generation);
647 }
Cache object: 41323fea45e620f236fb91def790d2cd
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