1 /*-
2 * Copyright (c) 1996, by Steve Passe
3 * Copyright (c) 2003, by Peter Wemm
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: releng/6.1/sys/amd64/amd64/mp_machdep.c 158108 2006-04-28 06:54:34Z cperciva $");
29
30 #include "opt_cpu.h"
31 #include "opt_kdb.h"
32 #include "opt_kstack_pages.h"
33 #include "opt_mp_watchdog.h"
34 #include "opt_sched.h"
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/bus.h>
39 #ifdef GPROF
40 #include <sys/gmon.h>
41 #endif
42 #include <sys/kernel.h>
43 #include <sys/ktr.h>
44 #include <sys/lock.h>
45 #include <sys/malloc.h>
46 #include <sys/memrange.h>
47 #include <sys/mutex.h>
48 #include <sys/pcpu.h>
49 #include <sys/proc.h>
50 #include <sys/smp.h>
51 #include <sys/sysctl.h>
52
53 #include <vm/vm.h>
54 #include <vm/vm_param.h>
55 #include <vm/pmap.h>
56 #include <vm/vm_kern.h>
57 #include <vm/vm_extern.h>
58
59 #include <machine/apicreg.h>
60 #include <machine/clock.h>
61 #include <machine/md_var.h>
62 #include <machine/mp_watchdog.h>
63 #include <machine/pcb.h>
64 #include <machine/psl.h>
65 #include <machine/smp.h>
66 #include <machine/specialreg.h>
67 #include <machine/tss.h>
68
69 #define WARMBOOT_TARGET 0
70 #define WARMBOOT_OFF (KERNBASE + 0x0467)
71 #define WARMBOOT_SEG (KERNBASE + 0x0469)
72
73 #define CMOS_REG (0x70)
74 #define CMOS_DATA (0x71)
75 #define BIOS_RESET (0x0f)
76 #define BIOS_WARM (0x0a)
77
78 /* lock region used by kernel profiling */
79 int mcount_lock;
80
81 int mp_naps; /* # of Applications processors */
82 int boot_cpu_id = -1; /* designated BSP */
83 extern int nkpt;
84
85 /*
86 * CPU topology map datastructures for HTT.
87 */
88 static struct cpu_group mp_groups[MAXCPU];
89 static struct cpu_top mp_top;
90
91 /* AP uses this during bootstrap. Do not staticize. */
92 char *bootSTK;
93 static int bootAP;
94
95 /* Free these after use */
96 void *bootstacks[MAXCPU];
97
98 /* Hotwire a 0->4MB V==P mapping */
99 extern pt_entry_t *KPTphys;
100
101 /* SMP page table page */
102 extern pt_entry_t *SMPpt;
103
104 struct pcb stoppcbs[MAXCPU];
105
106 /* Variables needed for SMP tlb shootdown. */
107 vm_offset_t smp_tlb_addr1;
108 vm_offset_t smp_tlb_addr2;
109 volatile int smp_tlb_wait;
110
111 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
112
113 /*
114 * Local data and functions.
115 */
116
117 static u_int logical_cpus;
118
119 /* used to hold the AP's until we are ready to release them */
120 static struct mtx ap_boot_mtx;
121
122 /* Set to 1 once we're ready to let the APs out of the pen. */
123 static volatile int aps_ready = 0;
124
125 /*
126 * Store data from cpu_add() until later in the boot when we actually setup
127 * the APs.
128 */
129 struct cpu_info {
130 int cpu_present:1;
131 int cpu_bsp:1;
132 int cpu_disabled:1;
133 } static cpu_info[MAXCPU];
134 static int cpu_apic_ids[MAXCPU];
135
136 /* Holds pending bitmap based IPIs per CPU */
137 static volatile u_int cpu_ipi_pending[MAXCPU];
138
139 static u_int boot_address;
140
141 static void set_interrupt_apic_ids(void);
142 static int start_all_aps(void);
143 static int start_ap(int apic_id);
144 static void release_aps(void *dummy);
145
146 static int hlt_logical_cpus;
147 static u_int hyperthreading_cpus;
148 static cpumask_t hyperthreading_cpus_mask;
149 static int hyperthreading_allowed;
150 static struct sysctl_ctx_list logical_cpu_clist;
151 static u_int bootMP_size;
152
153 static void
154 mem_range_AP_init(void)
155 {
156 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
157 mem_range_softc.mr_op->initAP(&mem_range_softc);
158 }
159
160 void
161 mp_topology(void)
162 {
163 struct cpu_group *group;
164 int logical_cpus;
165 int apic_id;
166 int groups;
167 int cpu;
168
169 /* Build the smp_topology map. */
170 /* Nothing to do if there is no HTT support. */
171 if ((cpu_feature & CPUID_HTT) == 0)
172 return;
173 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
174 if (logical_cpus <= 1)
175 return;
176 group = &mp_groups[0];
177 groups = 1;
178 for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) {
179 if (!cpu_info[apic_id].cpu_present)
180 continue;
181 /*
182 * If the current group has members and we're not a logical
183 * cpu, create a new group.
184 */
185 if (group->cg_count != 0 && (apic_id % logical_cpus) == 0) {
186 group++;
187 groups++;
188 }
189 group->cg_count++;
190 group->cg_mask |= 1 << cpu;
191 cpu++;
192 }
193
194 mp_top.ct_count = groups;
195 mp_top.ct_group = mp_groups;
196 smp_topology = &mp_top;
197 }
198
199
200 #ifdef KDB_STOP_NMI
201 volatile cpumask_t ipi_nmi_pending;
202 #endif
203
204 /*
205 * Calculate usable address in base memory for AP trampoline code.
206 */
207 u_int
208 mp_bootaddress(u_int basemem)
209 {
210
211 bootMP_size = mptramp_end - mptramp_start;
212 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
213 if (((basemem * 1024) - boot_address) < bootMP_size)
214 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
215 /* 3 levels of page table pages */
216 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
217
218 return mptramp_pagetables;
219 }
220
221 void
222 cpu_add(u_int apic_id, char boot_cpu)
223 {
224
225 if (apic_id >= MAXCPU) {
226 printf("SMP: CPU %d exceeds maximum CPU %d, ignoring\n",
227 apic_id, MAXCPU - 1);
228 return;
229 }
230 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
231 apic_id));
232 cpu_info[apic_id].cpu_present = 1;
233 if (boot_cpu) {
234 KASSERT(boot_cpu_id == -1,
235 ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
236 boot_cpu_id));
237 boot_cpu_id = apic_id;
238 cpu_info[apic_id].cpu_bsp = 1;
239 }
240 mp_ncpus++;
241 if (apic_id > mp_maxid)
242 mp_maxid = apic_id;
243 if (bootverbose)
244 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
245 "AP");
246
247 }
248
249 void
250 cpu_mp_setmaxid(void)
251 {
252
253 /*
254 * mp_maxid should be already set by calls to cpu_add().
255 * Just sanity check its value here.
256 */
257 if (mp_ncpus == 0)
258 KASSERT(mp_maxid == 0,
259 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__));
260 else if (mp_ncpus == 1)
261 mp_maxid = 0;
262 else
263 KASSERT(mp_maxid >= mp_ncpus - 1,
264 ("%s: counters out of sync: max %d, count %d", __func__,
265 mp_maxid, mp_ncpus));
266
267 }
268
269 int
270 cpu_mp_probe(void)
271 {
272
273 /*
274 * Always record BSP in CPU map so that the mbuf init code works
275 * correctly.
276 */
277 all_cpus = 1;
278 if (mp_ncpus == 0) {
279 /*
280 * No CPUs were found, so this must be a UP system. Setup
281 * the variables to represent a system with a single CPU
282 * with an id of 0.
283 */
284 mp_ncpus = 1;
285 return (0);
286 }
287
288 /* At least one CPU was found. */
289 if (mp_ncpus == 1) {
290 /*
291 * One CPU was found, so this must be a UP system with
292 * an I/O APIC.
293 */
294 mp_maxid = 0;
295 return (0);
296 }
297
298 /* At least two CPUs were found. */
299 return (1);
300 }
301
302 /*
303 * Initialize the IPI handlers and start up the AP's.
304 */
305 void
306 cpu_mp_start(void)
307 {
308 int i;
309 u_int threads_per_cache, p[4];
310
311 /* Initialize the logical ID to APIC ID table. */
312 for (i = 0; i < MAXCPU; i++) {
313 cpu_apic_ids[i] = -1;
314 cpu_ipi_pending[i] = 0;
315 }
316
317 /* Install an inter-CPU IPI for TLB invalidation */
318 setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0);
319 setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0);
320 setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0);
321
322 /* Install an inter-CPU IPI for all-CPU rendezvous */
323 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
324
325 /* Install generic inter-CPU IPI handler */
326 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
327 SDT_SYSIGT, SEL_KPL, 0);
328
329 /* Install an inter-CPU IPI for CPU stop/restart */
330 setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0);
331
332 /* Set boot_cpu_id if needed. */
333 if (boot_cpu_id == -1) {
334 boot_cpu_id = PCPU_GET(apic_id);
335 cpu_info[boot_cpu_id].cpu_bsp = 1;
336 } else
337 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
338 ("BSP's APIC ID doesn't match boot_cpu_id"));
339 cpu_apic_ids[0] = boot_cpu_id;
340
341 /* Start each Application Processor */
342 start_all_aps();
343
344 /* Setup the initial logical CPUs info. */
345 logical_cpus = logical_cpus_mask = 0;
346 if (cpu_feature & CPUID_HTT)
347 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
348
349 /*
350 * Work out if hyperthreading is *really* enabled. This
351 * is made really ugly by the fact that processors lie: Dual
352 * core processors claim to be hyperthreaded even when they're
353 * not, presumably because they want to be treated the same
354 * way as HTT with respect to per-cpu software licensing.
355 * At the time of writing (May 12, 2005) the only hyperthreaded
356 * cpus are from Intel, and Intel's dual-core processors can be
357 * identified via the "deterministic cache parameters" cpuid
358 * calls.
359 */
360 /*
361 * First determine if this is an Intel processor which claims
362 * to have hyperthreading support.
363 */
364 if ((cpu_feature & CPUID_HTT) &&
365 (strcmp(cpu_vendor, "GenuineIntel") == 0)) {
366 /*
367 * If the "deterministic cache parameters" cpuid calls
368 * are available, use them.
369 */
370 if (cpu_high >= 4) {
371 /* Ask the processor about the L1 cache. */
372 for (i = 0; i < 1; i++) {
373 cpuid_count(4, i, p);
374 threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1;
375 if (hyperthreading_cpus < threads_per_cache)
376 hyperthreading_cpus = threads_per_cache;
377 if ((p[0] & 0x1f) == 0)
378 break;
379 }
380 }
381
382 /*
383 * If the deterministic cache parameters are not
384 * available, or if no caches were reported to exist,
385 * just accept what the HTT flag indicated.
386 */
387 if (hyperthreading_cpus == 0)
388 hyperthreading_cpus = logical_cpus;
389 }
390
391 set_interrupt_apic_ids();
392 }
393
394
395 /*
396 * Print various information about the SMP system hardware and setup.
397 */
398 void
399 cpu_mp_announce(void)
400 {
401 int i, x;
402
403 /* List CPUs */
404 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id);
405 for (i = 1, x = 0; x < MAXCPU; x++) {
406 if (!cpu_info[x].cpu_present || cpu_info[x].cpu_bsp)
407 continue;
408 if (cpu_info[x].cpu_disabled)
409 printf(" cpu (AP): APIC ID: %2d (disabled)\n", x);
410 else {
411 KASSERT(i < mp_ncpus,
412 ("mp_ncpus and actual cpus are out of whack"));
413 printf(" cpu%d (AP): APIC ID: %2d\n", i++, x);
414 }
415 }
416 }
417
418 /*
419 * AP CPU's call this to initialize themselves.
420 */
421 void
422 init_secondary(void)
423 {
424 struct pcpu *pc;
425 u_int64_t msr, cr0;
426 int cpu, gsel_tss;
427
428 /* Set by the startup code for us to use */
429 cpu = bootAP;
430
431 /* Init tss */
432 common_tss[cpu] = common_tss[0];
433 common_tss[cpu].tss_rsp0 = 0; /* not used until after switch */
434 common_tss[cpu].tss_iobase = sizeof(struct amd64tss);
435
436 gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu];
437 ssdtosyssd(&gdt_segs[GPROC0_SEL],
438 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
439
440 lgdt(&r_gdt); /* does magic intra-segment return */
441
442 /* Get per-cpu data */
443 pc = &__pcpu[cpu];
444
445 /* prime data page for it to use */
446 pcpu_init(pc, cpu, sizeof(struct pcpu));
447 pc->pc_apic_id = cpu_apic_ids[cpu];
448 pc->pc_prvspace = pc;
449 pc->pc_curthread = 0;
450 pc->pc_tssp = &common_tss[cpu];
451 pc->pc_rsp0 = 0;
452
453 wrmsr(MSR_FSBASE, 0); /* User value */
454 wrmsr(MSR_GSBASE, (u_int64_t)pc);
455 wrmsr(MSR_KGSBASE, (u_int64_t)pc); /* XXX User value while we're in the kernel */
456
457 lidt(&r_idt);
458
459 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
460 ltr(gsel_tss);
461
462 /*
463 * Set to a known state:
464 * Set by mpboot.s: CR0_PG, CR0_PE
465 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
466 */
467 cr0 = rcr0();
468 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
469 load_cr0(cr0);
470
471 /* Set up the fast syscall stuff */
472 msr = rdmsr(MSR_EFER) | EFER_SCE;
473 wrmsr(MSR_EFER, msr);
474 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
475 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
476 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
477 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
478 wrmsr(MSR_STAR, msr);
479 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
480
481 /* Disable local APIC just to be sure. */
482 lapic_disable();
483
484 /* signal our startup to the BSP. */
485 mp_naps++;
486
487 /* Spin until the BSP releases the AP's. */
488 while (!aps_ready)
489 ia32_pause();
490
491 /* set up CPU registers and state */
492 cpu_setregs();
493
494 /* set up SSE/NX registers */
495 initializecpu();
496
497 /* set up FPU state on the AP */
498 fpuinit();
499
500 /* A quick check from sanity claus */
501 if (PCPU_GET(apic_id) != lapic_id()) {
502 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
503 printf("SMP: actual apic_id = %d\n", lapic_id());
504 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
505 panic("cpuid mismatch! boom!!");
506 }
507
508 /* Initialize curthread. */
509 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
510 PCPU_SET(curthread, PCPU_GET(idlethread));
511
512 mtx_lock_spin(&ap_boot_mtx);
513
514 /* Init local apic for irq's */
515 lapic_setup();
516
517 /* Set memory range attributes for this CPU to match the BSP */
518 mem_range_AP_init();
519
520 smp_cpus++;
521
522 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid));
523 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
524
525 /* Determine if we are a logical CPU. */
526 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0)
527 logical_cpus_mask |= PCPU_GET(cpumask);
528
529 /* Determine if we are a hyperthread. */
530 if (hyperthreading_cpus > 1 &&
531 PCPU_GET(apic_id) % hyperthreading_cpus != 0)
532 hyperthreading_cpus_mask |= PCPU_GET(cpumask);
533
534 /* Build our map of 'other' CPUs. */
535 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
536
537 if (bootverbose)
538 lapic_dump("AP");
539
540 if (smp_cpus == mp_ncpus) {
541 /* enable IPI's, tlb shootdown, freezes etc */
542 atomic_store_rel_int(&smp_started, 1);
543 smp_active = 1; /* historic */
544 }
545
546 /*
547 * Enable global pages TLB extension
548 * This also implicitly flushes the TLB
549 */
550
551 load_cr4(rcr4() | CR4_PGE);
552
553 mtx_unlock_spin(&ap_boot_mtx);
554
555 /* wait until all the AP's are up */
556 while (smp_started == 0)
557 ia32_pause();
558
559 /* ok, now grab sched_lock and enter the scheduler */
560 mtx_lock_spin(&sched_lock);
561
562 /*
563 * Correct spinlock nesting. The idle thread context that we are
564 * borrowing was created so that it would start out with a single
565 * spin lock (sched_lock) held in fork_trampoline(). Since we've
566 * explicitly acquired locks in this function, the nesting count
567 * is now 2 rather than 1. Since we are nested, calling
568 * spinlock_exit() will simply adjust the counts without allowing
569 * spin lock using code to interrupt us.
570 */
571 spinlock_exit();
572 KASSERT(curthread->td_md.md_spinlock_count == 1, ("invalid count"));
573
574 binuptime(PCPU_PTR(switchtime));
575 PCPU_SET(switchticks, ticks);
576
577 cpu_throw(NULL, choosethread()); /* doesn't return */
578
579 panic("scheduler returned us to %s", __func__);
580 /* NOTREACHED */
581 }
582
583 /*******************************************************************
584 * local functions and data
585 */
586
587 /*
588 * We tell the I/O APIC code about all the CPUs we want to receive
589 * interrupts. If we don't want certain CPUs to receive IRQs we
590 * can simply not tell the I/O APIC code about them in this function.
591 * We also do not tell it about the BSP since it tells itself about
592 * the BSP internally to work with UP kernels and on UP machines.
593 */
594 static void
595 set_interrupt_apic_ids(void)
596 {
597 u_int apic_id;
598
599 for (apic_id = 0; apic_id < MAXCPU; apic_id++) {
600 if (!cpu_info[apic_id].cpu_present)
601 continue;
602 if (cpu_info[apic_id].cpu_bsp)
603 continue;
604
605 /* Don't let hyperthreads service interrupts. */
606 if (hyperthreading_cpus > 1 &&
607 apic_id % hyperthreading_cpus != 0)
608 continue;
609
610 intr_add_cpu(apic_id);
611 }
612 }
613
614 /*
615 * start each AP in our list
616 */
617 static int
618 start_all_aps(void)
619 {
620 vm_offset_t va = boot_address + KERNBASE;
621 u_int64_t *pt4, *pt3, *pt2;
622 u_int32_t mpbioswarmvec;
623 int apic_id, cpu, i;
624 u_char mpbiosreason;
625
626 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
627
628 /* install the AP 1st level boot code */
629 pmap_kenter(va, boot_address);
630 pmap_invalidate_page(kernel_pmap, va);
631 bcopy(mptramp_start, (void *)va, bootMP_size);
632
633 /* Locate the page tables, they'll be below the trampoline */
634 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
635 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
636 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
637
638 /* Create the initial 1GB replicated page tables */
639 for (i = 0; i < 512; i++) {
640 /* Each slot of the level 4 pages points to the same level 3 page */
641 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
642 pt4[i] |= PG_V | PG_RW | PG_U;
643
644 /* Each slot of the level 3 pages points to the same level 2 page */
645 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
646 pt3[i] |= PG_V | PG_RW | PG_U;
647
648 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
649 pt2[i] = i * (2 * 1024 * 1024);
650 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
651 }
652
653 /* save the current value of the warm-start vector */
654 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
655 outb(CMOS_REG, BIOS_RESET);
656 mpbiosreason = inb(CMOS_DATA);
657
658 /* setup a vector to our boot code */
659 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
660 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
661 outb(CMOS_REG, BIOS_RESET);
662 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
663
664 /* start each AP */
665 for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) {
666
667 /* Ignore non-existent CPUs and the BSP. */
668 if (!cpu_info[apic_id].cpu_present ||
669 cpu_info[apic_id].cpu_bsp)
670 continue;
671
672 /* Don't use this CPU if it has been disabled by a tunable. */
673 if (resource_disabled("lapic", apic_id)) {
674 cpu_info[apic_id].cpu_disabled = 1;
675 mp_ncpus--;
676 continue;
677 }
678
679 cpu++;
680
681 /* save APIC ID for this logical ID */
682 cpu_apic_ids[cpu] = apic_id;
683
684 /* allocate and set up an idle stack data page */
685 bootstacks[cpu] = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE);
686
687 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 8;
688 bootAP = cpu;
689
690 /* attempt to start the Application Processor */
691 if (!start_ap(apic_id)) {
692 /* restore the warmstart vector */
693 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
694 panic("AP #%d (PHY# %d) failed!", cpu, apic_id);
695 }
696
697 all_cpus |= (1 << cpu); /* record AP in CPU map */
698 }
699
700 /* build our map of 'other' CPUs */
701 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
702
703 /* restore the warmstart vector */
704 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
705
706 outb(CMOS_REG, BIOS_RESET);
707 outb(CMOS_DATA, mpbiosreason);
708
709 /* number of APs actually started */
710 return mp_naps;
711 }
712
713
714 /*
715 * This function starts the AP (application processor) identified
716 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
717 * to accomplish this. This is necessary because of the nuances
718 * of the different hardware we might encounter. It isn't pretty,
719 * but it seems to work.
720 */
721 static int
722 start_ap(int apic_id)
723 {
724 int vector, ms;
725 int cpus;
726
727 /* calculate the vector */
728 vector = (boot_address >> 12) & 0xff;
729
730 /* used as a watchpoint to signal AP startup */
731 cpus = mp_naps;
732
733 /*
734 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
735 * and running the target CPU. OR this INIT IPI might be latched (P5
736 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
737 * ignored.
738 */
739
740 /* do an INIT IPI: assert RESET */
741 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
742 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
743
744 /* wait for pending status end */
745 lapic_ipi_wait(-1);
746
747 /* do an INIT IPI: deassert RESET */
748 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL |
749 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0);
750
751 /* wait for pending status end */
752 DELAY(10000); /* wait ~10mS */
753 lapic_ipi_wait(-1);
754
755 /*
756 * next we do a STARTUP IPI: the previous INIT IPI might still be
757 * latched, (P5 bug) this 1st STARTUP would then terminate
758 * immediately, and the previously started INIT IPI would continue. OR
759 * the previous INIT IPI has already run. and this STARTUP IPI will
760 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
761 * will run.
762 */
763
764 /* do a STARTUP IPI */
765 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
766 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
767 vector, apic_id);
768 lapic_ipi_wait(-1);
769 DELAY(200); /* wait ~200uS */
770
771 /*
772 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
773 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
774 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
775 * recognized after hardware RESET or INIT IPI.
776 */
777
778 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
779 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
780 vector, apic_id);
781 lapic_ipi_wait(-1);
782 DELAY(200); /* wait ~200uS */
783
784 /* Wait up to 5 seconds for it to start. */
785 for (ms = 0; ms < 5000; ms++) {
786 if (mp_naps > cpus)
787 return 1; /* return SUCCESS */
788 DELAY(1000);
789 }
790 return 0; /* return FAILURE */
791 }
792
793 /*
794 * Flush the TLB on all other CPU's
795 */
796 static void
797 smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
798 {
799 u_int ncpu;
800
801 ncpu = mp_ncpus - 1; /* does not shootdown self */
802 if (ncpu < 1)
803 return; /* no other cpus */
804 mtx_assert(&smp_ipi_mtx, MA_OWNED);
805 smp_tlb_addr1 = addr1;
806 smp_tlb_addr2 = addr2;
807 atomic_store_rel_int(&smp_tlb_wait, 0);
808 ipi_all_but_self(vector);
809 while (smp_tlb_wait < ncpu)
810 ia32_pause();
811 }
812
813 static void
814 smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
815 {
816 int ncpu, othercpus;
817
818 othercpus = mp_ncpus - 1;
819 if (mask == (u_int)-1) {
820 ncpu = othercpus;
821 if (ncpu < 1)
822 return;
823 } else {
824 mask &= ~PCPU_GET(cpumask);
825 if (mask == 0)
826 return;
827 ncpu = bitcount32(mask);
828 if (ncpu > othercpus) {
829 /* XXX this should be a panic offence */
830 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n",
831 ncpu, othercpus);
832 ncpu = othercpus;
833 }
834 /* XXX should be a panic, implied by mask == 0 above */
835 if (ncpu < 1)
836 return;
837 }
838 mtx_assert(&smp_ipi_mtx, MA_OWNED);
839 smp_tlb_addr1 = addr1;
840 smp_tlb_addr2 = addr2;
841 atomic_store_rel_int(&smp_tlb_wait, 0);
842 if (mask == (u_int)-1)
843 ipi_all_but_self(vector);
844 else
845 ipi_selected(mask, vector);
846 while (smp_tlb_wait < ncpu)
847 ia32_pause();
848 }
849
850 void
851 smp_invltlb(void)
852 {
853
854 if (smp_started) {
855 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
856 }
857 }
858
859 void
860 smp_invlpg(vm_offset_t addr)
861 {
862
863 if (smp_started)
864 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
865 }
866
867 void
868 smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
869 {
870
871 if (smp_started) {
872 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
873 }
874 }
875
876 void
877 smp_masked_invltlb(u_int mask)
878 {
879
880 if (smp_started) {
881 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
882 }
883 }
884
885 void
886 smp_masked_invlpg(u_int mask, vm_offset_t addr)
887 {
888
889 if (smp_started) {
890 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
891 }
892 }
893
894 void
895 smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2)
896 {
897
898 if (smp_started) {
899 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
900 }
901 }
902
903
904 void
905 ipi_bitmap_handler(struct clockframe frame)
906 {
907 int cpu = PCPU_GET(cpuid);
908 u_int ipi_bitmap;
909
910 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
911
912 #ifdef IPI_PREEMPTION
913 if (ipi_bitmap & IPI_PREEMPT) {
914 mtx_lock_spin(&sched_lock);
915 /* Don't preempt the idle thread */
916 if (curthread->td_priority < PRI_MIN_IDLE) {
917 struct thread *running_thread = curthread;
918 if (running_thread->td_critnest > 1)
919 running_thread->td_owepreempt = 1;
920 else
921 mi_switch(SW_INVOL | SW_PREEMPT, NULL);
922 }
923 mtx_unlock_spin(&sched_lock);
924 }
925 #endif
926
927 /* Nothing to do for AST */
928 }
929
930 /*
931 * send an IPI to a set of cpus.
932 */
933 void
934 ipi_selected(u_int32_t cpus, u_int ipi)
935 {
936 int cpu;
937 u_int bitmap = 0;
938 u_int old_pending;
939 u_int new_pending;
940
941 if (IPI_IS_BITMAPED(ipi)) {
942 bitmap = 1 << ipi;
943 ipi = IPI_BITMAP_VECTOR;
944 }
945
946 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi);
947 while ((cpu = ffs(cpus)) != 0) {
948 cpu--;
949 cpus &= ~(1 << cpu);
950
951 KASSERT(cpu_apic_ids[cpu] != -1,
952 ("IPI to non-existent CPU %d", cpu));
953
954 if (bitmap) {
955 do {
956 old_pending = cpu_ipi_pending[cpu];
957 new_pending = old_pending | bitmap;
958 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],old_pending, new_pending));
959
960 if (old_pending)
961 continue;
962 }
963
964 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
965 }
966
967 }
968
969 /*
970 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself
971 */
972 void
973 ipi_all(u_int ipi)
974 {
975
976 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
977 lapic_ipi_vectored(ipi, APIC_IPI_DEST_ALL);
978 }
979
980 /*
981 * send an IPI to all CPUs EXCEPT myself
982 */
983 void
984 ipi_all_but_self(u_int ipi)
985 {
986
987 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
988 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
989 }
990
991 /*
992 * send an IPI to myself
993 */
994 void
995 ipi_self(u_int ipi)
996 {
997
998 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
999 lapic_ipi_vectored(ipi, APIC_IPI_DEST_SELF);
1000 }
1001
1002 #ifdef KDB_STOP_NMI
1003 /*
1004 * send NMI IPI to selected CPUs
1005 */
1006
1007 #define BEFORE_SPIN 1000000
1008
1009 void
1010 ipi_nmi_selected(u_int32_t cpus)
1011 {
1012
1013 int cpu;
1014 register_t icrlo;
1015
1016 icrlo = APIC_DELMODE_NMI | APIC_DESTMODE_PHY | APIC_LEVEL_ASSERT
1017 | APIC_TRIGMOD_EDGE;
1018
1019 CTR2(KTR_SMP, "%s: cpus: %x nmi", __func__, cpus);
1020
1021
1022 atomic_set_int(&ipi_nmi_pending, cpus);
1023
1024
1025 while ((cpu = ffs(cpus)) != 0) {
1026 cpu--;
1027 cpus &= ~(1 << cpu);
1028
1029 KASSERT(cpu_apic_ids[cpu] != -1,
1030 ("IPI NMI to non-existent CPU %d", cpu));
1031
1032 /* Wait for an earlier IPI to finish. */
1033 if (!lapic_ipi_wait(BEFORE_SPIN))
1034 panic("ipi_nmi_selected: previous IPI has not cleared");
1035
1036 lapic_ipi_raw(icrlo,cpu_apic_ids[cpu]);
1037 }
1038 }
1039
1040
1041 int
1042 ipi_nmi_handler()
1043 {
1044 int cpu = PCPU_GET(cpuid);
1045
1046 if(!(atomic_load_acq_int(&ipi_nmi_pending) & (1 << cpu)))
1047 return 1;
1048
1049 atomic_clear_int(&ipi_nmi_pending,1 << cpu);
1050
1051 savectx(&stoppcbs[cpu]);
1052
1053 /* Indicate that we are stopped */
1054 atomic_set_int(&stopped_cpus,1 << cpu);
1055
1056
1057 /* Wait for restart */
1058 while(!(atomic_load_acq_int(&started_cpus) & (1 << cpu)))
1059 ia32_pause();
1060
1061 atomic_clear_int(&started_cpus,1 << cpu);
1062 atomic_clear_int(&stopped_cpus,1 << cpu);
1063
1064 if(cpu == 0 && cpustop_restartfunc != NULL)
1065 cpustop_restartfunc();
1066
1067 return 0;
1068 }
1069
1070 #endif /* KDB_STOP_NMI */
1071
1072 /*
1073 * This is called once the rest of the system is up and running and we're
1074 * ready to let the AP's out of the pen.
1075 */
1076 static void
1077 release_aps(void *dummy __unused)
1078 {
1079
1080 if (mp_ncpus == 1)
1081 return;
1082 mtx_lock_spin(&sched_lock);
1083 atomic_store_rel_int(&aps_ready, 1);
1084 while (smp_started == 0)
1085 ia32_pause();
1086 mtx_unlock_spin(&sched_lock);
1087 }
1088 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1089
1090 static int
1091 sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS)
1092 {
1093 u_int mask;
1094 int error;
1095
1096 mask = hlt_cpus_mask;
1097 error = sysctl_handle_int(oidp, &mask, 0, req);
1098 if (error || !req->newptr)
1099 return (error);
1100
1101 if (logical_cpus_mask != 0 &&
1102 (mask & logical_cpus_mask) == logical_cpus_mask)
1103 hlt_logical_cpus = 1;
1104 else
1105 hlt_logical_cpus = 0;
1106
1107 if (! hyperthreading_allowed)
1108 mask |= hyperthreading_cpus_mask;
1109
1110 if ((mask & all_cpus) == all_cpus)
1111 mask &= ~(1<<0);
1112 hlt_cpus_mask = mask;
1113 return (error);
1114 }
1115 SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW,
1116 0, 0, sysctl_hlt_cpus, "IU",
1117 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2.");
1118
1119 static int
1120 sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS)
1121 {
1122 int disable, error;
1123
1124 disable = hlt_logical_cpus;
1125 error = sysctl_handle_int(oidp, &disable, 0, req);
1126 if (error || !req->newptr)
1127 return (error);
1128
1129 if (disable)
1130 hlt_cpus_mask |= logical_cpus_mask;
1131 else
1132 hlt_cpus_mask &= ~logical_cpus_mask;
1133
1134 if (! hyperthreading_allowed)
1135 hlt_cpus_mask |= hyperthreading_cpus_mask;
1136
1137 if ((hlt_cpus_mask & all_cpus) == all_cpus)
1138 hlt_cpus_mask &= ~(1<<0);
1139
1140 hlt_logical_cpus = disable;
1141 return (error);
1142 }
1143
1144 static int
1145 sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS)
1146 {
1147 int allowed, error;
1148
1149 allowed = hyperthreading_allowed;
1150 error = sysctl_handle_int(oidp, &allowed, 0, req);
1151 if (error || !req->newptr)
1152 return (error);
1153
1154 if (allowed)
1155 hlt_cpus_mask &= ~hyperthreading_cpus_mask;
1156 else
1157 hlt_cpus_mask |= hyperthreading_cpus_mask;
1158
1159 if (logical_cpus_mask != 0 &&
1160 (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask)
1161 hlt_logical_cpus = 1;
1162 else
1163 hlt_logical_cpus = 0;
1164
1165 if ((hlt_cpus_mask & all_cpus) == all_cpus)
1166 hlt_cpus_mask &= ~(1<<0);
1167
1168 hyperthreading_allowed = allowed;
1169 return (error);
1170 }
1171
1172 static void
1173 cpu_hlt_setup(void *dummy __unused)
1174 {
1175
1176 if (logical_cpus_mask != 0) {
1177 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus",
1178 &hlt_logical_cpus);
1179 sysctl_ctx_init(&logical_cpu_clist);
1180 SYSCTL_ADD_PROC(&logical_cpu_clist,
1181 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1182 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0,
1183 sysctl_hlt_logical_cpus, "IU", "");
1184 SYSCTL_ADD_UINT(&logical_cpu_clist,
1185 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1186 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD,
1187 &logical_cpus_mask, 0, "");
1188
1189 if (hlt_logical_cpus)
1190 hlt_cpus_mask |= logical_cpus_mask;
1191
1192 /*
1193 * If necessary for security purposes, force
1194 * hyperthreading off, regardless of the value
1195 * of hlt_logical_cpus.
1196 */
1197 if (hyperthreading_cpus_mask) {
1198 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed",
1199 &hyperthreading_allowed);
1200 SYSCTL_ADD_PROC(&logical_cpu_clist,
1201 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1202 "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW,
1203 0, 0, sysctl_hyperthreading_allowed, "IU", "");
1204 if (! hyperthreading_allowed)
1205 hlt_cpus_mask |= hyperthreading_cpus_mask;
1206 }
1207 }
1208 }
1209 SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL);
1210
1211 int
1212 mp_grab_cpu_hlt(void)
1213 {
1214 u_int mask = PCPU_GET(cpumask);
1215 #ifdef MP_WATCHDOG
1216 u_int cpuid = PCPU_GET(cpuid);
1217 #endif
1218 int retval;
1219
1220 #ifdef MP_WATCHDOG
1221 ap_watchdog(cpuid);
1222 #endif
1223
1224 retval = mask & hlt_cpus_mask;
1225 while (mask & hlt_cpus_mask)
1226 __asm __volatile("sti; hlt" : : : "memory");
1227 return (retval);
1228 }
Cache object: 304d0843cd4430b2c285700e626990a7
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