The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/mp_machdep.c

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    1 /*-
    2  * Copyright (c) 1996, by Steve Passe
    3  * Copyright (c) 2003, by Peter Wemm
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. The name of the developer may NOT be used to endorse or promote products
   12  *    derived from this software without specific prior written permission.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD: releng/8.3/sys/amd64/amd64/mp_machdep.c 223413 2011-06-22 07:18:14Z avg $");
   29 
   30 #include "opt_cpu.h"
   31 #include "opt_kstack_pages.h"
   32 #include "opt_mp_watchdog.h"
   33 #include "opt_sched.h"
   34 
   35 #include <sys/param.h>
   36 #include <sys/systm.h>
   37 #include <sys/bus.h>
   38 #ifdef GPROF 
   39 #include <sys/gmon.h>
   40 #endif
   41 #include <sys/kernel.h>
   42 #include <sys/ktr.h>
   43 #include <sys/lock.h>
   44 #include <sys/malloc.h>
   45 #include <sys/memrange.h>
   46 #include <sys/mutex.h>
   47 #include <sys/pcpu.h>
   48 #include <sys/proc.h>
   49 #include <sys/sched.h>
   50 #include <sys/smp.h>
   51 #include <sys/sysctl.h>
   52 
   53 #include <vm/vm.h>
   54 #include <vm/vm_param.h>
   55 #include <vm/pmap.h>
   56 #include <vm/vm_kern.h>
   57 #include <vm/vm_extern.h>
   58 
   59 #include <machine/apicreg.h>
   60 #include <machine/clock.h>
   61 #include <machine/cputypes.h>
   62 #include <machine/cpufunc.h>
   63 #include <machine/mca.h>
   64 #include <machine/md_var.h>
   65 #include <machine/mp_watchdog.h>
   66 #include <machine/pcb.h>
   67 #include <machine/psl.h>
   68 #include <machine/smp.h>
   69 #include <machine/specialreg.h>
   70 #include <machine/tss.h>
   71 
   72 #define WARMBOOT_TARGET         0
   73 #define WARMBOOT_OFF            (KERNBASE + 0x0467)
   74 #define WARMBOOT_SEG            (KERNBASE + 0x0469)
   75 
   76 #define CMOS_REG                (0x70)
   77 #define CMOS_DATA               (0x71)
   78 #define BIOS_RESET              (0x0f)
   79 #define BIOS_WARM               (0x0a)
   80 
   81 /* lock region used by kernel profiling */
   82 int     mcount_lock;
   83 
   84 int     mp_naps;                /* # of Applications processors */
   85 int     boot_cpu_id = -1;       /* designated BSP */
   86 
   87 extern  struct pcpu __pcpu[];
   88 
   89 /* AP uses this during bootstrap.  Do not staticize.  */
   90 char *bootSTK;
   91 static int bootAP;
   92 
   93 /* Free these after use */
   94 void *bootstacks[MAXCPU];
   95 
   96 /* Temporary variables for init_secondary()  */
   97 char *doublefault_stack;
   98 char *nmi_stack;
   99 void *dpcpu;
  100 
  101 /* Hotwire a 0->4MB V==P mapping */
  102 extern pt_entry_t *KPTphys;
  103 
  104 /* SMP page table page */
  105 extern pt_entry_t *SMPpt;
  106 
  107 struct pcb stoppcbs[MAXCPU];
  108 struct pcb **susppcbs = NULL;
  109 
  110 /* Variables needed for SMP tlb shootdown. */
  111 vm_offset_t smp_tlb_addr1;
  112 vm_offset_t smp_tlb_addr2;
  113 volatile int smp_tlb_wait;
  114 
  115 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
  116 
  117 /*
  118  * Local data and functions.
  119  */
  120 
  121 static volatile cpumask_t ipi_nmi_pending;
  122 
  123 /* used to hold the AP's until we are ready to release them */
  124 static struct mtx ap_boot_mtx;
  125 
  126 /* Set to 1 once we're ready to let the APs out of the pen. */
  127 static volatile int aps_ready = 0;
  128 
  129 /*
  130  * Store data from cpu_add() until later in the boot when we actually setup
  131  * the APs.
  132  */
  133 struct cpu_info {
  134         int     cpu_present:1;
  135         int     cpu_bsp:1;
  136         int     cpu_disabled:1;
  137         int     cpu_hyperthread:1;
  138 } static cpu_info[MAX_APIC_ID + 1];
  139 int cpu_apic_ids[MAXCPU];
  140 int apic_cpuids[MAX_APIC_ID + 1];
  141 
  142 /* Holds pending bitmap based IPIs per CPU */
  143 static volatile u_int cpu_ipi_pending[MAXCPU];
  144 
  145 static u_int boot_address;
  146 static int cpu_logical;                 /* logical cpus per core */
  147 static int cpu_cores;                   /* cores per package */
  148 
  149 static void     assign_cpu_ids(void);
  150 static void     set_interrupt_apic_ids(void);
  151 static int      start_all_aps(void);
  152 static int      start_ap(int apic_id);
  153 static void     release_aps(void *dummy);
  154 
  155 static int      hlt_logical_cpus;
  156 static u_int    hyperthreading_cpus;    /* logical cpus sharing L1 cache */
  157 static cpumask_t        hyperthreading_cpus_mask;
  158 static int      hyperthreading_allowed = 1;
  159 static struct   sysctl_ctx_list logical_cpu_clist;
  160 static u_int    bootMP_size;
  161 
  162 static void
  163 mem_range_AP_init(void)
  164 {
  165         if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
  166                 mem_range_softc.mr_op->initAP(&mem_range_softc);
  167 }
  168 
  169 static void
  170 topo_probe_amd(void)
  171 {
  172         int core_id_bits;
  173         int id;
  174 
  175         /* AMD processors do not support HTT. */
  176         cpu_logical = 1;
  177 
  178         if ((amd_feature2 & AMDID2_CMP) == 0) {
  179                 cpu_cores = 1;
  180                 return;
  181         }
  182 
  183         core_id_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >>
  184             AMDID_COREID_SIZE_SHIFT;
  185         if (core_id_bits == 0) {
  186                 cpu_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
  187                 return;
  188         }
  189 
  190         /* Fam 10h and newer should get here. */
  191         for (id = 0; id <= MAX_APIC_ID; id++) {
  192                 /* Check logical CPU availability. */
  193                 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
  194                         continue;
  195                 /* Check if logical CPU has the same package ID. */
  196                 if ((id >> core_id_bits) != (boot_cpu_id >> core_id_bits))
  197                         continue;
  198                 cpu_cores++;
  199         }
  200 }
  201 
  202 /*
  203  * Round up to the next power of two, if necessary, and then
  204  * take log2.
  205  * Returns -1 if argument is zero.
  206  */
  207 static __inline int
  208 mask_width(u_int x)
  209 {
  210 
  211         return (fls(x << (1 - powerof2(x))) - 1);
  212 }
  213 
  214 static void
  215 topo_probe_0x4(void)
  216 {
  217         u_int p[4];
  218         int pkg_id_bits;
  219         int core_id_bits;
  220         int max_cores;
  221         int max_logical;
  222         int id;
  223 
  224         /* Both zero and one here mean one logical processor per package. */
  225         max_logical = (cpu_feature & CPUID_HTT) != 0 ?
  226             (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
  227         if (max_logical <= 1)
  228                 return;
  229 
  230         /*
  231          * Because of uniformity assumption we examine only
  232          * those logical processors that belong to the same
  233          * package as BSP.  Further, we count number of
  234          * logical processors that belong to the same core
  235          * as BSP thus deducing number of threads per core.
  236          */
  237         if (cpu_high >= 0x4) {
  238                 cpuid_count(0x04, 0, p);
  239                 max_cores = ((p[0] >> 26) & 0x3f) + 1;
  240         } else
  241                 max_cores = 1;
  242         core_id_bits = mask_width(max_logical/max_cores);
  243         if (core_id_bits < 0)
  244                 return;
  245         pkg_id_bits = core_id_bits + mask_width(max_cores);
  246 
  247         for (id = 0; id <= MAX_APIC_ID; id++) {
  248                 /* Check logical CPU availability. */
  249                 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
  250                         continue;
  251                 /* Check if logical CPU has the same package ID. */
  252                 if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits))
  253                         continue;
  254                 cpu_cores++;
  255                 /* Check if logical CPU has the same package and core IDs. */
  256                 if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits))
  257                         cpu_logical++;
  258         }
  259 
  260         KASSERT(cpu_cores >= 1 && cpu_logical >= 1,
  261             ("topo_probe_0x4 couldn't find BSP"));
  262 
  263         cpu_cores /= cpu_logical;
  264         hyperthreading_cpus = cpu_logical;
  265 }
  266 
  267 static void
  268 topo_probe_0xb(void)
  269 {
  270         u_int p[4];
  271         int bits;
  272         int cnt;
  273         int i;
  274         int logical;
  275         int type;
  276         int x;
  277 
  278         /* We only support three levels for now. */
  279         for (i = 0; i < 3; i++) {
  280                 cpuid_count(0x0b, i, p);
  281 
  282                 /* Fall back if CPU leaf 11 doesn't really exist. */
  283                 if (i == 0 && p[1] == 0) {
  284                         topo_probe_0x4();
  285                         return;
  286                 }
  287 
  288                 bits = p[0] & 0x1f;
  289                 logical = p[1] &= 0xffff;
  290                 type = (p[2] >> 8) & 0xff;
  291                 if (type == 0 || logical == 0)
  292                         break;
  293                 /*
  294                  * Because of uniformity assumption we examine only
  295                  * those logical processors that belong to the same
  296                  * package as BSP.
  297                  */
  298                 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) {
  299                         if (!cpu_info[x].cpu_present ||
  300                             cpu_info[x].cpu_disabled)
  301                                 continue;
  302                         if (x >> bits == boot_cpu_id >> bits)
  303                                 cnt++;
  304                 }
  305                 if (type == CPUID_TYPE_SMT)
  306                         cpu_logical = cnt;
  307                 else if (type == CPUID_TYPE_CORE)
  308                         cpu_cores = cnt;
  309         }
  310         if (cpu_logical == 0)
  311                 cpu_logical = 1;
  312         cpu_cores /= cpu_logical;
  313 }
  314 
  315 /*
  316  * Both topology discovery code and code that consumes topology
  317  * information assume top-down uniformity of the topology.
  318  * That is, all physical packages must be identical and each
  319  * core in a package must have the same number of threads.
  320  * Topology information is queried only on BSP, on which this
  321  * code runs and for which it can query CPUID information.
  322  * Then topology is extrapolated on all packages using the
  323  * uniformity assumption.
  324  */
  325 static void
  326 topo_probe(void)
  327 {
  328         static int cpu_topo_probed = 0;
  329 
  330         if (cpu_topo_probed)
  331                 return;
  332 
  333         logical_cpus_mask = 0;
  334         if (mp_ncpus <= 1)
  335                 cpu_cores = cpu_logical = 1;
  336         else if (cpu_vendor_id == CPU_VENDOR_AMD)
  337                 topo_probe_amd();
  338         else if (cpu_vendor_id == CPU_VENDOR_INTEL) {
  339                 /*
  340                  * See Intel(R) 64 Architecture Processor
  341                  * Topology Enumeration article for details.
  342                  *
  343                  * Note that 0x1 <= cpu_high < 4 case should be
  344                  * compatible with topo_probe_0x4() logic when
  345                  * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
  346                  * or it should trigger the fallback otherwise.
  347                  */
  348                 if (cpu_high >= 0xb)
  349                         topo_probe_0xb();
  350                 else if (cpu_high >= 0x1)
  351                         topo_probe_0x4();
  352         }
  353 
  354         /*
  355          * Fallback: assume each logical CPU is in separate
  356          * physical package.  That is, no multi-core, no SMT.
  357          */
  358         if (cpu_cores == 0 || cpu_logical == 0)
  359                 cpu_cores = cpu_logical = 1;
  360         cpu_topo_probed = 1;
  361 }
  362 
  363 struct cpu_group *
  364 cpu_topo(void)
  365 {
  366         int cg_flags;
  367 
  368         /*
  369          * Determine whether any threading flags are
  370          * necessry.
  371          */
  372         topo_probe();
  373         if (cpu_logical > 1 && hyperthreading_cpus)
  374                 cg_flags = CG_FLAG_HTT;
  375         else if (cpu_logical > 1)
  376                 cg_flags = CG_FLAG_SMT;
  377         else
  378                 cg_flags = 0;
  379         if (mp_ncpus % (cpu_cores * cpu_logical) != 0) {
  380                 printf("WARNING: Non-uniform processors.\n");
  381                 printf("WARNING: Using suboptimal topology.\n");
  382                 return (smp_topo_none());
  383         }
  384         /*
  385          * No multi-core or hyper-threaded.
  386          */
  387         if (cpu_logical * cpu_cores == 1)
  388                 return (smp_topo_none());
  389         /*
  390          * Only HTT no multi-core.
  391          */
  392         if (cpu_logical > 1 && cpu_cores == 1)
  393                 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags));
  394         /*
  395          * Only multi-core no HTT.
  396          */
  397         if (cpu_cores > 1 && cpu_logical == 1)
  398                 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags));
  399         /*
  400          * Both HTT and multi-core.
  401          */
  402         return (smp_topo_2level(CG_SHARE_L2, cpu_cores,
  403             CG_SHARE_L1, cpu_logical, cg_flags));
  404 }
  405 
  406 /*
  407  * Calculate usable address in base memory for AP trampoline code.
  408  */
  409 u_int
  410 mp_bootaddress(u_int basemem)
  411 {
  412 
  413         bootMP_size = mptramp_end - mptramp_start;
  414         boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
  415         if (((basemem * 1024) - boot_address) < bootMP_size)
  416                 boot_address -= PAGE_SIZE;      /* not enough, lower by 4k */
  417         /* 3 levels of page table pages */
  418         mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
  419 
  420         return mptramp_pagetables;
  421 }
  422 
  423 void
  424 cpu_add(u_int apic_id, char boot_cpu)
  425 {
  426 
  427         if (apic_id > MAX_APIC_ID) {
  428                 panic("SMP: APIC ID %d too high", apic_id);
  429                 return;
  430         }
  431         KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
  432             apic_id));
  433         cpu_info[apic_id].cpu_present = 1;
  434         if (boot_cpu) {
  435                 KASSERT(boot_cpu_id == -1,
  436                     ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
  437                     boot_cpu_id));
  438                 boot_cpu_id = apic_id;
  439                 cpu_info[apic_id].cpu_bsp = 1;
  440         }
  441         if (mp_ncpus < MAXCPU) {
  442                 mp_ncpus++;
  443                 mp_maxid = mp_ncpus -1;
  444         }
  445         if (bootverbose)
  446                 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
  447                     "AP");
  448 }
  449 
  450 void
  451 cpu_mp_setmaxid(void)
  452 {
  453 
  454         /*
  455          * mp_maxid should be already set by calls to cpu_add().
  456          * Just sanity check its value here.
  457          */
  458         if (mp_ncpus == 0)
  459                 KASSERT(mp_maxid == 0,
  460                     ("%s: mp_ncpus is zero, but mp_maxid is not", __func__));
  461         else if (mp_ncpus == 1)
  462                 mp_maxid = 0;
  463         else
  464                 KASSERT(mp_maxid >= mp_ncpus - 1,
  465                     ("%s: counters out of sync: max %d, count %d", __func__,
  466                         mp_maxid, mp_ncpus));           
  467 }
  468 
  469 int
  470 cpu_mp_probe(void)
  471 {
  472 
  473         /*
  474          * Always record BSP in CPU map so that the mbuf init code works
  475          * correctly.
  476          */
  477         all_cpus = 1;
  478         if (mp_ncpus == 0) {
  479                 /*
  480                  * No CPUs were found, so this must be a UP system.  Setup
  481                  * the variables to represent a system with a single CPU
  482                  * with an id of 0.
  483                  */
  484                 mp_ncpus = 1;
  485                 return (0);
  486         }
  487 
  488         /* At least one CPU was found. */
  489         if (mp_ncpus == 1) {
  490                 /*
  491                  * One CPU was found, so this must be a UP system with
  492                  * an I/O APIC.
  493                  */
  494                 mp_maxid = 0;
  495                 return (0);
  496         }
  497 
  498         /* At least two CPUs were found. */
  499         return (1);
  500 }
  501 
  502 /*
  503  * Initialize the IPI handlers and start up the AP's.
  504  */
  505 void
  506 cpu_mp_start(void)
  507 {
  508         int i;
  509 
  510         /* Initialize the logical ID to APIC ID table. */
  511         for (i = 0; i < MAXCPU; i++) {
  512                 cpu_apic_ids[i] = -1;
  513                 cpu_ipi_pending[i] = 0;
  514         }
  515 
  516         /* Install an inter-CPU IPI for TLB invalidation */
  517         setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0);
  518         setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0);
  519         setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0);
  520 
  521         /* Install an inter-CPU IPI for cache invalidation. */
  522         setidt(IPI_INVLCACHE, IDTVEC(invlcache), SDT_SYSIGT, SEL_KPL, 0);
  523 
  524         /* Install an inter-CPU IPI for all-CPU rendezvous */
  525         setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
  526 
  527         /* Install generic inter-CPU IPI handler */
  528         setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
  529                SDT_SYSIGT, SEL_KPL, 0);
  530 
  531         /* Install an inter-CPU IPI for CPU stop/restart */
  532         setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0);
  533 
  534         /* Install an inter-CPU IPI for CPU suspend/resume */
  535         setidt(IPI_SUSPEND, IDTVEC(cpususpend), SDT_SYSIGT, SEL_KPL, 0);
  536 
  537         /* Set boot_cpu_id if needed. */
  538         if (boot_cpu_id == -1) {
  539                 boot_cpu_id = PCPU_GET(apic_id);
  540                 cpu_info[boot_cpu_id].cpu_bsp = 1;
  541         } else
  542                 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
  543                     ("BSP's APIC ID doesn't match boot_cpu_id"));
  544 
  545         /* Probe logical/physical core configuration. */
  546         topo_probe();
  547 
  548         assign_cpu_ids();
  549 
  550         /* Start each Application Processor */
  551         start_all_aps();
  552 
  553         set_interrupt_apic_ids();
  554 }
  555 
  556 
  557 /*
  558  * Print various information about the SMP system hardware and setup.
  559  */
  560 void
  561 cpu_mp_announce(void)
  562 {
  563         const char *hyperthread;
  564         int i;
  565 
  566         printf("FreeBSD/SMP: %d package(s) x %d core(s)",
  567             mp_ncpus / (cpu_cores * cpu_logical), cpu_cores);
  568         if (hyperthreading_cpus > 1)
  569             printf(" x %d HTT threads", cpu_logical);
  570         else if (cpu_logical > 1)
  571             printf(" x %d SMT threads", cpu_logical);
  572         printf("\n");
  573 
  574         /* List active CPUs first. */
  575         printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id);
  576         for (i = 1; i < mp_ncpus; i++) {
  577                 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread)
  578                         hyperthread = "/HT";
  579                 else
  580                         hyperthread = "";
  581                 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread,
  582                     cpu_apic_ids[i]);
  583         }
  584 
  585         /* List disabled CPUs last. */
  586         for (i = 0; i <= MAX_APIC_ID; i++) {
  587                 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled)
  588                         continue;
  589                 if (cpu_info[i].cpu_hyperthread)
  590                         hyperthread = "/HT";
  591                 else
  592                         hyperthread = "";
  593                 printf("  cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread,
  594                     i);
  595         }
  596 }
  597 
  598 /*
  599  * AP CPU's call this to initialize themselves.
  600  */
  601 void
  602 init_secondary(void)
  603 {
  604         struct pcpu *pc;
  605         struct nmi_pcpu *np;
  606         u_int64_t msr, cr0;
  607         int cpu, gsel_tss, x;
  608         struct region_descriptor ap_gdt;
  609 
  610         /* Set by the startup code for us to use */
  611         cpu = bootAP;
  612 
  613         /* Init tss */
  614         common_tss[cpu] = common_tss[0];
  615         common_tss[cpu].tss_rsp0 = 0;   /* not used until after switch */
  616         common_tss[cpu].tss_iobase = sizeof(struct amd64tss) +
  617             IOPAGES * PAGE_SIZE;
  618         common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
  619 
  620         /* The NMI stack runs on IST2. */
  621         np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
  622         common_tss[cpu].tss_ist2 = (long) np;
  623 
  624         /* Prepare private GDT */
  625         gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu];
  626         for (x = 0; x < NGDT; x++) {
  627                 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) &&
  628                     x != GUSERLDT_SEL && x != (GUSERLDT_SEL + 1))
  629                         ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]);
  630         }
  631         ssdtosyssd(&gdt_segs[GPROC0_SEL],
  632             (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]);
  633         ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
  634         ap_gdt.rd_base =  (long) &gdt[NGDT * cpu];
  635         lgdt(&ap_gdt);                  /* does magic intra-segment return */
  636 
  637         /* Get per-cpu data */
  638         pc = &__pcpu[cpu];
  639 
  640         /* prime data page for it to use */
  641         pcpu_init(pc, cpu, sizeof(struct pcpu));
  642         dpcpu_init(dpcpu, cpu);
  643         pc->pc_apic_id = cpu_apic_ids[cpu];
  644         pc->pc_prvspace = pc;
  645         pc->pc_curthread = 0;
  646         pc->pc_tssp = &common_tss[cpu];
  647         pc->pc_commontssp = &common_tss[cpu];
  648         pc->pc_rsp0 = 0;
  649         pc->pc_tss = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
  650             GPROC0_SEL];
  651         pc->pc_fs32p = &gdt[NGDT * cpu + GUFS32_SEL];
  652         pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL];
  653         pc->pc_ldt = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
  654             GUSERLDT_SEL];
  655 
  656         /* Save the per-cpu pointer for use by the NMI handler. */
  657         np->np_pcpu = (register_t) pc;
  658 
  659         wrmsr(MSR_FSBASE, 0);           /* User value */
  660         wrmsr(MSR_GSBASE, (u_int64_t)pc);
  661         wrmsr(MSR_KGSBASE, (u_int64_t)pc);      /* XXX User value while we're in the kernel */
  662 
  663         lidt(&r_idt);
  664 
  665         gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
  666         ltr(gsel_tss);
  667 
  668         /*
  669          * Set to a known state:
  670          * Set by mpboot.s: CR0_PG, CR0_PE
  671          * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
  672          */
  673         cr0 = rcr0();
  674         cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
  675         load_cr0(cr0);
  676 
  677         /* Set up the fast syscall stuff */
  678         msr = rdmsr(MSR_EFER) | EFER_SCE;
  679         wrmsr(MSR_EFER, msr);
  680         wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
  681         wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
  682         msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
  683               ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
  684         wrmsr(MSR_STAR, msr);
  685         wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
  686 
  687         /* Disable local APIC just to be sure. */
  688         lapic_disable();
  689 
  690         /* signal our startup to the BSP. */
  691         mp_naps++;
  692 
  693         /* Spin until the BSP releases the AP's. */
  694         while (!aps_ready)
  695                 ia32_pause();
  696 
  697         /* Initialize the PAT MSR. */
  698         pmap_init_pat();
  699 
  700         /* set up CPU registers and state */
  701         cpu_setregs();
  702 
  703         /* set up SSE/NX registers */
  704         initializecpu();
  705 
  706         /* set up FPU state on the AP */
  707         fpuinit();
  708 
  709         /* A quick check from sanity claus */
  710         if (PCPU_GET(apic_id) != lapic_id()) {
  711                 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
  712                 printf("SMP: actual apic_id = %d\n", lapic_id());
  713                 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
  714                 panic("cpuid mismatch! boom!!");
  715         }
  716 
  717         /* Initialize curthread. */
  718         KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
  719         PCPU_SET(curthread, PCPU_GET(idlethread));
  720 
  721         mca_init();
  722 
  723         mtx_lock_spin(&ap_boot_mtx);
  724 
  725         /* Init local apic for irq's */
  726         lapic_setup(1);
  727 
  728         /* Set memory range attributes for this CPU to match the BSP */
  729         mem_range_AP_init();
  730 
  731         smp_cpus++;
  732 
  733         CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid));
  734         printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
  735 
  736         /* Determine if we are a logical CPU. */
  737         /* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */
  738         if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0)
  739                 logical_cpus_mask |= PCPU_GET(cpumask);
  740         
  741         /* Determine if we are a hyperthread. */
  742         if (hyperthreading_cpus > 1 &&
  743             PCPU_GET(apic_id) % hyperthreading_cpus != 0)
  744                 hyperthreading_cpus_mask |= PCPU_GET(cpumask);
  745 
  746         /* Build our map of 'other' CPUs. */
  747         PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
  748 
  749         if (bootverbose)
  750                 lapic_dump("AP");
  751 
  752         if (smp_cpus == mp_ncpus) {
  753                 /* enable IPI's, tlb shootdown, freezes etc */
  754                 atomic_store_rel_int(&smp_started, 1);
  755                 smp_active = 1;  /* historic */
  756         }
  757 
  758         /*
  759          * Enable global pages TLB extension
  760          * This also implicitly flushes the TLB 
  761          */
  762 
  763         load_cr4(rcr4() | CR4_PGE);
  764         load_ds(_udatasel);
  765         load_es(_udatasel);
  766         load_fs(_ufssel);
  767         mtx_unlock_spin(&ap_boot_mtx);
  768 
  769         /* wait until all the AP's are up */
  770         while (smp_started == 0)
  771                 ia32_pause();
  772 
  773         sched_throw(NULL);
  774 
  775         panic("scheduler returned us to %s", __func__);
  776         /* NOTREACHED */
  777 }
  778 
  779 /*******************************************************************
  780  * local functions and data
  781  */
  782 
  783 /*
  784  * We tell the I/O APIC code about all the CPUs we want to receive
  785  * interrupts.  If we don't want certain CPUs to receive IRQs we
  786  * can simply not tell the I/O APIC code about them in this function.
  787  * We also do not tell it about the BSP since it tells itself about
  788  * the BSP internally to work with UP kernels and on UP machines.
  789  */
  790 static void
  791 set_interrupt_apic_ids(void)
  792 {
  793         u_int i, apic_id;
  794 
  795         for (i = 0; i < MAXCPU; i++) {
  796                 apic_id = cpu_apic_ids[i];
  797                 if (apic_id == -1)
  798                         continue;
  799                 if (cpu_info[apic_id].cpu_bsp)
  800                         continue;
  801                 if (cpu_info[apic_id].cpu_disabled)
  802                         continue;
  803 
  804                 /* Don't let hyperthreads service interrupts. */
  805                 if (hyperthreading_cpus > 1 &&
  806                     apic_id % hyperthreading_cpus != 0)
  807                         continue;
  808 
  809                 intr_add_cpu(i);
  810         }
  811 }
  812 
  813 /*
  814  * Assign logical CPU IDs to local APICs.
  815  */
  816 static void
  817 assign_cpu_ids(void)
  818 {
  819         u_int i;
  820 
  821         TUNABLE_INT_FETCH("machdep.hyperthreading_allowed",
  822             &hyperthreading_allowed);
  823 
  824         /* Check for explicitly disabled CPUs. */
  825         for (i = 0; i <= MAX_APIC_ID; i++) {
  826                 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp)
  827                         continue;
  828 
  829                 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) {
  830                         cpu_info[i].cpu_hyperthread = 1;
  831 #if defined(SCHED_ULE)
  832                         /*
  833                          * Don't use HT CPU if it has been disabled by a
  834                          * tunable.
  835                          */
  836                         if (hyperthreading_allowed == 0) {
  837                                 cpu_info[i].cpu_disabled = 1;
  838                                 continue;
  839                         }
  840 #endif
  841                 }
  842 
  843                 /* Don't use this CPU if it has been disabled by a tunable. */
  844                 if (resource_disabled("lapic", i)) {
  845                         cpu_info[i].cpu_disabled = 1;
  846                         continue;
  847                 }
  848         }
  849 
  850         /*
  851          * Assign CPU IDs to local APIC IDs and disable any CPUs
  852          * beyond MAXCPU.  CPU 0 is always assigned to the BSP.
  853          *
  854          * To minimize confusion for userland, we attempt to number
  855          * CPUs such that all threads and cores in a package are
  856          * grouped together.  For now we assume that the BSP is always
  857          * the first thread in a package and just start adding APs
  858          * starting with the BSP's APIC ID.
  859          */
  860         mp_ncpus = 1;
  861         cpu_apic_ids[0] = boot_cpu_id;
  862         apic_cpuids[boot_cpu_id] = 0;
  863         for (i = boot_cpu_id + 1; i != boot_cpu_id;
  864              i == MAX_APIC_ID ? i = 0 : i++) {
  865                 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp ||
  866                     cpu_info[i].cpu_disabled)
  867                         continue;
  868 
  869                 if (mp_ncpus < MAXCPU) {
  870                         cpu_apic_ids[mp_ncpus] = i;
  871                         apic_cpuids[i] = mp_ncpus;
  872                         mp_ncpus++;
  873                 } else
  874                         cpu_info[i].cpu_disabled = 1;
  875         }
  876         KASSERT(mp_maxid >= mp_ncpus - 1,
  877             ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
  878             mp_ncpus));         
  879 }
  880 
  881 /*
  882  * start each AP in our list
  883  */
  884 static int
  885 start_all_aps(void)
  886 {
  887         vm_offset_t va = boot_address + KERNBASE;
  888         u_int64_t *pt4, *pt3, *pt2;
  889         u_int32_t mpbioswarmvec;
  890         int apic_id, cpu, i;
  891         u_char mpbiosreason;
  892 
  893         mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
  894 
  895         /* install the AP 1st level boot code */
  896         pmap_kenter(va, boot_address);
  897         pmap_invalidate_page(kernel_pmap, va);
  898         bcopy(mptramp_start, (void *)va, bootMP_size);
  899 
  900         /* Locate the page tables, they'll be below the trampoline */
  901         pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
  902         pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
  903         pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
  904 
  905         /* Create the initial 1GB replicated page tables */
  906         for (i = 0; i < 512; i++) {
  907                 /* Each slot of the level 4 pages points to the same level 3 page */
  908                 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
  909                 pt4[i] |= PG_V | PG_RW | PG_U;
  910 
  911                 /* Each slot of the level 3 pages points to the same level 2 page */
  912                 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
  913                 pt3[i] |= PG_V | PG_RW | PG_U;
  914 
  915                 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
  916                 pt2[i] = i * (2 * 1024 * 1024);
  917                 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
  918         }
  919 
  920         /* save the current value of the warm-start vector */
  921         mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
  922         outb(CMOS_REG, BIOS_RESET);
  923         mpbiosreason = inb(CMOS_DATA);
  924 
  925         /* setup a vector to our boot code */
  926         *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
  927         *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
  928         outb(CMOS_REG, BIOS_RESET);
  929         outb(CMOS_DATA, BIOS_WARM);     /* 'warm-start' */
  930 
  931         /* start each AP */
  932         for (cpu = 1; cpu < mp_ncpus; cpu++) {
  933                 apic_id = cpu_apic_ids[cpu];
  934 
  935                 /* allocate and set up an idle stack data page */
  936                 bootstacks[cpu] = (void *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE);
  937                 doublefault_stack = (char *)kmem_alloc(kernel_map, PAGE_SIZE);
  938                 nmi_stack = (char *)kmem_alloc(kernel_map, PAGE_SIZE);
  939                 dpcpu = (void *)kmem_alloc(kernel_map, DPCPU_SIZE);
  940 
  941                 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 8;
  942                 bootAP = cpu;
  943 
  944                 /* attempt to start the Application Processor */
  945                 if (!start_ap(apic_id)) {
  946                         /* restore the warmstart vector */
  947                         *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
  948                         panic("AP #%d (PHY# %d) failed!", cpu, apic_id);
  949                 }
  950 
  951                 all_cpus |= (1 << cpu);         /* record AP in CPU map */
  952         }
  953 
  954         /* build our map of 'other' CPUs */
  955         PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
  956 
  957         /* restore the warmstart vector */
  958         *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
  959 
  960         outb(CMOS_REG, BIOS_RESET);
  961         outb(CMOS_DATA, mpbiosreason);
  962 
  963         /* number of APs actually started */
  964         return mp_naps;
  965 }
  966 
  967 
  968 /*
  969  * This function starts the AP (application processor) identified
  970  * by the APIC ID 'physicalCpu'.  It does quite a "song and dance"
  971  * to accomplish this.  This is necessary because of the nuances
  972  * of the different hardware we might encounter.  It isn't pretty,
  973  * but it seems to work.
  974  */
  975 static int
  976 start_ap(int apic_id)
  977 {
  978         int vector, ms;
  979         int cpus;
  980 
  981         /* calculate the vector */
  982         vector = (boot_address >> 12) & 0xff;
  983 
  984         /* used as a watchpoint to signal AP startup */
  985         cpus = mp_naps;
  986 
  987         /*
  988          * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
  989          * and running the target CPU. OR this INIT IPI might be latched (P5
  990          * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
  991          * ignored.
  992          */
  993 
  994         /* do an INIT IPI: assert RESET */
  995         lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
  996             APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
  997 
  998         /* wait for pending status end */
  999         lapic_ipi_wait(-1);
 1000 
 1001         /* do an INIT IPI: deassert RESET */
 1002         lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL |
 1003             APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0);
 1004 
 1005         /* wait for pending status end */
 1006         DELAY(10000);           /* wait ~10mS */
 1007         lapic_ipi_wait(-1);
 1008 
 1009         /*
 1010          * next we do a STARTUP IPI: the previous INIT IPI might still be
 1011          * latched, (P5 bug) this 1st STARTUP would then terminate
 1012          * immediately, and the previously started INIT IPI would continue. OR
 1013          * the previous INIT IPI has already run. and this STARTUP IPI will
 1014          * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
 1015          * will run.
 1016          */
 1017 
 1018         /* do a STARTUP IPI */
 1019         lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
 1020             APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
 1021             vector, apic_id);
 1022         lapic_ipi_wait(-1);
 1023         DELAY(200);             /* wait ~200uS */
 1024 
 1025         /*
 1026          * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
 1027          * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
 1028          * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
 1029          * recognized after hardware RESET or INIT IPI.
 1030          */
 1031 
 1032         lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
 1033             APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
 1034             vector, apic_id);
 1035         lapic_ipi_wait(-1);
 1036         DELAY(200);             /* wait ~200uS */
 1037 
 1038         /* Wait up to 5 seconds for it to start. */
 1039         for (ms = 0; ms < 5000; ms++) {
 1040                 if (mp_naps > cpus)
 1041                         return 1;       /* return SUCCESS */
 1042                 DELAY(1000);
 1043         }
 1044         return 0;               /* return FAILURE */
 1045 }
 1046 
 1047 /*
 1048  * Flush the TLB on all other CPU's
 1049  */
 1050 static void
 1051 smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
 1052 {
 1053         u_int ncpu;
 1054 
 1055         ncpu = mp_ncpus - 1;    /* does not shootdown self */
 1056         if (ncpu < 1)
 1057                 return;         /* no other cpus */
 1058         if (!(read_rflags() & PSL_I))
 1059                 panic("%s: interrupts disabled", __func__);
 1060         mtx_lock_spin(&smp_ipi_mtx);
 1061         smp_tlb_addr1 = addr1;
 1062         smp_tlb_addr2 = addr2;
 1063         atomic_store_rel_int(&smp_tlb_wait, 0);
 1064         ipi_all_but_self(vector);
 1065         while (smp_tlb_wait < ncpu)
 1066                 ia32_pause();
 1067         mtx_unlock_spin(&smp_ipi_mtx);
 1068 }
 1069 
 1070 static void
 1071 smp_targeted_tlb_shootdown(cpumask_t mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
 1072 {
 1073         int ncpu, othercpus;
 1074 
 1075         othercpus = mp_ncpus - 1;
 1076         if (mask == (cpumask_t)-1) {
 1077                 ncpu = othercpus;
 1078                 if (ncpu < 1)
 1079                         return;
 1080         } else {
 1081                 mask &= ~PCPU_GET(cpumask);
 1082                 if (mask == 0)
 1083                         return;
 1084                 ncpu = bitcount32(mask);
 1085                 if (ncpu > othercpus) {
 1086                         /* XXX this should be a panic offence */
 1087                         printf("SMP: tlb shootdown to %d other cpus (only have %d)\n",
 1088                             ncpu, othercpus);
 1089                         ncpu = othercpus;
 1090                 }
 1091                 /* XXX should be a panic, implied by mask == 0 above */
 1092                 if (ncpu < 1)
 1093                         return;
 1094         }
 1095         if (!(read_rflags() & PSL_I))
 1096                 panic("%s: interrupts disabled", __func__);
 1097         mtx_lock_spin(&smp_ipi_mtx);
 1098         smp_tlb_addr1 = addr1;
 1099         smp_tlb_addr2 = addr2;
 1100         atomic_store_rel_int(&smp_tlb_wait, 0);
 1101         if (mask == (cpumask_t)-1)
 1102                 ipi_all_but_self(vector);
 1103         else
 1104                 ipi_selected(mask, vector);
 1105         while (smp_tlb_wait < ncpu)
 1106                 ia32_pause();
 1107         mtx_unlock_spin(&smp_ipi_mtx);
 1108 }
 1109 
 1110 /*
 1111  * Send an IPI to specified CPU handling the bitmap logic.
 1112  */
 1113 static void
 1114 ipi_send_cpu(int cpu, u_int ipi)
 1115 {
 1116         u_int bitmap, old_pending, new_pending;
 1117 
 1118         KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu));
 1119 
 1120         if (IPI_IS_BITMAPED(ipi)) {
 1121                 bitmap = 1 << ipi;
 1122                 ipi = IPI_BITMAP_VECTOR;
 1123                 do {
 1124                         old_pending = cpu_ipi_pending[cpu];
 1125                         new_pending = old_pending | bitmap;
 1126                 } while  (!atomic_cmpset_int(&cpu_ipi_pending[cpu],
 1127                     old_pending, new_pending)); 
 1128                 if (old_pending)
 1129                         return;
 1130         }
 1131         lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
 1132 }
 1133 
 1134 void
 1135 smp_cache_flush(void)
 1136 {
 1137 
 1138         if (smp_started)
 1139                 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0);
 1140 }
 1141 
 1142 void
 1143 smp_invltlb(void)
 1144 {
 1145 
 1146         if (smp_started) {
 1147                 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
 1148         }
 1149 }
 1150 
 1151 void
 1152 smp_invlpg(vm_offset_t addr)
 1153 {
 1154 
 1155         if (smp_started)
 1156                 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
 1157 }
 1158 
 1159 void
 1160 smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
 1161 {
 1162 
 1163         if (smp_started) {
 1164                 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
 1165         }
 1166 }
 1167 
 1168 void
 1169 smp_masked_invltlb(cpumask_t mask)
 1170 {
 1171 
 1172         if (smp_started) {
 1173                 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
 1174         }
 1175 }
 1176 
 1177 void
 1178 smp_masked_invlpg(cpumask_t mask, vm_offset_t addr)
 1179 {
 1180 
 1181         if (smp_started) {
 1182                 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
 1183         }
 1184 }
 1185 
 1186 void
 1187 smp_masked_invlpg_range(cpumask_t mask, vm_offset_t addr1, vm_offset_t addr2)
 1188 {
 1189 
 1190         if (smp_started) {
 1191                 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
 1192         }
 1193 }
 1194 
 1195 void
 1196 ipi_bitmap_handler(struct trapframe frame)
 1197 {
 1198         int cpu = PCPU_GET(cpuid);
 1199         u_int ipi_bitmap;
 1200 
 1201         ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
 1202 
 1203         if (ipi_bitmap & (1 << IPI_PREEMPT))
 1204                 sched_preempt(curthread);
 1205 
 1206         /* Nothing to do for AST */
 1207 
 1208         if (ipi_bitmap & (1 << IPI_HARDCLOCK))
 1209                 hardclockintr(&frame);
 1210 
 1211         if (ipi_bitmap & (1 << IPI_STATCLOCK))
 1212                 statclockintr(&frame);
 1213 
 1214         if (ipi_bitmap & (1 << IPI_PROFCLOCK))
 1215                 profclockintr(&frame);
 1216 }
 1217 
 1218 /*
 1219  * send an IPI to a set of cpus.
 1220  */
 1221 void
 1222 ipi_selected(cpumask_t cpus, u_int ipi)
 1223 {
 1224         int cpu;
 1225 
 1226         /*
 1227          * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
 1228          * of help in order to understand what is the source.
 1229          * Set the mask of receiving CPUs for this purpose.
 1230          */
 1231         if (ipi == IPI_STOP_HARD)
 1232                 atomic_set_int(&ipi_nmi_pending, cpus);
 1233 
 1234         CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi);
 1235         while ((cpu = ffs(cpus)) != 0) {
 1236                 cpu--;
 1237                 cpus &= ~(1 << cpu);
 1238                 ipi_send_cpu(cpu, ipi);
 1239         }
 1240 }
 1241 
 1242 /*
 1243  * send an IPI to a specific CPU.
 1244  */
 1245 void
 1246 ipi_cpu(int cpu, u_int ipi)
 1247 {
 1248 
 1249         /*
 1250          * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
 1251          * of help in order to understand what is the source.
 1252          * Set the mask of receiving CPUs for this purpose.
 1253          */
 1254         if (ipi == IPI_STOP_HARD)
 1255                 atomic_set_int(&ipi_nmi_pending, 1 << cpu);
 1256 
 1257         CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
 1258         ipi_send_cpu(cpu, ipi);
 1259 }
 1260 
 1261 /*
 1262  * send an IPI to all CPUs EXCEPT myself
 1263  */
 1264 void
 1265 ipi_all_but_self(u_int ipi)
 1266 {
 1267 
 1268         if (IPI_IS_BITMAPED(ipi)) {
 1269                 ipi_selected(PCPU_GET(other_cpus), ipi);
 1270                 return;
 1271         }
 1272 
 1273         /*
 1274          * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
 1275          * of help in order to understand what is the source.
 1276          * Set the mask of receiving CPUs for this purpose.
 1277          */
 1278         if (ipi == IPI_STOP_HARD)
 1279                 atomic_set_int(&ipi_nmi_pending, PCPU_GET(other_cpus));
 1280 
 1281         CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
 1282         lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
 1283 }
 1284 
 1285 int
 1286 ipi_nmi_handler()
 1287 {
 1288         cpumask_t cpumask;
 1289 
 1290         /*
 1291          * As long as there is not a simple way to know about a NMI's
 1292          * source, if the bitmask for the current CPU is present in
 1293          * the global pending bitword an IPI_STOP_HARD has been issued
 1294          * and should be handled.
 1295          */
 1296         cpumask = PCPU_GET(cpumask);
 1297         if ((ipi_nmi_pending & cpumask) == 0)
 1298                 return (1);
 1299 
 1300         atomic_clear_int(&ipi_nmi_pending, cpumask);
 1301         cpustop_handler();
 1302         return (0);
 1303 }
 1304      
 1305 /*
 1306  * Handle an IPI_STOP by saving our current context and spinning until we
 1307  * are resumed.
 1308  */
 1309 void
 1310 cpustop_handler(void)
 1311 {
 1312         cpumask_t cpumask;
 1313         u_int cpu;
 1314 
 1315         cpu = PCPU_GET(cpuid);
 1316         cpumask = PCPU_GET(cpumask);
 1317 
 1318         savectx(&stoppcbs[cpu]);
 1319 
 1320         /* Indicate that we are stopped */
 1321         atomic_set_int(&stopped_cpus, cpumask);
 1322 
 1323         /* Wait for restart */
 1324         while (!(started_cpus & cpumask))
 1325             ia32_pause();
 1326 
 1327         atomic_clear_int(&started_cpus, cpumask);
 1328         atomic_clear_int(&stopped_cpus, cpumask);
 1329 
 1330         if (cpu == 0 && cpustop_restartfunc != NULL) {
 1331                 cpustop_restartfunc();
 1332                 cpustop_restartfunc = NULL;
 1333         }
 1334 }
 1335 
 1336 /*
 1337  * Handle an IPI_SUSPEND by saving our current context and spinning until we
 1338  * are resumed.
 1339  */
 1340 void
 1341 cpususpend_handler(void)
 1342 {
 1343         cpumask_t cpumask;
 1344         register_t cr3, rf;
 1345         u_int cpu;
 1346 
 1347         cpu = PCPU_GET(cpuid);
 1348         cpumask = PCPU_GET(cpumask);
 1349 
 1350         rf = intr_disable();
 1351         cr3 = rcr3();
 1352 
 1353         if (savectx(susppcbs[cpu])) {
 1354                 wbinvd();
 1355                 atomic_set_int(&stopped_cpus, cpumask);
 1356         } else {
 1357                 pmap_init_pat();
 1358                 PCPU_SET(switchtime, 0);
 1359                 PCPU_SET(switchticks, ticks);
 1360         }
 1361 
 1362         /* Wait for resume */
 1363         while (!(started_cpus & cpumask))
 1364                 ia32_pause();
 1365 
 1366         atomic_clear_int(&started_cpus, cpumask);
 1367         atomic_clear_int(&stopped_cpus, cpumask);
 1368 
 1369         /* Restore CR3 and enable interrupts */
 1370         load_cr3(cr3);
 1371         mca_resume();
 1372         lapic_setup(0);
 1373         intr_restore(rf);
 1374 }
 1375 
 1376 /*
 1377  * This is called once the rest of the system is up and running and we're
 1378  * ready to let the AP's out of the pen.
 1379  */
 1380 static void
 1381 release_aps(void *dummy __unused)
 1382 {
 1383 
 1384         if (mp_ncpus == 1) 
 1385                 return;
 1386         atomic_store_rel_int(&aps_ready, 1);
 1387         while (smp_started == 0)
 1388                 ia32_pause();
 1389 }
 1390 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
 1391 
 1392 static int
 1393 sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS)
 1394 {
 1395         cpumask_t mask;
 1396         int error;
 1397 
 1398         mask = hlt_cpus_mask;
 1399         error = sysctl_handle_int(oidp, &mask, 0, req);
 1400         if (error || !req->newptr)
 1401                 return (error);
 1402 
 1403         if (logical_cpus_mask != 0 &&
 1404             (mask & logical_cpus_mask) == logical_cpus_mask)
 1405                 hlt_logical_cpus = 1;
 1406         else
 1407                 hlt_logical_cpus = 0;
 1408 
 1409         if (! hyperthreading_allowed)
 1410                 mask |= hyperthreading_cpus_mask;
 1411 
 1412         if ((mask & all_cpus) == all_cpus)
 1413                 mask &= ~(1<<0);
 1414         hlt_cpus_mask = mask;
 1415         return (error);
 1416 }
 1417 SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW,
 1418     0, 0, sysctl_hlt_cpus, "IU",
 1419     "Bitmap of CPUs to halt.  101 (binary) will halt CPUs 0 and 2.");
 1420 
 1421 static int
 1422 sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS)
 1423 {
 1424         int disable, error;
 1425 
 1426         disable = hlt_logical_cpus;
 1427         error = sysctl_handle_int(oidp, &disable, 0, req);
 1428         if (error || !req->newptr)
 1429                 return (error);
 1430 
 1431         if (disable)
 1432                 hlt_cpus_mask |= logical_cpus_mask;
 1433         else
 1434                 hlt_cpus_mask &= ~logical_cpus_mask;
 1435 
 1436         if (! hyperthreading_allowed)
 1437                 hlt_cpus_mask |= hyperthreading_cpus_mask;
 1438 
 1439         if ((hlt_cpus_mask & all_cpus) == all_cpus)
 1440                 hlt_cpus_mask &= ~(1<<0);
 1441 
 1442         hlt_logical_cpus = disable;
 1443         return (error);
 1444 }
 1445 
 1446 static int
 1447 sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS)
 1448 {
 1449         int allowed, error;
 1450 
 1451         allowed = hyperthreading_allowed;
 1452         error = sysctl_handle_int(oidp, &allowed, 0, req);
 1453         if (error || !req->newptr)
 1454                 return (error);
 1455 
 1456 #ifdef SCHED_ULE
 1457         /*
 1458          * SCHED_ULE doesn't allow enabling/disabling HT cores at
 1459          * run-time.
 1460          */
 1461         if (allowed != hyperthreading_allowed)
 1462                 return (ENOTSUP);
 1463         return (error);
 1464 #endif
 1465 
 1466         if (allowed)
 1467                 hlt_cpus_mask &= ~hyperthreading_cpus_mask;
 1468         else
 1469                 hlt_cpus_mask |= hyperthreading_cpus_mask;
 1470 
 1471         if (logical_cpus_mask != 0 &&
 1472             (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask)
 1473                 hlt_logical_cpus = 1;
 1474         else
 1475                 hlt_logical_cpus = 0;
 1476 
 1477         if ((hlt_cpus_mask & all_cpus) == all_cpus)
 1478                 hlt_cpus_mask &= ~(1<<0);
 1479 
 1480         hyperthreading_allowed = allowed;
 1481         return (error);
 1482 }
 1483 
 1484 static void
 1485 cpu_hlt_setup(void *dummy __unused)
 1486 {
 1487 
 1488         if (logical_cpus_mask != 0) {
 1489                 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus",
 1490                     &hlt_logical_cpus);
 1491                 sysctl_ctx_init(&logical_cpu_clist);
 1492                 SYSCTL_ADD_PROC(&logical_cpu_clist,
 1493                     SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
 1494                     "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0,
 1495                     sysctl_hlt_logical_cpus, "IU", "");
 1496                 SYSCTL_ADD_UINT(&logical_cpu_clist,
 1497                     SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
 1498                     "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD,
 1499                     &logical_cpus_mask, 0, "");
 1500 
 1501                 if (hlt_logical_cpus)
 1502                         hlt_cpus_mask |= logical_cpus_mask;
 1503 
 1504                 /*
 1505                  * If necessary for security purposes, force
 1506                  * hyperthreading off, regardless of the value
 1507                  * of hlt_logical_cpus.
 1508                  */
 1509                 if (hyperthreading_cpus_mask) {
 1510                         SYSCTL_ADD_PROC(&logical_cpu_clist,
 1511                             SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
 1512                             "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW,
 1513                             0, 0, sysctl_hyperthreading_allowed, "IU", "");
 1514                         if (! hyperthreading_allowed)
 1515                                 hlt_cpus_mask |= hyperthreading_cpus_mask;
 1516                 }
 1517         }
 1518 }
 1519 SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL);
 1520 
 1521 int
 1522 mp_grab_cpu_hlt(void)
 1523 {
 1524         cpumask_t mask;
 1525 #ifdef MP_WATCHDOG
 1526         u_int cpuid;
 1527 #endif
 1528         int retval;
 1529 
 1530         mask = PCPU_GET(cpumask);
 1531 #ifdef MP_WATCHDOG
 1532         cpuid = PCPU_GET(cpuid);
 1533         ap_watchdog(cpuid);
 1534 #endif
 1535 
 1536         retval = 0;
 1537         while (mask & hlt_cpus_mask) {
 1538                 retval = 1;
 1539                 __asm __volatile("sti; hlt" : : : "memory");
 1540         }
 1541         return (retval);
 1542 }

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