The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/amd64/amd64/mp_machdep.c

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    1 /*-
    2  * Copyright (c) 1996, by Steve Passe
    3  * Copyright (c) 2003, by Peter Wemm
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. The name of the developer may NOT be used to endorse or promote products
   12  *    derived from this software without specific prior written permission.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD: releng/9.0/sys/amd64/amd64/mp_machdep.c 223758 2011-07-04 12:04:52Z attilio $");
   29 
   30 #include "opt_cpu.h"
   31 #include "opt_kstack_pages.h"
   32 #include "opt_sched.h"
   33 #include "opt_smp.h"
   34 
   35 #include <sys/param.h>
   36 #include <sys/systm.h>
   37 #include <sys/bus.h>
   38 #include <sys/cpuset.h>
   39 #ifdef GPROF 
   40 #include <sys/gmon.h>
   41 #endif
   42 #include <sys/kernel.h>
   43 #include <sys/ktr.h>
   44 #include <sys/lock.h>
   45 #include <sys/malloc.h>
   46 #include <sys/memrange.h>
   47 #include <sys/mutex.h>
   48 #include <sys/pcpu.h>
   49 #include <sys/proc.h>
   50 #include <sys/sched.h>
   51 #include <sys/smp.h>
   52 #include <sys/sysctl.h>
   53 
   54 #include <vm/vm.h>
   55 #include <vm/vm_param.h>
   56 #include <vm/pmap.h>
   57 #include <vm/vm_kern.h>
   58 #include <vm/vm_extern.h>
   59 
   60 #include <x86/apicreg.h>
   61 #include <machine/clock.h>
   62 #include <machine/cputypes.h>
   63 #include <machine/cpufunc.h>
   64 #include <x86/mca.h>
   65 #include <machine/md_var.h>
   66 #include <machine/pcb.h>
   67 #include <machine/psl.h>
   68 #include <machine/smp.h>
   69 #include <machine/specialreg.h>
   70 #include <machine/tss.h>
   71 
   72 #define WARMBOOT_TARGET         0
   73 #define WARMBOOT_OFF            (KERNBASE + 0x0467)
   74 #define WARMBOOT_SEG            (KERNBASE + 0x0469)
   75 
   76 #define CMOS_REG                (0x70)
   77 #define CMOS_DATA               (0x71)
   78 #define BIOS_RESET              (0x0f)
   79 #define BIOS_WARM               (0x0a)
   80 
   81 /* lock region used by kernel profiling */
   82 int     mcount_lock;
   83 
   84 int     mp_naps;                /* # of Applications processors */
   85 int     boot_cpu_id = -1;       /* designated BSP */
   86 
   87 extern  struct pcpu __pcpu[];
   88 
   89 /* AP uses this during bootstrap.  Do not staticize.  */
   90 char *bootSTK;
   91 static int bootAP;
   92 
   93 /* Free these after use */
   94 void *bootstacks[MAXCPU];
   95 
   96 /* Temporary variables for init_secondary()  */
   97 char *doublefault_stack;
   98 char *nmi_stack;
   99 void *dpcpu;
  100 
  101 struct pcb stoppcbs[MAXCPU];
  102 struct pcb **susppcbs = NULL;
  103 
  104 /* Variables needed for SMP tlb shootdown. */
  105 vm_offset_t smp_tlb_addr1;
  106 vm_offset_t smp_tlb_addr2;
  107 volatile int smp_tlb_wait;
  108 
  109 #ifdef COUNT_IPIS
  110 /* Interrupt counts. */
  111 static u_long *ipi_preempt_counts[MAXCPU];
  112 static u_long *ipi_ast_counts[MAXCPU];
  113 u_long *ipi_invltlb_counts[MAXCPU];
  114 u_long *ipi_invlrng_counts[MAXCPU];
  115 u_long *ipi_invlpg_counts[MAXCPU];
  116 u_long *ipi_invlcache_counts[MAXCPU];
  117 u_long *ipi_rendezvous_counts[MAXCPU];
  118 static u_long *ipi_hardclock_counts[MAXCPU];
  119 #endif
  120 
  121 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
  122 
  123 /*
  124  * Local data and functions.
  125  */
  126 
  127 static volatile cpuset_t ipi_nmi_pending;
  128 
  129 /* used to hold the AP's until we are ready to release them */
  130 static struct mtx ap_boot_mtx;
  131 
  132 /* Set to 1 once we're ready to let the APs out of the pen. */
  133 static volatile int aps_ready = 0;
  134 
  135 /*
  136  * Store data from cpu_add() until later in the boot when we actually setup
  137  * the APs.
  138  */
  139 struct cpu_info {
  140         int     cpu_present:1;
  141         int     cpu_bsp:1;
  142         int     cpu_disabled:1;
  143         int     cpu_hyperthread:1;
  144 } static cpu_info[MAX_APIC_ID + 1];
  145 int cpu_apic_ids[MAXCPU];
  146 int apic_cpuids[MAX_APIC_ID + 1];
  147 
  148 /* Holds pending bitmap based IPIs per CPU */
  149 static volatile u_int cpu_ipi_pending[MAXCPU];
  150 
  151 static u_int boot_address;
  152 static int cpu_logical;                 /* logical cpus per core */
  153 static int cpu_cores;                   /* cores per package */
  154 
  155 static void     assign_cpu_ids(void);
  156 static void     set_interrupt_apic_ids(void);
  157 static int      start_all_aps(void);
  158 static int      start_ap(int apic_id);
  159 static void     release_aps(void *dummy);
  160 
  161 static u_int    hyperthreading_cpus;    /* logical cpus sharing L1 cache */
  162 static int      hyperthreading_allowed = 1;
  163 static u_int    bootMP_size;
  164 
  165 static void
  166 mem_range_AP_init(void)
  167 {
  168         if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
  169                 mem_range_softc.mr_op->initAP(&mem_range_softc);
  170 }
  171 
  172 static void
  173 topo_probe_amd(void)
  174 {
  175         int core_id_bits;
  176         int id;
  177 
  178         /* AMD processors do not support HTT. */
  179         cpu_logical = 1;
  180 
  181         if ((amd_feature2 & AMDID2_CMP) == 0) {
  182                 cpu_cores = 1;
  183                 return;
  184         }
  185 
  186         core_id_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >>
  187             AMDID_COREID_SIZE_SHIFT;
  188         if (core_id_bits == 0) {
  189                 cpu_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
  190                 return;
  191         }
  192 
  193         /* Fam 10h and newer should get here. */
  194         for (id = 0; id <= MAX_APIC_ID; id++) {
  195                 /* Check logical CPU availability. */
  196                 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
  197                         continue;
  198                 /* Check if logical CPU has the same package ID. */
  199                 if ((id >> core_id_bits) != (boot_cpu_id >> core_id_bits))
  200                         continue;
  201                 cpu_cores++;
  202         }
  203 }
  204 
  205 /*
  206  * Round up to the next power of two, if necessary, and then
  207  * take log2.
  208  * Returns -1 if argument is zero.
  209  */
  210 static __inline int
  211 mask_width(u_int x)
  212 {
  213 
  214         return (fls(x << (1 - powerof2(x))) - 1);
  215 }
  216 
  217 static void
  218 topo_probe_0x4(void)
  219 {
  220         u_int p[4];
  221         int pkg_id_bits;
  222         int core_id_bits;
  223         int max_cores;
  224         int max_logical;
  225         int id;
  226 
  227         /* Both zero and one here mean one logical processor per package. */
  228         max_logical = (cpu_feature & CPUID_HTT) != 0 ?
  229             (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
  230         if (max_logical <= 1)
  231                 return;
  232 
  233         /*
  234          * Because of uniformity assumption we examine only
  235          * those logical processors that belong to the same
  236          * package as BSP.  Further, we count number of
  237          * logical processors that belong to the same core
  238          * as BSP thus deducing number of threads per core.
  239          */
  240         if (cpu_high >= 0x4) {
  241                 cpuid_count(0x04, 0, p);
  242                 max_cores = ((p[0] >> 26) & 0x3f) + 1;
  243         } else
  244                 max_cores = 1;
  245         core_id_bits = mask_width(max_logical/max_cores);
  246         if (core_id_bits < 0)
  247                 return;
  248         pkg_id_bits = core_id_bits + mask_width(max_cores);
  249 
  250         for (id = 0; id <= MAX_APIC_ID; id++) {
  251                 /* Check logical CPU availability. */
  252                 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
  253                         continue;
  254                 /* Check if logical CPU has the same package ID. */
  255                 if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits))
  256                         continue;
  257                 cpu_cores++;
  258                 /* Check if logical CPU has the same package and core IDs. */
  259                 if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits))
  260                         cpu_logical++;
  261         }
  262 
  263         KASSERT(cpu_cores >= 1 && cpu_logical >= 1,
  264             ("topo_probe_0x4 couldn't find BSP"));
  265 
  266         cpu_cores /= cpu_logical;
  267         hyperthreading_cpus = cpu_logical;
  268 }
  269 
  270 static void
  271 topo_probe_0xb(void)
  272 {
  273         u_int p[4];
  274         int bits;
  275         int cnt;
  276         int i;
  277         int logical;
  278         int type;
  279         int x;
  280 
  281         /* We only support three levels for now. */
  282         for (i = 0; i < 3; i++) {
  283                 cpuid_count(0x0b, i, p);
  284 
  285                 /* Fall back if CPU leaf 11 doesn't really exist. */
  286                 if (i == 0 && p[1] == 0) {
  287                         topo_probe_0x4();
  288                         return;
  289                 }
  290 
  291                 bits = p[0] & 0x1f;
  292                 logical = p[1] &= 0xffff;
  293                 type = (p[2] >> 8) & 0xff;
  294                 if (type == 0 || logical == 0)
  295                         break;
  296                 /*
  297                  * Because of uniformity assumption we examine only
  298                  * those logical processors that belong to the same
  299                  * package as BSP.
  300                  */
  301                 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) {
  302                         if (!cpu_info[x].cpu_present ||
  303                             cpu_info[x].cpu_disabled)
  304                                 continue;
  305                         if (x >> bits == boot_cpu_id >> bits)
  306                                 cnt++;
  307                 }
  308                 if (type == CPUID_TYPE_SMT)
  309                         cpu_logical = cnt;
  310                 else if (type == CPUID_TYPE_CORE)
  311                         cpu_cores = cnt;
  312         }
  313         if (cpu_logical == 0)
  314                 cpu_logical = 1;
  315         cpu_cores /= cpu_logical;
  316 }
  317 
  318 /*
  319  * Both topology discovery code and code that consumes topology
  320  * information assume top-down uniformity of the topology.
  321  * That is, all physical packages must be identical and each
  322  * core in a package must have the same number of threads.
  323  * Topology information is queried only on BSP, on which this
  324  * code runs and for which it can query CPUID information.
  325  * Then topology is extrapolated on all packages using the
  326  * uniformity assumption.
  327  */
  328 static void
  329 topo_probe(void)
  330 {
  331         static int cpu_topo_probed = 0;
  332 
  333         if (cpu_topo_probed)
  334                 return;
  335 
  336         CPU_ZERO(&logical_cpus_mask);
  337         if (mp_ncpus <= 1)
  338                 cpu_cores = cpu_logical = 1;
  339         else if (cpu_vendor_id == CPU_VENDOR_AMD)
  340                 topo_probe_amd();
  341         else if (cpu_vendor_id == CPU_VENDOR_INTEL) {
  342                 /*
  343                  * See Intel(R) 64 Architecture Processor
  344                  * Topology Enumeration article for details.
  345                  *
  346                  * Note that 0x1 <= cpu_high < 4 case should be
  347                  * compatible with topo_probe_0x4() logic when
  348                  * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
  349                  * or it should trigger the fallback otherwise.
  350                  */
  351                 if (cpu_high >= 0xb)
  352                         topo_probe_0xb();
  353                 else if (cpu_high >= 0x1)
  354                         topo_probe_0x4();
  355         }
  356 
  357         /*
  358          * Fallback: assume each logical CPU is in separate
  359          * physical package.  That is, no multi-core, no SMT.
  360          */
  361         if (cpu_cores == 0 || cpu_logical == 0)
  362                 cpu_cores = cpu_logical = 1;
  363         cpu_topo_probed = 1;
  364 }
  365 
  366 struct cpu_group *
  367 cpu_topo(void)
  368 {
  369         int cg_flags;
  370 
  371         /*
  372          * Determine whether any threading flags are
  373          * necessry.
  374          */
  375         topo_probe();
  376         if (cpu_logical > 1 && hyperthreading_cpus)
  377                 cg_flags = CG_FLAG_HTT;
  378         else if (cpu_logical > 1)
  379                 cg_flags = CG_FLAG_SMT;
  380         else
  381                 cg_flags = 0;
  382         if (mp_ncpus % (cpu_cores * cpu_logical) != 0) {
  383                 printf("WARNING: Non-uniform processors.\n");
  384                 printf("WARNING: Using suboptimal topology.\n");
  385                 return (smp_topo_none());
  386         }
  387         /*
  388          * No multi-core or hyper-threaded.
  389          */
  390         if (cpu_logical * cpu_cores == 1)
  391                 return (smp_topo_none());
  392         /*
  393          * Only HTT no multi-core.
  394          */
  395         if (cpu_logical > 1 && cpu_cores == 1)
  396                 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags));
  397         /*
  398          * Only multi-core no HTT.
  399          */
  400         if (cpu_cores > 1 && cpu_logical == 1)
  401                 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags));
  402         /*
  403          * Both HTT and multi-core.
  404          */
  405         return (smp_topo_2level(CG_SHARE_L2, cpu_cores,
  406             CG_SHARE_L1, cpu_logical, cg_flags));
  407 }
  408 
  409 /*
  410  * Calculate usable address in base memory for AP trampoline code.
  411  */
  412 u_int
  413 mp_bootaddress(u_int basemem)
  414 {
  415 
  416         bootMP_size = mptramp_end - mptramp_start;
  417         boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
  418         if (((basemem * 1024) - boot_address) < bootMP_size)
  419                 boot_address -= PAGE_SIZE;      /* not enough, lower by 4k */
  420         /* 3 levels of page table pages */
  421         mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
  422 
  423         return mptramp_pagetables;
  424 }
  425 
  426 void
  427 cpu_add(u_int apic_id, char boot_cpu)
  428 {
  429 
  430         if (apic_id > MAX_APIC_ID) {
  431                 panic("SMP: APIC ID %d too high", apic_id);
  432                 return;
  433         }
  434         KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
  435             apic_id));
  436         cpu_info[apic_id].cpu_present = 1;
  437         if (boot_cpu) {
  438                 KASSERT(boot_cpu_id == -1,
  439                     ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
  440                     boot_cpu_id));
  441                 boot_cpu_id = apic_id;
  442                 cpu_info[apic_id].cpu_bsp = 1;
  443         }
  444         if (mp_ncpus < MAXCPU) {
  445                 mp_ncpus++;
  446                 mp_maxid = mp_ncpus - 1;
  447         }
  448         if (bootverbose)
  449                 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
  450                     "AP");
  451 }
  452 
  453 void
  454 cpu_mp_setmaxid(void)
  455 {
  456 
  457         /*
  458          * mp_maxid should be already set by calls to cpu_add().
  459          * Just sanity check its value here.
  460          */
  461         if (mp_ncpus == 0)
  462                 KASSERT(mp_maxid == 0,
  463                     ("%s: mp_ncpus is zero, but mp_maxid is not", __func__));
  464         else if (mp_ncpus == 1)
  465                 mp_maxid = 0;
  466         else
  467                 KASSERT(mp_maxid >= mp_ncpus - 1,
  468                     ("%s: counters out of sync: max %d, count %d", __func__,
  469                         mp_maxid, mp_ncpus));
  470 }
  471 
  472 int
  473 cpu_mp_probe(void)
  474 {
  475 
  476         /*
  477          * Always record BSP in CPU map so that the mbuf init code works
  478          * correctly.
  479          */
  480         CPU_SETOF(0, &all_cpus);
  481         if (mp_ncpus == 0) {
  482                 /*
  483                  * No CPUs were found, so this must be a UP system.  Setup
  484                  * the variables to represent a system with a single CPU
  485                  * with an id of 0.
  486                  */
  487                 mp_ncpus = 1;
  488                 return (0);
  489         }
  490 
  491         /* At least one CPU was found. */
  492         if (mp_ncpus == 1) {
  493                 /*
  494                  * One CPU was found, so this must be a UP system with
  495                  * an I/O APIC.
  496                  */
  497                 mp_maxid = 0;
  498                 return (0);
  499         }
  500 
  501         /* At least two CPUs were found. */
  502         return (1);
  503 }
  504 
  505 /*
  506  * Initialize the IPI handlers and start up the AP's.
  507  */
  508 void
  509 cpu_mp_start(void)
  510 {
  511         int i;
  512 
  513         /* Initialize the logical ID to APIC ID table. */
  514         for (i = 0; i < MAXCPU; i++) {
  515                 cpu_apic_ids[i] = -1;
  516                 cpu_ipi_pending[i] = 0;
  517         }
  518 
  519         /* Install an inter-CPU IPI for TLB invalidation */
  520         setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0);
  521         setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0);
  522         setidt(IPI_INVLRNG, IDTVEC(invlrng), SDT_SYSIGT, SEL_KPL, 0);
  523 
  524         /* Install an inter-CPU IPI for cache invalidation. */
  525         setidt(IPI_INVLCACHE, IDTVEC(invlcache), SDT_SYSIGT, SEL_KPL, 0);
  526 
  527         /* Install an inter-CPU IPI for all-CPU rendezvous */
  528         setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), SDT_SYSIGT, SEL_KPL, 0);
  529 
  530         /* Install generic inter-CPU IPI handler */
  531         setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
  532                SDT_SYSIGT, SEL_KPL, 0);
  533 
  534         /* Install an inter-CPU IPI for CPU stop/restart */
  535         setidt(IPI_STOP, IDTVEC(cpustop), SDT_SYSIGT, SEL_KPL, 0);
  536 
  537         /* Install an inter-CPU IPI for CPU suspend/resume */
  538         setidt(IPI_SUSPEND, IDTVEC(cpususpend), SDT_SYSIGT, SEL_KPL, 0);
  539 
  540         /* Set boot_cpu_id if needed. */
  541         if (boot_cpu_id == -1) {
  542                 boot_cpu_id = PCPU_GET(apic_id);
  543                 cpu_info[boot_cpu_id].cpu_bsp = 1;
  544         } else
  545                 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
  546                     ("BSP's APIC ID doesn't match boot_cpu_id"));
  547 
  548         /* Probe logical/physical core configuration. */
  549         topo_probe();
  550 
  551         assign_cpu_ids();
  552 
  553         /* Start each Application Processor */
  554         start_all_aps();
  555 
  556         set_interrupt_apic_ids();
  557 }
  558 
  559 
  560 /*
  561  * Print various information about the SMP system hardware and setup.
  562  */
  563 void
  564 cpu_mp_announce(void)
  565 {
  566         const char *hyperthread;
  567         int i;
  568 
  569         printf("FreeBSD/SMP: %d package(s) x %d core(s)",
  570             mp_ncpus / (cpu_cores * cpu_logical), cpu_cores);
  571         if (hyperthreading_cpus > 1)
  572             printf(" x %d HTT threads", cpu_logical);
  573         else if (cpu_logical > 1)
  574             printf(" x %d SMT threads", cpu_logical);
  575         printf("\n");
  576 
  577         /* List active CPUs first. */
  578         printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id);
  579         for (i = 1; i < mp_ncpus; i++) {
  580                 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread)
  581                         hyperthread = "/HT";
  582                 else
  583                         hyperthread = "";
  584                 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread,
  585                     cpu_apic_ids[i]);
  586         }
  587 
  588         /* List disabled CPUs last. */
  589         for (i = 0; i <= MAX_APIC_ID; i++) {
  590                 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled)
  591                         continue;
  592                 if (cpu_info[i].cpu_hyperthread)
  593                         hyperthread = "/HT";
  594                 else
  595                         hyperthread = "";
  596                 printf("  cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread,
  597                     i);
  598         }
  599 }
  600 
  601 /*
  602  * AP CPU's call this to initialize themselves.
  603  */
  604 void
  605 init_secondary(void)
  606 {
  607         struct pcpu *pc;
  608         struct nmi_pcpu *np;
  609         u_int64_t msr, cr0;
  610         u_int cpuid;
  611         int cpu, gsel_tss, x;
  612         struct region_descriptor ap_gdt;
  613 
  614         /* Set by the startup code for us to use */
  615         cpu = bootAP;
  616 
  617         /* Init tss */
  618         common_tss[cpu] = common_tss[0];
  619         common_tss[cpu].tss_rsp0 = 0;   /* not used until after switch */
  620         common_tss[cpu].tss_iobase = sizeof(struct amd64tss) +
  621             IOPAGES * PAGE_SIZE;
  622         common_tss[cpu].tss_ist1 = (long)&doublefault_stack[PAGE_SIZE];
  623 
  624         /* The NMI stack runs on IST2. */
  625         np = ((struct nmi_pcpu *) &nmi_stack[PAGE_SIZE]) - 1;
  626         common_tss[cpu].tss_ist2 = (long) np;
  627 
  628         /* Prepare private GDT */
  629         gdt_segs[GPROC0_SEL].ssd_base = (long) &common_tss[cpu];
  630         for (x = 0; x < NGDT; x++) {
  631                 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1) &&
  632                     x != GUSERLDT_SEL && x != (GUSERLDT_SEL + 1))
  633                         ssdtosd(&gdt_segs[x], &gdt[NGDT * cpu + x]);
  634         }
  635         ssdtosyssd(&gdt_segs[GPROC0_SEL],
  636             (struct system_segment_descriptor *)&gdt[NGDT * cpu + GPROC0_SEL]);
  637         ap_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
  638         ap_gdt.rd_base =  (long) &gdt[NGDT * cpu];
  639         lgdt(&ap_gdt);                  /* does magic intra-segment return */
  640 
  641         /* Get per-cpu data */
  642         pc = &__pcpu[cpu];
  643 
  644         /* prime data page for it to use */
  645         pcpu_init(pc, cpu, sizeof(struct pcpu));
  646         dpcpu_init(dpcpu, cpu);
  647         pc->pc_apic_id = cpu_apic_ids[cpu];
  648         pc->pc_prvspace = pc;
  649         pc->pc_curthread = 0;
  650         pc->pc_tssp = &common_tss[cpu];
  651         pc->pc_commontssp = &common_tss[cpu];
  652         pc->pc_rsp0 = 0;
  653         pc->pc_tss = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
  654             GPROC0_SEL];
  655         pc->pc_fs32p = &gdt[NGDT * cpu + GUFS32_SEL];
  656         pc->pc_gs32p = &gdt[NGDT * cpu + GUGS32_SEL];
  657         pc->pc_ldt = (struct system_segment_descriptor *)&gdt[NGDT * cpu +
  658             GUSERLDT_SEL];
  659 
  660         /* Save the per-cpu pointer for use by the NMI handler. */
  661         np->np_pcpu = (register_t) pc;
  662 
  663         wrmsr(MSR_FSBASE, 0);           /* User value */
  664         wrmsr(MSR_GSBASE, (u_int64_t)pc);
  665         wrmsr(MSR_KGSBASE, (u_int64_t)pc);      /* XXX User value while we're in the kernel */
  666 
  667         lidt(&r_idt);
  668 
  669         gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
  670         ltr(gsel_tss);
  671 
  672         /*
  673          * Set to a known state:
  674          * Set by mpboot.s: CR0_PG, CR0_PE
  675          * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
  676          */
  677         cr0 = rcr0();
  678         cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
  679         load_cr0(cr0);
  680 
  681         /* Set up the fast syscall stuff */
  682         msr = rdmsr(MSR_EFER) | EFER_SCE;
  683         wrmsr(MSR_EFER, msr);
  684         wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
  685         wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
  686         msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
  687               ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
  688         wrmsr(MSR_STAR, msr);
  689         wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
  690 
  691         /* Disable local APIC just to be sure. */
  692         lapic_disable();
  693 
  694         /* signal our startup to the BSP. */
  695         mp_naps++;
  696 
  697         /* Spin until the BSP releases the AP's. */
  698         while (!aps_ready)
  699                 ia32_pause();
  700 
  701         /* Initialize the PAT MSR. */
  702         pmap_init_pat();
  703 
  704         /* set up CPU registers and state */
  705         cpu_setregs();
  706 
  707         /* set up SSE/NX registers */
  708         initializecpu();
  709 
  710         /* set up FPU state on the AP */
  711         fpuinit();
  712 
  713         /* A quick check from sanity claus */
  714         cpuid = PCPU_GET(cpuid);
  715         if (PCPU_GET(apic_id) != lapic_id()) {
  716                 printf("SMP: cpuid = %d\n", cpuid);
  717                 printf("SMP: actual apic_id = %d\n", lapic_id());
  718                 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
  719                 panic("cpuid mismatch! boom!!");
  720         }
  721 
  722         /* Initialize curthread. */
  723         KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
  724         PCPU_SET(curthread, PCPU_GET(idlethread));
  725 
  726         mca_init();
  727 
  728         mtx_lock_spin(&ap_boot_mtx);
  729 
  730         /* Init local apic for irq's */
  731         lapic_setup(1);
  732 
  733         /* Set memory range attributes for this CPU to match the BSP */
  734         mem_range_AP_init();
  735 
  736         smp_cpus++;
  737 
  738         CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid);
  739         printf("SMP: AP CPU #%d Launched!\n", cpuid);
  740 
  741         /* Determine if we are a logical CPU. */
  742         /* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */
  743         if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0)
  744                 CPU_SET(cpuid, &logical_cpus_mask);
  745 
  746         if (bootverbose)
  747                 lapic_dump("AP");
  748 
  749         if (smp_cpus == mp_ncpus) {
  750                 /* enable IPI's, tlb shootdown, freezes etc */
  751                 atomic_store_rel_int(&smp_started, 1);
  752                 smp_active = 1;  /* historic */
  753         }
  754 
  755         /*
  756          * Enable global pages TLB extension
  757          * This also implicitly flushes the TLB 
  758          */
  759 
  760         load_cr4(rcr4() | CR4_PGE);
  761         load_ds(_udatasel);
  762         load_es(_udatasel);
  763         load_fs(_ufssel);
  764         mtx_unlock_spin(&ap_boot_mtx);
  765 
  766         /* Wait until all the AP's are up. */
  767         while (smp_started == 0)
  768                 ia32_pause();
  769 
  770         /* Start per-CPU event timers. */
  771         cpu_initclocks_ap();
  772 
  773         sched_throw(NULL);
  774 
  775         panic("scheduler returned us to %s", __func__);
  776         /* NOTREACHED */
  777 }
  778 
  779 /*******************************************************************
  780  * local functions and data
  781  */
  782 
  783 /*
  784  * We tell the I/O APIC code about all the CPUs we want to receive
  785  * interrupts.  If we don't want certain CPUs to receive IRQs we
  786  * can simply not tell the I/O APIC code about them in this function.
  787  * We also do not tell it about the BSP since it tells itself about
  788  * the BSP internally to work with UP kernels and on UP machines.
  789  */
  790 static void
  791 set_interrupt_apic_ids(void)
  792 {
  793         u_int i, apic_id;
  794 
  795         for (i = 0; i < MAXCPU; i++) {
  796                 apic_id = cpu_apic_ids[i];
  797                 if (apic_id == -1)
  798                         continue;
  799                 if (cpu_info[apic_id].cpu_bsp)
  800                         continue;
  801                 if (cpu_info[apic_id].cpu_disabled)
  802                         continue;
  803 
  804                 /* Don't let hyperthreads service interrupts. */
  805                 if (hyperthreading_cpus > 1 &&
  806                     apic_id % hyperthreading_cpus != 0)
  807                         continue;
  808 
  809                 intr_add_cpu(i);
  810         }
  811 }
  812 
  813 /*
  814  * Assign logical CPU IDs to local APICs.
  815  */
  816 static void
  817 assign_cpu_ids(void)
  818 {
  819         u_int i;
  820 
  821         TUNABLE_INT_FETCH("machdep.hyperthreading_allowed",
  822             &hyperthreading_allowed);
  823 
  824         /* Check for explicitly disabled CPUs. */
  825         for (i = 0; i <= MAX_APIC_ID; i++) {
  826                 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp)
  827                         continue;
  828 
  829                 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) {
  830                         cpu_info[i].cpu_hyperthread = 1;
  831 
  832                         /*
  833                          * Don't use HT CPU if it has been disabled by a
  834                          * tunable.
  835                          */
  836                         if (hyperthreading_allowed == 0) {
  837                                 cpu_info[i].cpu_disabled = 1;
  838                                 continue;
  839                         }
  840                 }
  841 
  842                 /* Don't use this CPU if it has been disabled by a tunable. */
  843                 if (resource_disabled("lapic", i)) {
  844                         cpu_info[i].cpu_disabled = 1;
  845                         continue;
  846                 }
  847         }
  848 
  849         if (hyperthreading_allowed == 0 && hyperthreading_cpus > 1) {
  850                 hyperthreading_cpus = 0;
  851                 cpu_logical = 1;
  852         }
  853 
  854         /*
  855          * Assign CPU IDs to local APIC IDs and disable any CPUs
  856          * beyond MAXCPU.  CPU 0 is always assigned to the BSP.
  857          *
  858          * To minimize confusion for userland, we attempt to number
  859          * CPUs such that all threads and cores in a package are
  860          * grouped together.  For now we assume that the BSP is always
  861          * the first thread in a package and just start adding APs
  862          * starting with the BSP's APIC ID.
  863          */
  864         mp_ncpus = 1;
  865         cpu_apic_ids[0] = boot_cpu_id;
  866         apic_cpuids[boot_cpu_id] = 0;
  867         for (i = boot_cpu_id + 1; i != boot_cpu_id;
  868              i == MAX_APIC_ID ? i = 0 : i++) {
  869                 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp ||
  870                     cpu_info[i].cpu_disabled)
  871                         continue;
  872 
  873                 if (mp_ncpus < MAXCPU) {
  874                         cpu_apic_ids[mp_ncpus] = i;
  875                         apic_cpuids[i] = mp_ncpus;
  876                         mp_ncpus++;
  877                 } else
  878                         cpu_info[i].cpu_disabled = 1;
  879         }
  880         KASSERT(mp_maxid >= mp_ncpus - 1,
  881             ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
  882             mp_ncpus));         
  883 }
  884 
  885 /*
  886  * start each AP in our list
  887  */
  888 static int
  889 start_all_aps(void)
  890 {
  891         vm_offset_t va = boot_address + KERNBASE;
  892         u_int64_t *pt4, *pt3, *pt2;
  893         u_int32_t mpbioswarmvec;
  894         int apic_id, cpu, i;
  895         u_char mpbiosreason;
  896 
  897         mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
  898 
  899         /* install the AP 1st level boot code */
  900         pmap_kenter(va, boot_address);
  901         pmap_invalidate_page(kernel_pmap, va);
  902         bcopy(mptramp_start, (void *)va, bootMP_size);
  903 
  904         /* Locate the page tables, they'll be below the trampoline */
  905         pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
  906         pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
  907         pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
  908 
  909         /* Create the initial 1GB replicated page tables */
  910         for (i = 0; i < 512; i++) {
  911                 /* Each slot of the level 4 pages points to the same level 3 page */
  912                 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
  913                 pt4[i] |= PG_V | PG_RW | PG_U;
  914 
  915                 /* Each slot of the level 3 pages points to the same level 2 page */
  916                 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
  917                 pt3[i] |= PG_V | PG_RW | PG_U;
  918 
  919                 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
  920                 pt2[i] = i * (2 * 1024 * 1024);
  921                 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
  922         }
  923 
  924         /* save the current value of the warm-start vector */
  925         mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
  926         outb(CMOS_REG, BIOS_RESET);
  927         mpbiosreason = inb(CMOS_DATA);
  928 
  929         /* setup a vector to our boot code */
  930         *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
  931         *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
  932         outb(CMOS_REG, BIOS_RESET);
  933         outb(CMOS_DATA, BIOS_WARM);     /* 'warm-start' */
  934 
  935         /* start each AP */
  936         for (cpu = 1; cpu < mp_ncpus; cpu++) {
  937                 apic_id = cpu_apic_ids[cpu];
  938 
  939                 /* allocate and set up an idle stack data page */
  940                 bootstacks[cpu] = (void *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE);
  941                 doublefault_stack = (char *)kmem_alloc(kernel_map, PAGE_SIZE);
  942                 nmi_stack = (char *)kmem_alloc(kernel_map, PAGE_SIZE);
  943                 dpcpu = (void *)kmem_alloc(kernel_map, DPCPU_SIZE);
  944 
  945                 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 8;
  946                 bootAP = cpu;
  947 
  948                 /* attempt to start the Application Processor */
  949                 if (!start_ap(apic_id)) {
  950                         /* restore the warmstart vector */
  951                         *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
  952                         panic("AP #%d (PHY# %d) failed!", cpu, apic_id);
  953                 }
  954 
  955                 CPU_SET(cpu, &all_cpus);        /* record AP in CPU map */
  956         }
  957 
  958         /* restore the warmstart vector */
  959         *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
  960 
  961         outb(CMOS_REG, BIOS_RESET);
  962         outb(CMOS_DATA, mpbiosreason);
  963 
  964         /* number of APs actually started */
  965         return mp_naps;
  966 }
  967 
  968 
  969 /*
  970  * This function starts the AP (application processor) identified
  971  * by the APIC ID 'physicalCpu'.  It does quite a "song and dance"
  972  * to accomplish this.  This is necessary because of the nuances
  973  * of the different hardware we might encounter.  It isn't pretty,
  974  * but it seems to work.
  975  */
  976 static int
  977 start_ap(int apic_id)
  978 {
  979         int vector, ms;
  980         int cpus;
  981 
  982         /* calculate the vector */
  983         vector = (boot_address >> 12) & 0xff;
  984 
  985         /* used as a watchpoint to signal AP startup */
  986         cpus = mp_naps;
  987 
  988         /*
  989          * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
  990          * and running the target CPU. OR this INIT IPI might be latched (P5
  991          * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
  992          * ignored.
  993          */
  994 
  995         /* do an INIT IPI: assert RESET */
  996         lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
  997             APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
  998 
  999         /* wait for pending status end */
 1000         lapic_ipi_wait(-1);
 1001 
 1002         /* do an INIT IPI: deassert RESET */
 1003         lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL |
 1004             APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0);
 1005 
 1006         /* wait for pending status end */
 1007         DELAY(10000);           /* wait ~10mS */
 1008         lapic_ipi_wait(-1);
 1009 
 1010         /*
 1011          * next we do a STARTUP IPI: the previous INIT IPI might still be
 1012          * latched, (P5 bug) this 1st STARTUP would then terminate
 1013          * immediately, and the previously started INIT IPI would continue. OR
 1014          * the previous INIT IPI has already run. and this STARTUP IPI will
 1015          * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
 1016          * will run.
 1017          */
 1018 
 1019         /* do a STARTUP IPI */
 1020         lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
 1021             APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
 1022             vector, apic_id);
 1023         lapic_ipi_wait(-1);
 1024         DELAY(200);             /* wait ~200uS */
 1025 
 1026         /*
 1027          * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
 1028          * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
 1029          * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
 1030          * recognized after hardware RESET or INIT IPI.
 1031          */
 1032 
 1033         lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
 1034             APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
 1035             vector, apic_id);
 1036         lapic_ipi_wait(-1);
 1037         DELAY(200);             /* wait ~200uS */
 1038 
 1039         /* Wait up to 5 seconds for it to start. */
 1040         for (ms = 0; ms < 5000; ms++) {
 1041                 if (mp_naps > cpus)
 1042                         return 1;       /* return SUCCESS */
 1043                 DELAY(1000);
 1044         }
 1045         return 0;               /* return FAILURE */
 1046 }
 1047 
 1048 #ifdef COUNT_XINVLTLB_HITS
 1049 u_int xhits_gbl[MAXCPU];
 1050 u_int xhits_pg[MAXCPU];
 1051 u_int xhits_rng[MAXCPU];
 1052 SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
 1053 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
 1054     sizeof(xhits_gbl), "IU", "");
 1055 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
 1056     sizeof(xhits_pg), "IU", "");
 1057 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
 1058     sizeof(xhits_rng), "IU", "");
 1059 
 1060 u_int ipi_global;
 1061 u_int ipi_page;
 1062 u_int ipi_range;
 1063 u_int ipi_range_size;
 1064 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
 1065 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
 1066 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
 1067 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW,
 1068     &ipi_range_size, 0, "");
 1069 
 1070 u_int ipi_masked_global;
 1071 u_int ipi_masked_page;
 1072 u_int ipi_masked_range;
 1073 u_int ipi_masked_range_size;
 1074 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW,
 1075     &ipi_masked_global, 0, "");
 1076 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW,
 1077     &ipi_masked_page, 0, "");
 1078 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW,
 1079     &ipi_masked_range, 0, "");
 1080 SYSCTL_UINT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW,
 1081     &ipi_masked_range_size, 0, "");
 1082 #endif /* COUNT_XINVLTLB_HITS */
 1083 
 1084 /*
 1085  * Send an IPI to specified CPU handling the bitmap logic.
 1086  */
 1087 static void
 1088 ipi_send_cpu(int cpu, u_int ipi)
 1089 {
 1090         u_int bitmap, old_pending, new_pending;
 1091 
 1092         KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu));
 1093 
 1094         if (IPI_IS_BITMAPED(ipi)) {
 1095                 bitmap = 1 << ipi;
 1096                 ipi = IPI_BITMAP_VECTOR;
 1097                 do {
 1098                         old_pending = cpu_ipi_pending[cpu];
 1099                         new_pending = old_pending | bitmap;
 1100                 } while  (!atomic_cmpset_int(&cpu_ipi_pending[cpu],
 1101                     old_pending, new_pending)); 
 1102                 if (old_pending)
 1103                         return;
 1104         }
 1105         lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
 1106 }
 1107 
 1108 /*
 1109  * Flush the TLB on all other CPU's
 1110  */
 1111 static void
 1112 smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
 1113 {
 1114         u_int ncpu;
 1115 
 1116         ncpu = mp_ncpus - 1;    /* does not shootdown self */
 1117         if (ncpu < 1)
 1118                 return;         /* no other cpus */
 1119         if (!(read_rflags() & PSL_I))
 1120                 panic("%s: interrupts disabled", __func__);
 1121         mtx_lock_spin(&smp_ipi_mtx);
 1122         smp_tlb_addr1 = addr1;
 1123         smp_tlb_addr2 = addr2;
 1124         atomic_store_rel_int(&smp_tlb_wait, 0);
 1125         ipi_all_but_self(vector);
 1126         while (smp_tlb_wait < ncpu)
 1127                 ia32_pause();
 1128         mtx_unlock_spin(&smp_ipi_mtx);
 1129 }
 1130 
 1131 static void
 1132 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
 1133 {
 1134         int cpu, ncpu, othercpus;
 1135 
 1136         othercpus = mp_ncpus - 1;
 1137         if (CPU_ISFULLSET(&mask)) {
 1138                 if (othercpus < 1)
 1139                         return;
 1140         } else {
 1141                 CPU_CLR(PCPU_GET(cpuid), &mask);
 1142                 if (CPU_EMPTY(&mask))
 1143                         return;
 1144         }
 1145         if (!(read_rflags() & PSL_I))
 1146                 panic("%s: interrupts disabled", __func__);
 1147         mtx_lock_spin(&smp_ipi_mtx);
 1148         smp_tlb_addr1 = addr1;
 1149         smp_tlb_addr2 = addr2;
 1150         atomic_store_rel_int(&smp_tlb_wait, 0);
 1151         if (CPU_ISFULLSET(&mask)) {
 1152                 ncpu = othercpus;
 1153                 ipi_all_but_self(vector);
 1154         } else {
 1155                 ncpu = 0;
 1156                 while ((cpu = cpusetobj_ffs(&mask)) != 0) {
 1157                         cpu--;
 1158                         CPU_CLR(cpu, &mask);
 1159                         CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__,
 1160                             cpu, vector);
 1161                         ipi_send_cpu(cpu, vector);
 1162                         ncpu++;
 1163                 }
 1164         }
 1165         while (smp_tlb_wait < ncpu)
 1166                 ia32_pause();
 1167         mtx_unlock_spin(&smp_ipi_mtx);
 1168 }
 1169 
 1170 void
 1171 smp_cache_flush(void)
 1172 {
 1173 
 1174         if (smp_started)
 1175                 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0);
 1176 }
 1177 
 1178 void
 1179 smp_invltlb(void)
 1180 {
 1181 
 1182         if (smp_started) {
 1183                 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
 1184 #ifdef COUNT_XINVLTLB_HITS
 1185                 ipi_global++;
 1186 #endif
 1187         }
 1188 }
 1189 
 1190 void
 1191 smp_invlpg(vm_offset_t addr)
 1192 {
 1193 
 1194         if (smp_started) {
 1195                 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
 1196 #ifdef COUNT_XINVLTLB_HITS
 1197                 ipi_page++;
 1198 #endif
 1199         }
 1200 }
 1201 
 1202 void
 1203 smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
 1204 {
 1205 
 1206         if (smp_started) {
 1207                 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
 1208 #ifdef COUNT_XINVLTLB_HITS
 1209                 ipi_range++;
 1210                 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
 1211 #endif
 1212         }
 1213 }
 1214 
 1215 void
 1216 smp_masked_invltlb(cpuset_t mask)
 1217 {
 1218 
 1219         if (smp_started) {
 1220                 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
 1221 #ifdef COUNT_XINVLTLB_HITS
 1222                 ipi_masked_global++;
 1223 #endif
 1224         }
 1225 }
 1226 
 1227 void
 1228 smp_masked_invlpg(cpuset_t mask, vm_offset_t addr)
 1229 {
 1230 
 1231         if (smp_started) {
 1232                 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
 1233 #ifdef COUNT_XINVLTLB_HITS
 1234                 ipi_masked_page++;
 1235 #endif
 1236         }
 1237 }
 1238 
 1239 void
 1240 smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2)
 1241 {
 1242 
 1243         if (smp_started) {
 1244                 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
 1245 #ifdef COUNT_XINVLTLB_HITS
 1246                 ipi_masked_range++;
 1247                 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE;
 1248 #endif
 1249         }
 1250 }
 1251 
 1252 void
 1253 ipi_bitmap_handler(struct trapframe frame)
 1254 {
 1255         struct trapframe *oldframe;
 1256         struct thread *td;
 1257         int cpu = PCPU_GET(cpuid);
 1258         u_int ipi_bitmap;
 1259 
 1260         critical_enter();
 1261         td = curthread;
 1262         td->td_intr_nesting_level++;
 1263         oldframe = td->td_intr_frame;
 1264         td->td_intr_frame = &frame;
 1265         ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
 1266         if (ipi_bitmap & (1 << IPI_PREEMPT)) {
 1267 #ifdef COUNT_IPIS
 1268                 (*ipi_preempt_counts[cpu])++;
 1269 #endif
 1270                 sched_preempt(td);
 1271         }
 1272         if (ipi_bitmap & (1 << IPI_AST)) {
 1273 #ifdef COUNT_IPIS
 1274                 (*ipi_ast_counts[cpu])++;
 1275 #endif
 1276                 /* Nothing to do for AST */
 1277         }
 1278         if (ipi_bitmap & (1 << IPI_HARDCLOCK)) {
 1279 #ifdef COUNT_IPIS
 1280                 (*ipi_hardclock_counts[cpu])++;
 1281 #endif
 1282                 hardclockintr();
 1283         }
 1284         td->td_intr_frame = oldframe;
 1285         td->td_intr_nesting_level--;
 1286         critical_exit();
 1287 }
 1288 
 1289 /*
 1290  * send an IPI to a set of cpus.
 1291  */
 1292 void
 1293 ipi_selected(cpuset_t cpus, u_int ipi)
 1294 {
 1295         int cpu;
 1296 
 1297         /*
 1298          * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
 1299          * of help in order to understand what is the source.
 1300          * Set the mask of receiving CPUs for this purpose.
 1301          */
 1302         if (ipi == IPI_STOP_HARD)
 1303                 CPU_OR_ATOMIC(&ipi_nmi_pending, &cpus);
 1304 
 1305         while ((cpu = cpusetobj_ffs(&cpus)) != 0) {
 1306                 cpu--;
 1307                 CPU_CLR(cpu, &cpus);
 1308                 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
 1309                 ipi_send_cpu(cpu, ipi);
 1310         }
 1311 }
 1312 
 1313 /*
 1314  * send an IPI to a specific CPU.
 1315  */
 1316 void
 1317 ipi_cpu(int cpu, u_int ipi)
 1318 {
 1319 
 1320         /*
 1321          * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
 1322          * of help in order to understand what is the source.
 1323          * Set the mask of receiving CPUs for this purpose.
 1324          */
 1325         if (ipi == IPI_STOP_HARD)
 1326                 CPU_SET_ATOMIC(cpu, &ipi_nmi_pending);
 1327 
 1328         CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
 1329         ipi_send_cpu(cpu, ipi);
 1330 }
 1331 
 1332 /*
 1333  * send an IPI to all CPUs EXCEPT myself
 1334  */
 1335 void
 1336 ipi_all_but_self(u_int ipi)
 1337 {
 1338         cpuset_t other_cpus;
 1339 
 1340         other_cpus = all_cpus;
 1341         CPU_CLR(PCPU_GET(cpuid), &other_cpus);
 1342 
 1343         if (IPI_IS_BITMAPED(ipi)) {
 1344                 ipi_selected(other_cpus, ipi);
 1345                 return;
 1346         }
 1347 
 1348         /*
 1349          * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
 1350          * of help in order to understand what is the source.
 1351          * Set the mask of receiving CPUs for this purpose.
 1352          */
 1353         if (ipi == IPI_STOP_HARD)
 1354                 CPU_OR_ATOMIC(&ipi_nmi_pending, &other_cpus);
 1355 
 1356         CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
 1357         lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
 1358 }
 1359 
 1360 int
 1361 ipi_nmi_handler()
 1362 {
 1363         u_int cpuid;
 1364 
 1365         /*
 1366          * As long as there is not a simple way to know about a NMI's
 1367          * source, if the bitmask for the current CPU is present in
 1368          * the global pending bitword an IPI_STOP_HARD has been issued
 1369          * and should be handled.
 1370          */
 1371         cpuid = PCPU_GET(cpuid);
 1372         if (!CPU_ISSET(cpuid, &ipi_nmi_pending))
 1373                 return (1);
 1374 
 1375         CPU_CLR_ATOMIC(cpuid, &ipi_nmi_pending);
 1376         cpustop_handler();
 1377         return (0);
 1378 }
 1379      
 1380 /*
 1381  * Handle an IPI_STOP by saving our current context and spinning until we
 1382  * are resumed.
 1383  */
 1384 void
 1385 cpustop_handler(void)
 1386 {
 1387         u_int cpu;
 1388 
 1389         cpu = PCPU_GET(cpuid);
 1390 
 1391         savectx(&stoppcbs[cpu]);
 1392 
 1393         /* Indicate that we are stopped */
 1394         CPU_SET_ATOMIC(cpu, &stopped_cpus);
 1395 
 1396         /* Wait for restart */
 1397         while (!CPU_ISSET(cpu, &started_cpus))
 1398             ia32_pause();
 1399 
 1400         CPU_CLR_ATOMIC(cpu, &started_cpus);
 1401         CPU_CLR_ATOMIC(cpu, &stopped_cpus);
 1402 
 1403         if (cpu == 0 && cpustop_restartfunc != NULL) {
 1404                 cpustop_restartfunc();
 1405                 cpustop_restartfunc = NULL;
 1406         }
 1407 }
 1408 
 1409 /*
 1410  * Handle an IPI_SUSPEND by saving our current context and spinning until we
 1411  * are resumed.
 1412  */
 1413 void
 1414 cpususpend_handler(void)
 1415 {
 1416         register_t cr3, rf;
 1417         u_int cpu;
 1418 
 1419         cpu = PCPU_GET(cpuid);
 1420 
 1421         rf = intr_disable();
 1422         cr3 = rcr3();
 1423 
 1424         if (savectx(susppcbs[cpu])) {
 1425                 wbinvd();
 1426                 CPU_SET_ATOMIC(cpu, &stopped_cpus);
 1427         } else {
 1428                 pmap_init_pat();
 1429                 PCPU_SET(switchtime, 0);
 1430                 PCPU_SET(switchticks, ticks);
 1431         }
 1432 
 1433         /* Wait for resume */
 1434         while (!CPU_ISSET(cpu, &started_cpus))
 1435                 ia32_pause();
 1436 
 1437         CPU_CLR_ATOMIC(cpu, &started_cpus);
 1438         CPU_CLR_ATOMIC(cpu, &stopped_cpus);
 1439 
 1440         /* Restore CR3 and enable interrupts */
 1441         load_cr3(cr3);
 1442         mca_resume();
 1443         lapic_setup(0);
 1444         intr_restore(rf);
 1445 }
 1446 
 1447 /*
 1448  * This is called once the rest of the system is up and running and we're
 1449  * ready to let the AP's out of the pen.
 1450  */
 1451 static void
 1452 release_aps(void *dummy __unused)
 1453 {
 1454 
 1455         if (mp_ncpus == 1) 
 1456                 return;
 1457         atomic_store_rel_int(&aps_ready, 1);
 1458         while (smp_started == 0)
 1459                 ia32_pause();
 1460 }
 1461 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
 1462 
 1463 #ifdef COUNT_IPIS
 1464 /*
 1465  * Setup interrupt counters for IPI handlers.
 1466  */
 1467 static void
 1468 mp_ipi_intrcnt(void *dummy)
 1469 {
 1470         char buf[64];
 1471         int i;
 1472 
 1473         CPU_FOREACH(i) {
 1474                 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i);
 1475                 intrcnt_add(buf, &ipi_invltlb_counts[i]);
 1476                 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i);
 1477                 intrcnt_add(buf, &ipi_invlrng_counts[i]);
 1478                 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i);
 1479                 intrcnt_add(buf, &ipi_invlpg_counts[i]);
 1480                 snprintf(buf, sizeof(buf), "cpu%d:preempt", i);
 1481                 intrcnt_add(buf, &ipi_preempt_counts[i]);
 1482                 snprintf(buf, sizeof(buf), "cpu%d:ast", i);
 1483                 intrcnt_add(buf, &ipi_ast_counts[i]);
 1484                 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i);
 1485                 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
 1486                 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
 1487                 intrcnt_add(buf, &ipi_hardclock_counts[i]);
 1488         }
 1489 }
 1490 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);
 1491 #endif
 1492 

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