1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/kernel.h>
34 #include <sys/malloc.h>
35
36 #include <vm/vm.h>
37 #include <vm/vm_param.h>
38 #include <vm/pmap.h>
39
40 #include <machine/apicreg.h>
41 #include <machine/frame.h>
42 #include <machine/intr_machdep.h>
43 #include <machine/apicvar.h>
44 #include <machine/md_var.h>
45 #include <machine/mptable.h>
46 #include <machine/specialreg.h>
47
48 #include <dev/pci/pcivar.h>
49
50 /* string defined by the Intel MP Spec as identifying the MP table */
51 #define MP_SIG 0x5f504d5f /* _MP_ */
52
53 #define MAX_LAPIC_ID 63 /* Max local APIC ID for HTT fixup */
54
55 #define BIOS_BASE (0xf0000)
56 #define BIOS_SIZE (0x10000)
57 #define BIOS_COUNT (BIOS_SIZE/4)
58
59 typedef void mptable_entry_handler(u_char *entry, void *arg);
60
61 static basetable_entry basetable_entry_types[] =
62 {
63 {0, 20, "Processor"},
64 {1, 8, "Bus"},
65 {2, 8, "I/O APIC"},
66 {3, 8, "I/O INT"},
67 {4, 8, "Local INT"}
68 };
69
70 typedef struct BUSDATA {
71 u_char bus_id;
72 enum busTypes bus_type;
73 } bus_datum;
74
75 typedef struct INTDATA {
76 u_char int_type;
77 u_short int_flags;
78 u_char src_bus_id;
79 u_char src_bus_irq;
80 u_char dst_apic_id;
81 u_char dst_apic_int;
82 u_char int_vector;
83 } io_int, local_int;
84
85 typedef struct BUSTYPENAME {
86 u_char type;
87 char name[7];
88 } bus_type_name;
89
90 /* From MP spec v1.4, table 4-8. */
91 static bus_type_name bus_type_table[] =
92 {
93 {UNKNOWN_BUSTYPE, "CBUS "},
94 {UNKNOWN_BUSTYPE, "CBUSII"},
95 {EISA, "EISA "},
96 {UNKNOWN_BUSTYPE, "FUTURE"},
97 {UNKNOWN_BUSTYPE, "INTERN"},
98 {ISA, "ISA "},
99 {UNKNOWN_BUSTYPE, "MBI "},
100 {UNKNOWN_BUSTYPE, "MBII "},
101 {MCA, "MCA "},
102 {UNKNOWN_BUSTYPE, "MPI "},
103 {UNKNOWN_BUSTYPE, "MPSA "},
104 {UNKNOWN_BUSTYPE, "NUBUS "},
105 {PCI, "PCI "},
106 {UNKNOWN_BUSTYPE, "PCMCIA"},
107 {UNKNOWN_BUSTYPE, "TC "},
108 {UNKNOWN_BUSTYPE, "VL "},
109 {UNKNOWN_BUSTYPE, "VME "},
110 {UNKNOWN_BUSTYPE, "XPRESS"}
111 };
112
113 /* From MP spec v1.4, table 5-1. */
114 static int default_data[7][5] =
115 {
116 /* nbus, id0, type0, id1, type1 */
117 {1, 0, ISA, 255, NOBUS},
118 {1, 0, EISA, 255, NOBUS},
119 {1, 0, EISA, 255, NOBUS},
120 {1, 0, MCA, 255, NOBUS},
121 {2, 0, ISA, 1, PCI},
122 {2, 0, EISA, 1, PCI},
123 {2, 0, MCA, 1, PCI}
124 };
125
126 struct pci_probe_table_args {
127 u_char bus;
128 u_char found;
129 };
130
131 struct pci_route_interrupt_args {
132 u_char bus; /* Source bus. */
133 u_char irq; /* Source slot:pin. */
134 int vector; /* Return value. */
135 };
136
137 static mpfps_t mpfps;
138 static mpcth_t mpct;
139 static void *ioapics[MAX_APIC_ID + 1];
140 static bus_datum *busses;
141 static int mptable_nioapics, mptable_nbusses, mptable_maxbusid;
142 static int pci0 = -1;
143
144 static MALLOC_DEFINE(M_MPTABLE, "mptable", "MP Table Items");
145
146 static enum intr_polarity conforming_polarity(u_char src_bus,
147 u_char src_bus_irq);
148 static enum intr_trigger conforming_trigger(u_char src_bus, u_char src_bus_irq);
149 static enum intr_polarity intentry_polarity(int_entry_ptr intr);
150 static enum intr_trigger intentry_trigger(int_entry_ptr intr);
151 static int lookup_bus_type(char *name);
152 static void mptable_count_items(void);
153 static void mptable_count_items_handler(u_char *entry, void *arg);
154 #ifdef MPTABLE_FORCE_HTT
155 static void mptable_hyperthread_fixup(u_long id_mask);
156 #endif
157 static void mptable_parse_apics_and_busses(void);
158 static void mptable_parse_apics_and_busses_handler(u_char *entry,
159 void *arg);
160 static void mptable_parse_default_config_ints(void);
161 static void mptable_parse_ints(void);
162 static void mptable_parse_ints_handler(u_char *entry, void *arg);
163 static void mptable_parse_io_int(int_entry_ptr intr);
164 static void mptable_parse_local_int(int_entry_ptr intr);
165 static void mptable_pci_probe_table_handler(u_char *entry, void *arg);
166 static void mptable_pci_route_interrupt_handler(u_char *entry, void *arg);
167 static void mptable_pci_setup(void);
168 static int mptable_probe(void);
169 static int mptable_probe_cpus(void);
170 static void mptable_probe_cpus_handler(u_char *entry, void *arg __unused);
171 static void mptable_register(void *dummy);
172 static int mptable_setup_local(void);
173 static int mptable_setup_io(void);
174 static void mptable_walk_table(mptable_entry_handler *handler, void *arg);
175 static int search_for_sig(u_int32_t target, int count);
176
177 static struct apic_enumerator mptable_enumerator = {
178 "MPTable",
179 mptable_probe,
180 mptable_probe_cpus,
181 mptable_setup_local,
182 mptable_setup_io
183 };
184
185 /*
186 * look for the MP spec signature
187 */
188
189 static int
190 search_for_sig(u_int32_t target, int count)
191 {
192 int x;
193 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
194
195 for (x = 0; x < count; x += 4)
196 if (addr[x] == MP_SIG)
197 /* make array index a byte index */
198 return (target + (x * sizeof(u_int32_t)));
199 return (-1);
200 }
201
202 static int
203 lookup_bus_type(char *name)
204 {
205 int x;
206
207 for (x = 0; x < MAX_BUSTYPE; ++x)
208 if (strncmp(bus_type_table[x].name, name, 6) == 0)
209 return (bus_type_table[x].type);
210
211 return (UNKNOWN_BUSTYPE);
212 }
213
214 /*
215 * Look for an Intel MP spec table (ie, SMP capable hardware).
216 */
217 static int
218 mptable_probe(void)
219 {
220 int x;
221 u_int32_t segment;
222 u_int32_t target;
223
224 /* see if EBDA exists */
225 segment = (u_int32_t) *(u_short *)(KERNBASE + 0x40e);
226 if (segment != 0) {
227 /* search first 1K of EBDA */
228 target = (u_int32_t) (segment << 4);
229 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
230 goto found;
231 } else {
232 /* last 1K of base memory, effective 'top of base' passed in */
233 target = (u_int32_t) ((basemem * 1024) - 0x400);
234 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
235 goto found;
236 }
237
238 /* search the BIOS */
239 target = (u_int32_t) BIOS_BASE;
240 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
241 goto found;
242
243 /* nothing found */
244 return (ENXIO);
245
246 found:
247 mpfps = (mpfps_t)(KERNBASE + x);
248
249 /* Map in the configuration table if it exists. */
250 if (mpfps->config_type != 0) {
251 if (bootverbose)
252 printf(
253 "MP Table version 1.%d found using Default Configuration %d\n",
254 mpfps->spec_rev, mpfps->config_type);
255 if (mpfps->config_type != 5 && mpfps->config_type != 6) {
256 printf(
257 "MP Table Default Configuration %d is unsupported\n",
258 mpfps->config_type);
259 return (ENXIO);
260 }
261 mpct = NULL;
262 } else {
263 if ((uintptr_t)mpfps->pap >= 1024 * 1024) {
264 printf("%s: Unable to map MP Configuration Table\n",
265 __func__);
266 return (ENXIO);
267 }
268 mpct = (mpcth_t)(KERNBASE + (uintptr_t)mpfps->pap);
269 if (mpct->base_table_length + (uintptr_t)mpfps->pap >=
270 1024 * 1024) {
271 printf("%s: Unable to map end of MP Config Table\n",
272 __func__);
273 return (ENXIO);
274 }
275 if (mpct->signature[0] != 'P' || mpct->signature[1] != 'C' ||
276 mpct->signature[2] != 'M' || mpct->signature[3] != 'P') {
277 printf("%s: MP Config Table has bad signature: %c%c%c%c\n",
278 __func__, mpct->signature[0], mpct->signature[1],
279 mpct->signature[2], mpct->signature[3]);
280 return (ENXIO);
281 }
282 if (bootverbose)
283 printf(
284 "MP Configuration Table version 1.%d found at %p\n",
285 mpct->spec_rev, mpct);
286 }
287
288 return (-100);
289 }
290
291 /*
292 * Run through the MP table enumerating CPUs.
293 */
294 static int
295 mptable_probe_cpus(void)
296 {
297 u_long cpu_mask;
298
299 /* Is this a pre-defined config? */
300 if (mpfps->config_type != 0) {
301 lapic_create(0, 1);
302 lapic_create(1, 0);
303 } else {
304 cpu_mask = 0;
305 mptable_walk_table(mptable_probe_cpus_handler, &cpu_mask);
306 #ifdef MPTABLE_FORCE_HTT
307 mptable_hyperthread_fixup(cpu_mask);
308 #endif
309 }
310 return (0);
311 }
312
313 /*
314 * Initialize the local APIC on the BSP.
315 */
316 static int
317 mptable_setup_local(void)
318 {
319 vm_paddr_t addr;
320
321 /* Is this a pre-defined config? */
322 printf("MPTable: <");
323 if (mpfps->config_type != 0) {
324 addr = DEFAULT_APIC_BASE;
325 printf("Default Configuration %d", mpfps->config_type);
326 } else {
327 addr = mpct->apic_address;
328 printf("%.*s %.*s", (int)sizeof(mpct->oem_id), mpct->oem_id,
329 (int)sizeof(mpct->product_id), mpct->product_id);
330 }
331 printf(">\n");
332 lapic_init(addr);
333 return (0);
334 }
335
336 /*
337 * Run through the MP table enumerating I/O APICs.
338 */
339 static int
340 mptable_setup_io(void)
341 {
342 int i;
343 u_char byte;
344
345 /* First, we count individual items and allocate arrays. */
346 mptable_count_items();
347 busses = malloc((mptable_maxbusid + 1) * sizeof(bus_datum), M_MPTABLE,
348 M_WAITOK);
349 for (i = 0; i <= mptable_maxbusid; i++)
350 busses[i].bus_type = NOBUS;
351
352 /* Second, we run through adding I/O APIC's and busses. */
353 mptable_parse_apics_and_busses();
354
355 /* Third, we run through the table tweaking interrupt sources. */
356 mptable_parse_ints();
357
358 /* Fourth, we register all the I/O APIC's. */
359 for (i = 0; i <= MAX_APIC_ID; i++)
360 if (ioapics[i] != NULL)
361 ioapic_register(ioapics[i]);
362
363 /* Fifth, we setup data structures to handle PCI interrupt routing. */
364 mptable_pci_setup();
365
366 /* Finally, we throw the switch to enable the I/O APIC's. */
367 if (mpfps->mpfb2 & MPFB2_IMCR_PRESENT) {
368 outb(0x22, 0x70); /* select IMCR */
369 byte = inb(0x23); /* current contents */
370 byte |= 0x01; /* mask external INTR */
371 outb(0x23, byte); /* disconnect 8259s/NMI */
372 }
373
374 return (0);
375 }
376
377 static void
378 mptable_register(void *dummy __unused)
379 {
380
381 apic_register_enumerator(&mptable_enumerator);
382 }
383 SYSINIT(mptable_register, SI_SUB_TUNABLES - 1, SI_ORDER_FIRST,
384 mptable_register, NULL);
385
386 /*
387 * Call the handler routine for each entry in the MP config table.
388 */
389 static void
390 mptable_walk_table(mptable_entry_handler *handler, void *arg)
391 {
392 u_int i;
393 u_char *entry;
394
395 entry = (u_char *)(mpct + 1);
396 for (i = 0; i < mpct->entry_count; i++) {
397 switch (*entry) {
398 case MPCT_ENTRY_PROCESSOR:
399 case MPCT_ENTRY_IOAPIC:
400 case MPCT_ENTRY_BUS:
401 case MPCT_ENTRY_INT:
402 case MPCT_ENTRY_LOCAL_INT:
403 break;
404 default:
405 panic("%s: Unknown MP Config Entry %d\n", __func__,
406 (int)*entry);
407 }
408 handler(entry, arg);
409 entry += basetable_entry_types[*entry].length;
410 }
411 }
412
413 static void
414 mptable_probe_cpus_handler(u_char *entry, void *arg)
415 {
416 proc_entry_ptr proc;
417 u_long *cpu_mask;
418
419 switch (*entry) {
420 case MPCT_ENTRY_PROCESSOR:
421 proc = (proc_entry_ptr)entry;
422 if (proc->cpu_flags & PROCENTRY_FLAG_EN) {
423 lapic_create(proc->apic_id, proc->cpu_flags &
424 PROCENTRY_FLAG_BP);
425 if (proc->apic_id < MAX_LAPIC_ID) {
426 cpu_mask = (u_long *)arg;
427 *cpu_mask |= (1ul << proc->apic_id);
428 }
429 }
430 break;
431 }
432 }
433
434 static void
435 mptable_count_items_handler(u_char *entry, void *arg __unused)
436 {
437 io_apic_entry_ptr apic;
438 bus_entry_ptr bus;
439
440 switch (*entry) {
441 case MPCT_ENTRY_BUS:
442 bus = (bus_entry_ptr)entry;
443 mptable_nbusses++;
444 if (bus->bus_id > mptable_maxbusid)
445 mptable_maxbusid = bus->bus_id;
446 break;
447 case MPCT_ENTRY_IOAPIC:
448 apic = (io_apic_entry_ptr)entry;
449 if (apic->apic_flags & IOAPICENTRY_FLAG_EN)
450 mptable_nioapics++;
451 break;
452 }
453 }
454
455 /*
456 * Count items in the table.
457 */
458 static void
459 mptable_count_items(void)
460 {
461
462 /* Is this a pre-defined config? */
463 if (mpfps->config_type != 0) {
464 mptable_nioapics = 1;
465 switch (mpfps->config_type) {
466 case 1:
467 case 2:
468 case 3:
469 case 4:
470 mptable_nbusses = 1;
471 break;
472 case 5:
473 case 6:
474 case 7:
475 mptable_nbusses = 2;
476 break;
477 default:
478 panic("Unknown pre-defined MP Table config type %d",
479 mpfps->config_type);
480 }
481 mptable_maxbusid = mptable_nbusses - 1;
482 } else
483 mptable_walk_table(mptable_count_items_handler, NULL);
484 }
485
486 /*
487 * Add a bus or I/O APIC from an entry in the table.
488 */
489 static void
490 mptable_parse_apics_and_busses_handler(u_char *entry, void *arg __unused)
491 {
492 io_apic_entry_ptr apic;
493 bus_entry_ptr bus;
494 enum busTypes bus_type;
495 int i;
496
497
498 switch (*entry) {
499 case MPCT_ENTRY_BUS:
500 bus = (bus_entry_ptr)entry;
501 bus_type = lookup_bus_type(bus->bus_type);
502 if (bus_type == UNKNOWN_BUSTYPE) {
503 printf("MPTable: Unknown bus %d type \"", bus->bus_id);
504 for (i = 0; i < 6; i++)
505 printf("%c", bus->bus_type[i]);
506 printf("\"\n");
507 }
508 busses[bus->bus_id].bus_id = bus->bus_id;
509 busses[bus->bus_id].bus_type = bus_type;
510 break;
511 case MPCT_ENTRY_IOAPIC:
512 apic = (io_apic_entry_ptr)entry;
513 if (!(apic->apic_flags & IOAPICENTRY_FLAG_EN))
514 break;
515 if (apic->apic_id > MAX_APIC_ID)
516 panic("%s: I/O APIC ID %d too high", __func__,
517 apic->apic_id);
518 if (ioapics[apic->apic_id] != NULL)
519 panic("%s: Double APIC ID %d", __func__,
520 apic->apic_id);
521 ioapics[apic->apic_id] = ioapic_create(apic->apic_address,
522 apic->apic_id, -1);
523 break;
524 default:
525 break;
526 }
527 }
528
529 /*
530 * Enumerate I/O APIC's and busses.
531 */
532 static void
533 mptable_parse_apics_and_busses(void)
534 {
535
536 /* Is this a pre-defined config? */
537 if (mpfps->config_type != 0) {
538 ioapics[2] = ioapic_create(DEFAULT_IO_APIC_BASE, 2, 0);
539 busses[0].bus_id = 0;
540 busses[0].bus_type = default_data[mpfps->config_type - 1][2];
541 if (mptable_nbusses > 1) {
542 busses[1].bus_id = 1;
543 busses[1].bus_type =
544 default_data[mpfps->config_type - 1][4];
545 }
546 } else
547 mptable_walk_table(mptable_parse_apics_and_busses_handler,
548 NULL);
549 }
550
551 /*
552 * Determine conforming polarity for a given bus type.
553 */
554 static enum intr_polarity
555 conforming_polarity(u_char src_bus, u_char src_bus_irq)
556 {
557
558 KASSERT(src_bus <= mptable_maxbusid, ("bus id %d too large", src_bus));
559 switch (busses[src_bus].bus_type) {
560 case ISA:
561 case EISA:
562 return (INTR_POLARITY_HIGH);
563 case PCI:
564 return (INTR_POLARITY_LOW);
565 default:
566 panic("%s: unknown bus type %d", __func__,
567 busses[src_bus].bus_type);
568 }
569 }
570
571 /*
572 * Determine conforming trigger for a given bus type.
573 */
574 static enum intr_trigger
575 conforming_trigger(u_char src_bus, u_char src_bus_irq)
576 {
577
578 KASSERT(src_bus <= mptable_maxbusid, ("bus id %d too large", src_bus));
579 switch (busses[src_bus].bus_type) {
580 case ISA:
581 if (elcr_found)
582 return (elcr_read_trigger(src_bus_irq));
583 else
584 return (INTR_TRIGGER_EDGE);
585 case PCI:
586 return (INTR_TRIGGER_LEVEL);
587 case EISA:
588 KASSERT(src_bus_irq < 16, ("Invalid EISA IRQ %d", src_bus_irq));
589 KASSERT(elcr_found, ("Missing ELCR"));
590 return (elcr_read_trigger(src_bus_irq));
591 default:
592 panic("%s: unknown bus type %d", __func__,
593 busses[src_bus].bus_type);
594 }
595 }
596
597 static enum intr_polarity
598 intentry_polarity(int_entry_ptr intr)
599 {
600
601 switch (intr->int_flags & INTENTRY_FLAGS_POLARITY) {
602 case INTENTRY_FLAGS_POLARITY_CONFORM:
603 return (conforming_polarity(intr->src_bus_id,
604 intr->src_bus_irq));
605 case INTENTRY_FLAGS_POLARITY_ACTIVEHI:
606 return (INTR_POLARITY_HIGH);
607 case INTENTRY_FLAGS_POLARITY_ACTIVELO:
608 return (INTR_POLARITY_LOW);
609 default:
610 panic("Bogus interrupt flags");
611 }
612 }
613
614 static enum intr_trigger
615 intentry_trigger(int_entry_ptr intr)
616 {
617
618 switch (intr->int_flags & INTENTRY_FLAGS_TRIGGER) {
619 case INTENTRY_FLAGS_TRIGGER_CONFORM:
620 return (conforming_trigger(intr->src_bus_id,
621 intr->src_bus_irq));
622 case INTENTRY_FLAGS_TRIGGER_EDGE:
623 return (INTR_TRIGGER_EDGE);
624 case INTENTRY_FLAGS_TRIGGER_LEVEL:
625 return (INTR_TRIGGER_LEVEL);
626 default:
627 panic("Bogus interrupt flags");
628 }
629 }
630
631 /*
632 * Parse an interrupt entry for an I/O interrupt routed to a pin on an I/O APIC.
633 */
634 static void
635 mptable_parse_io_int(int_entry_ptr intr)
636 {
637 void *ioapic;
638 u_int pin, apic_id;
639
640 apic_id = intr->dst_apic_id;
641 if (intr->dst_apic_id == 0xff) {
642 /*
643 * An APIC ID of 0xff means that the interrupt is connected
644 * to the specified pin on all I/O APICs in the system. If
645 * there is only one I/O APIC, then use that APIC to route
646 * the interrupts. If there is more than one I/O APIC, then
647 * punt.
648 */
649 if (mptable_nioapics == 1) {
650 apic_id = 0;
651 while (ioapics[apic_id] == NULL)
652 apic_id++;
653 } else {
654 printf(
655 "MPTable: Ignoring global interrupt entry for pin %d\n",
656 intr->dst_apic_int);
657 return;
658 }
659 }
660 if (apic_id > MAX_APIC_ID) {
661 printf("MPTable: Ignoring interrupt entry for ioapic%d\n",
662 intr->dst_apic_id);
663 return;
664 }
665 ioapic = ioapics[apic_id];
666 if (ioapic == NULL) {
667 printf(
668 "MPTable: Ignoring interrupt entry for missing ioapic%d\n",
669 apic_id);
670 return;
671 }
672 pin = intr->dst_apic_int;
673 switch (intr->int_type) {
674 case INTENTRY_TYPE_INT:
675 switch (busses[intr->src_bus_id].bus_type) {
676 case NOBUS:
677 panic("interrupt from missing bus");
678 case ISA:
679 case EISA:
680 if (busses[intr->src_bus_id].bus_type == ISA)
681 ioapic_set_bus(ioapic, pin, APIC_BUS_ISA);
682 else
683 ioapic_set_bus(ioapic, pin, APIC_BUS_EISA);
684 if (intr->src_bus_irq == pin)
685 break;
686 ioapic_remap_vector(ioapic, pin, intr->src_bus_irq);
687 if (ioapic_get_vector(ioapic, intr->src_bus_irq) ==
688 intr->src_bus_irq)
689 ioapic_disable_pin(ioapic, intr->src_bus_irq);
690 break;
691 case PCI:
692 ioapic_set_bus(ioapic, pin, APIC_BUS_PCI);
693 break;
694 default:
695 ioapic_set_bus(ioapic, pin, APIC_BUS_UNKNOWN);
696 break;
697 }
698 break;
699 case INTENTRY_TYPE_NMI:
700 ioapic_set_nmi(ioapic, pin);
701 break;
702 case INTENTRY_TYPE_SMI:
703 ioapic_set_smi(ioapic, pin);
704 break;
705 case INTENTRY_TYPE_EXTINT:
706 ioapic_set_extint(ioapic, pin);
707 break;
708 default:
709 panic("%s: invalid interrupt entry type %d\n", __func__,
710 intr->int_type);
711 }
712 if (intr->int_type == INTENTRY_TYPE_INT ||
713 (intr->int_flags & INTENTRY_FLAGS_TRIGGER) !=
714 INTENTRY_FLAGS_TRIGGER_CONFORM)
715 ioapic_set_triggermode(ioapic, pin, intentry_trigger(intr));
716 if (intr->int_type == INTENTRY_TYPE_INT ||
717 (intr->int_flags & INTENTRY_FLAGS_POLARITY) !=
718 INTENTRY_FLAGS_POLARITY_CONFORM)
719 ioapic_set_polarity(ioapic, pin, intentry_polarity(intr));
720 }
721
722 /*
723 * Parse an interrupt entry for a local APIC LVT pin.
724 */
725 static void
726 mptable_parse_local_int(int_entry_ptr intr)
727 {
728 u_int apic_id, pin;
729
730 if (intr->dst_apic_id == 0xff)
731 apic_id = APIC_ID_ALL;
732 else
733 apic_id = intr->dst_apic_id;
734 if (intr->dst_apic_int == 0)
735 pin = LVT_LINT0;
736 else
737 pin = LVT_LINT1;
738 switch (intr->int_type) {
739 case INTENTRY_TYPE_INT:
740 #if 1
741 printf(
742 "MPTable: Ignoring vectored local interrupt for LINTIN%d vector %d\n",
743 intr->dst_apic_int, intr->src_bus_irq);
744 return;
745 #else
746 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_FIXED);
747 break;
748 #endif
749 case INTENTRY_TYPE_NMI:
750 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_NMI);
751 break;
752 case INTENTRY_TYPE_SMI:
753 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_SMI);
754 break;
755 case INTENTRY_TYPE_EXTINT:
756 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_EXTINT);
757 break;
758 default:
759 panic("%s: invalid interrupt entry type %d\n", __func__,
760 intr->int_type);
761 }
762 if ((intr->int_flags & INTENTRY_FLAGS_TRIGGER) !=
763 INTENTRY_FLAGS_TRIGGER_CONFORM)
764 lapic_set_lvt_triggermode(apic_id, pin,
765 intentry_trigger(intr));
766 if ((intr->int_flags & INTENTRY_FLAGS_POLARITY) !=
767 INTENTRY_FLAGS_POLARITY_CONFORM)
768 lapic_set_lvt_polarity(apic_id, pin, intentry_polarity(intr));
769 }
770
771 /*
772 * Parse interrupt entries.
773 */
774 static void
775 mptable_parse_ints_handler(u_char *entry, void *arg __unused)
776 {
777 int_entry_ptr intr;
778
779 intr = (int_entry_ptr)entry;
780 switch (*entry) {
781 case MPCT_ENTRY_INT:
782 mptable_parse_io_int(intr);
783 break;
784 case MPCT_ENTRY_LOCAL_INT:
785 mptable_parse_local_int(intr);
786 break;
787 }
788 }
789
790 /*
791 * Configure interrupt pins for a default configuration. For details see
792 * Table 5-2 in Section 5 of the MP Table specification.
793 */
794 static void
795 mptable_parse_default_config_ints(void)
796 {
797 struct INTENTRY entry;
798 int pin;
799
800 /*
801 * All default configs route IRQs from bus 0 to the first 16 pins
802 * of the first I/O APIC with an APIC ID of 2.
803 */
804 entry.type = MPCT_ENTRY_INT;
805 entry.int_flags = INTENTRY_FLAGS_POLARITY_CONFORM |
806 INTENTRY_FLAGS_TRIGGER_CONFORM;
807 entry.src_bus_id = 0;
808 entry.dst_apic_id = 2;
809
810 /* Run through all 16 pins. */
811 for (pin = 0; pin < 16; pin++) {
812 entry.dst_apic_int = pin;
813 switch (pin) {
814 case 0:
815 /* Pin 0 is an ExtINT pin. */
816 entry.int_type = INTENTRY_TYPE_EXTINT;
817 break;
818 case 2:
819 /* IRQ 0 is routed to pin 2. */
820 entry.int_type = INTENTRY_TYPE_INT;
821 entry.src_bus_irq = 0;
822 break;
823 default:
824 /* All other pins are identity mapped. */
825 entry.int_type = INTENTRY_TYPE_INT;
826 entry.src_bus_irq = pin;
827 break;
828 }
829 mptable_parse_io_int(&entry);
830 }
831
832 /* Certain configs disable certain pins. */
833 if (mpfps->config_type == 7)
834 ioapic_disable_pin(ioapics[2], 0);
835 if (mpfps->config_type == 2) {
836 ioapic_disable_pin(ioapics[2], 2);
837 ioapic_disable_pin(ioapics[2], 13);
838 }
839 }
840
841 /*
842 * Configure the interrupt pins
843 */
844 static void
845 mptable_parse_ints(void)
846 {
847
848 /* Is this a pre-defined config? */
849 if (mpfps->config_type != 0) {
850 /* Configure LINT pins. */
851 lapic_set_lvt_mode(APIC_ID_ALL, LVT_LINT0, APIC_LVT_DM_EXTINT);
852 lapic_set_lvt_mode(APIC_ID_ALL, LVT_LINT1, APIC_LVT_DM_NMI);
853
854 /* Configure I/O APIC pins. */
855 mptable_parse_default_config_ints();
856 } else
857 mptable_walk_table(mptable_parse_ints_handler, NULL);
858 }
859
860 #ifdef MPTABLE_FORCE_HTT
861 /*
862 * Perform a hyperthreading "fix-up" to enumerate any logical CPU's
863 * that aren't already listed in the table.
864 *
865 * XXX: We assume that all of the physical CPUs in the
866 * system have the same number of logical CPUs.
867 *
868 * XXX: We assume that APIC ID's are allocated such that
869 * the APIC ID's for a physical processor are aligned
870 * with the number of logical CPU's in the processor.
871 */
872 static void
873 mptable_hyperthread_fixup(u_long id_mask)
874 {
875 u_int i, id, logical_cpus;
876
877 /* Nothing to do if there is no HTT support. */
878 if ((cpu_feature & CPUID_HTT) == 0)
879 return;
880 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
881 if (logical_cpus <= 1)
882 return;
883
884 /*
885 * For each APIC ID of a CPU that is set in the mask,
886 * scan the other candidate APIC ID's for this
887 * physical processor. If any of those ID's are
888 * already in the table, then kill the fixup.
889 */
890 for (id = 0; id <= MAX_LAPIC_ID; id++) {
891 if ((id_mask & 1 << id) == 0)
892 continue;
893 /* First, make sure we are on a logical_cpus boundary. */
894 if (id % logical_cpus != 0)
895 return;
896 for (i = id + 1; i < id + logical_cpus; i++)
897 if ((id_mask & 1 << i) != 0)
898 return;
899 }
900
901 /*
902 * Ok, the ID's checked out, so perform the fixup by
903 * adding the logical CPUs.
904 */
905 while ((id = ffsl(id_mask)) != 0) {
906 id--;
907 for (i = id + 1; i < id + logical_cpus; i++) {
908 if (bootverbose)
909 printf(
910 "MPTable: Adding logical CPU %d from main CPU %d\n",
911 i, id);
912 lapic_create(i, 0);
913 }
914 id_mask &= ~(1 << id);
915 }
916 }
917 #endif /* MPTABLE_FORCE_HTT */
918
919 /*
920 * Support code for routing PCI interrupts using the MP Table.
921 */
922 static void
923 mptable_pci_setup(void)
924 {
925 int i;
926
927 /*
928 * Find the first pci bus and call it 0. Panic if pci0 is not
929 * bus zero and there are multiple PCI busses.
930 */
931 for (i = 0; i <= mptable_maxbusid; i++)
932 if (busses[i].bus_type == PCI) {
933 if (pci0 == -1)
934 pci0 = i;
935 else if (pci0 != 0)
936 panic(
937 "MPTable contains multiple PCI busses but no PCI bus 0");
938 }
939 }
940
941 static void
942 mptable_pci_probe_table_handler(u_char *entry, void *arg)
943 {
944 struct pci_probe_table_args *args;
945 int_entry_ptr intr;
946
947 if (*entry != MPCT_ENTRY_INT)
948 return;
949 intr = (int_entry_ptr)entry;
950 args = (struct pci_probe_table_args *)arg;
951 KASSERT(args->bus <= mptable_maxbusid,
952 ("bus %d is too big", args->bus));
953 KASSERT(busses[args->bus].bus_type == PCI, ("probing for non-PCI bus"));
954 if (intr->src_bus_id == args->bus)
955 args->found = 1;
956 }
957
958 int
959 mptable_pci_probe_table(int bus)
960 {
961 struct pci_probe_table_args args;
962
963 if (bus < 0)
964 return (EINVAL);
965 if (mpct == NULL || pci0 == -1 || pci0 + bus > mptable_maxbusid)
966 return (ENXIO);
967 if (busses[pci0 + bus].bus_type != PCI)
968 return (ENXIO);
969 args.bus = pci0 + bus;
970 args.found = 0;
971 mptable_walk_table(mptable_pci_probe_table_handler, &args);
972 if (args.found == 0)
973 return (ENXIO);
974 return (0);
975 }
976
977 static void
978 mptable_pci_route_interrupt_handler(u_char *entry, void *arg)
979 {
980 struct pci_route_interrupt_args *args;
981 int_entry_ptr intr;
982 int vector;
983
984 if (*entry != MPCT_ENTRY_INT)
985 return;
986 intr = (int_entry_ptr)entry;
987 args = (struct pci_route_interrupt_args *)arg;
988 if (intr->src_bus_id != args->bus || intr->src_bus_irq != args->irq)
989 return;
990
991 /* Make sure the APIC maps to a known APIC. */
992 KASSERT(ioapics[intr->dst_apic_id] != NULL,
993 ("No I/O APIC %d to route interrupt to", intr->dst_apic_id));
994
995 /*
996 * Look up the vector for this APIC / pin combination. If we
997 * have previously matched an entry for this PCI IRQ but it
998 * has the same vector as this entry, just return. Otherwise,
999 * we use the vector for this APIC / pin combination.
1000 */
1001 vector = ioapic_get_vector(ioapics[intr->dst_apic_id],
1002 intr->dst_apic_int);
1003 if (args->vector == vector)
1004 return;
1005 KASSERT(args->vector == -1,
1006 ("Multiple IRQs for PCI interrupt %d.%d.INT%c: %d and %d\n",
1007 args->bus, args->irq >> 2, 'A' + (args->irq & 0x3), args->vector,
1008 vector));
1009 args->vector = vector;
1010 }
1011
1012 int
1013 mptable_pci_route_interrupt(device_t pcib, device_t dev, int pin)
1014 {
1015 struct pci_route_interrupt_args args;
1016 int slot;
1017
1018 /* Like ACPI, pin numbers are 0-3, not 1-4. */
1019 pin--;
1020 KASSERT(pci0 != -1, ("do not know how to route PCI interrupts"));
1021 args.bus = pci_get_bus(dev) + pci0;
1022 slot = pci_get_slot(dev);
1023
1024 /*
1025 * PCI interrupt entries in the MP Table encode both the slot and
1026 * pin into the IRQ with the pin being the two least significant
1027 * bits, the slot being the next five bits, and the most significant
1028 * bit being reserved.
1029 */
1030 args.irq = slot << 2 | pin;
1031 args.vector = -1;
1032 mptable_walk_table(mptable_pci_route_interrupt_handler, &args);
1033 if (args.vector < 0) {
1034 device_printf(pcib, "unable to route slot %d INT%c\n", slot,
1035 'A' + pin);
1036 return (PCI_INVALID_IRQ);
1037 }
1038 if (bootverbose)
1039 device_printf(pcib, "slot %d INT%c routed to irq %d\n", slot,
1040 'A' + pin, args.vector);
1041 return (args.vector);
1042 }
Cache object: 42496c8c4583e6ece12503dfb3776ce3
|