1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD: src/sys/amd64/include/apicvar.h,v 1.26 2008/12/11 15:56:30 jhb Exp $
30 */
31
32 #ifndef _MACHINE_APICVAR_H_
33 #define _MACHINE_APICVAR_H_
34
35 #include <machine/segments.h>
36
37 /*
38 * Local && I/O APIC variable definitions.
39 */
40
41 /*
42 * Layout of local APIC interrupt vectors:
43 *
44 * 0xff (255) +-------------+
45 * | | 15 (Spurious / IPIs / Local Interrupts)
46 * 0xf0 (240) +-------------+
47 * | | 14 (I/O Interrupts / Timer)
48 * 0xe0 (224) +-------------+
49 * | | 13 (I/O Interrupts)
50 * 0xd0 (208) +-------------+
51 * | | 12 (I/O Interrupts)
52 * 0xc0 (192) +-------------+
53 * | | 11 (I/O Interrupts)
54 * 0xb0 (176) +-------------+
55 * | | 10 (I/O Interrupts)
56 * 0xa0 (160) +-------------+
57 * | | 9 (I/O Interrupts)
58 * 0x90 (144) +-------------+
59 * | | 8 (I/O Interrupts / System Calls)
60 * 0x80 (128) +-------------+
61 * | | 7 (I/O Interrupts)
62 * 0x70 (112) +-------------+
63 * | | 6 (I/O Interrupts)
64 * 0x60 (96) +-------------+
65 * | | 5 (I/O Interrupts)
66 * 0x50 (80) +-------------+
67 * | | 4 (I/O Interrupts)
68 * 0x40 (64) +-------------+
69 * | | 3 (I/O Interrupts)
70 * 0x30 (48) +-------------+
71 * | | 2 (ATPIC Interrupts)
72 * 0x20 (32) +-------------+
73 * | | 1 (Exceptions, traps, faults, etc.)
74 * 0x10 (16) +-------------+
75 * | | 0 (Exceptions, traps, faults, etc.)
76 * 0x00 (0) +-------------+
77 *
78 * Note: 0x80 needs to be handled specially and not allocated to an
79 * I/O device!
80 */
81
82 #define MAX_APIC_ID 0xfe
83 #define APIC_ID_ALL 0xff
84
85 /* I/O Interrupts are used for external devices such as ISA, PCI, etc. */
86 #define APIC_IO_INTS (IDT_IO_INTS + 16)
87 #define APIC_NUM_IOINTS 191
88
89 /* The timer interrupt is used for clock handling and drives hardclock, etc. */
90 #define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS)
91
92 /*
93 ********************* !!! WARNING !!! ******************************
94 * Each local apic has an interrupt receive fifo that is two entries deep
95 * for each interrupt priority class (higher 4 bits of interrupt vector).
96 * Once the fifo is full the APIC can no longer receive interrupts for this
97 * class and sending IPIs from other CPUs will be blocked.
98 * To avoid deadlocks there should be no more than two IPI interrupts
99 * pending at the same time.
100 * Currently this is guaranteed by dividing the IPIs in two groups that have
101 * each at most one IPI interrupt pending. The first group is protected by the
102 * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user
103 * at a time) The second group uses a single interrupt and a bitmap to avoid
104 * redundant IPI interrupts.
105 *
106 * Right now IPI_STOP used by kdb shares the interrupt priority class with
107 * the two IPI groups mentioned above. As such IPI_STOP may cause a deadlock.
108 * Eventually IPI_STOP should use NMI IPIs - this would eliminate this and
109 * other deadlocks caused by IPI_STOP.
110 */
111
112 /* Interrupts for local APIC LVT entries other than the timer. */
113 #define APIC_LOCAL_INTS 240
114 #define APIC_ERROR_INT APIC_LOCAL_INTS
115 #define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1)
116
117 #define APIC_IPI_INTS (APIC_LOCAL_INTS + 2)
118 #define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */
119 #define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */
120 #define IPI_INVLPG (APIC_IPI_INTS + 2)
121 #define IPI_INVLRNG (APIC_IPI_INTS + 3)
122 #define IPI_INVLCACHE (APIC_IPI_INTS + 4)
123 /* Vector to handle bitmap based IPIs */
124 #define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 6)
125
126 /* IPIs handled by IPI_BITMAPED_VECTOR (XXX ups is there a better place?) */
127 #define IPI_AST 0 /* Generate software trap. */
128 #define IPI_PREEMPT 1
129 #define IPI_BITMAP_LAST IPI_PREEMPT
130 #define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST)
131
132 #define IPI_STOP (APIC_IPI_INTS + 7) /* Stop CPU until restarted. */
133
134 /*
135 * The spurious interrupt can share the priority class with the IPIs since
136 * it is not a normal interrupt. (Does not use the APIC's interrupt fifo)
137 */
138 #define APIC_SPURIOUS_INT 255
139
140 #define LVT_LINT0 0
141 #define LVT_LINT1 1
142 #define LVT_TIMER 2
143 #define LVT_ERROR 3
144 #define LVT_PMC 4
145 #define LVT_THERMAL 5
146 #define LVT_MAX LVT_THERMAL
147
148 #ifndef LOCORE
149
150 #define APIC_IPI_DEST_SELF -1
151 #define APIC_IPI_DEST_ALL -2
152 #define APIC_IPI_DEST_OTHERS -3
153
154 #define APIC_BUS_UNKNOWN -1
155 #define APIC_BUS_ISA 0
156 #define APIC_BUS_EISA 1
157 #define APIC_BUS_PCI 2
158 #define APIC_BUS_MAX APIC_BUS_PCI
159
160 /*
161 * An APIC enumerator is a psuedo bus driver that enumerates APIC's including
162 * CPU's and I/O APIC's.
163 */
164 struct apic_enumerator {
165 const char *apic_name;
166 int (*apic_probe)(void);
167 int (*apic_probe_cpus)(void);
168 int (*apic_setup_local)(void);
169 int (*apic_setup_io)(void);
170 SLIST_ENTRY(apic_enumerator) apic_next;
171 };
172
173 inthand_t
174 IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3),
175 IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6),
176 IDTVEC(apic_isr7), IDTVEC(spuriousint), IDTVEC(timerint);
177
178 extern vm_paddr_t lapic_paddr;
179
180 u_int apic_alloc_vector(u_int irq);
181 u_int apic_alloc_vectors(u_int *irqs, u_int count, u_int align);
182 void apic_disable_vector(u_int vector);
183 void apic_enable_vector(u_int vector);
184 void apic_free_vector(u_int vector, u_int irq);
185 u_int apic_idt_to_irq(u_int vector);
186 void apic_register_enumerator(struct apic_enumerator *enumerator);
187 void *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase);
188 int ioapic_disable_pin(void *cookie, u_int pin);
189 int ioapic_get_vector(void *cookie, u_int pin);
190 void ioapic_register(void *cookie);
191 int ioapic_remap_vector(void *cookie, u_int pin, int vector);
192 int ioapic_set_bus(void *cookie, u_int pin, int bus_type);
193 int ioapic_set_extint(void *cookie, u_int pin);
194 int ioapic_set_nmi(void *cookie, u_int pin);
195 int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol);
196 int ioapic_set_triggermode(void *cookie, u_int pin,
197 enum intr_trigger trigger);
198 int ioapic_set_smi(void *cookie, u_int pin);
199 void lapic_create(u_int apic_id, int boot_cpu);
200 void lapic_disable(void);
201 void lapic_dump(const char *str);
202 void lapic_eoi(void);
203 u_int lapic_error(void);
204 int lapic_id(void);
205 void lapic_init(vm_paddr_t addr);
206 int lapic_intr_pending(u_int vector);
207 void lapic_ipi_raw(register_t icrlo, u_int dest);
208 void lapic_ipi_vectored(u_int vector, int dest);
209 int lapic_ipi_wait(int delay);
210 void lapic_handle_intr(int vector, struct trapframe *frame);
211 void lapic_handle_timer(struct trapframe *frame);
212 void lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id);
213 int lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked);
214 int lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode);
215 int lapic_set_lvt_polarity(u_int apic_id, u_int lvt,
216 enum intr_polarity pol);
217 int lapic_set_lvt_triggermode(u_int apic_id, u_int lvt,
218 enum intr_trigger trigger);
219 void lapic_set_tpr(u_int vector);
220 void lapic_setup(int boot);
221 int lapic_setup_clock(void);
222
223 #endif /* !LOCORE */
224 #endif /* _MACHINE_APICVAR_H_ */
225 Cache object: 03c4094a7dad9c4a9c08cab8deb96f78
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