1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/amd64/include/intr_machdep.h,v 1.19 2008/03/14 19:41:46 jhb Exp $
27 */
28
29 #ifndef __MACHINE_INTR_MACHDEP_H__
30 #define __MACHINE_INTR_MACHDEP_H__
31
32 #ifdef _KERNEL
33
34 /*
35 * The maximum number of I/O interrupts we allow. This number is rather
36 * arbitrary as it is just the maximum IRQ resource value. The interrupt
37 * source for a given IRQ maps that I/O interrupt to device interrupt
38 * source whether it be a pin on an interrupt controller or an MSI interrupt.
39 * The 16 ISA IRQs are assigned fixed IDT vectors, but all other device
40 * interrupts allocate IDT vectors on demand. Currently we have 191 IDT
41 * vectors available for device interrupts. On many systems with I/O APICs,
42 * a lot of the IRQs are not used, so this number can be much larger than
43 * 191 and still be safe since only interrupt sources in actual use will
44 * allocate IDT vectors.
45 *
46 * The first 255 IRQs (0 - 254) are reserved for ISA IRQs and PCI intline IRQs.
47 * IRQ values beyond 256 are used by MSI. We leave 255 unused to avoid
48 * confusion since 255 is used in PCI to indicate an invalid IRQ.
49 */
50 #define NUM_MSI_INTS 128
51 #define FIRST_MSI_INT 256
52 #define NUM_IO_INTS (FIRST_MSI_INT + NUM_MSI_INTS)
53
54 /*
55 * Default base address for MSI messages on x86 platforms.
56 */
57 #define MSI_INTEL_ADDR_BASE 0xfee00000
58
59 /*
60 * - 1 ??? dummy counter.
61 * - 2 counters for each I/O interrupt.
62 * - 1 counter for each CPU for lapic timer.
63 * - 7 counters for each CPU for IPI counters for SMP.
64 */
65 #ifdef SMP
66 #define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 7) * MAXCPU)
67 #else
68 #define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1)
69 #endif
70
71 #ifndef LOCORE
72
73 typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
74
75 #define IDTVEC(name) __CONCAT(X,name)
76
77 struct intsrc;
78
79 /*
80 * Methods that a PIC provides to mask/unmask a given interrupt source,
81 * "turn on" the interrupt on the CPU side by setting up an IDT entry, and
82 * return the vector associated with this source.
83 */
84 struct pic {
85 void (*pic_enable_source)(struct intsrc *);
86 void (*pic_disable_source)(struct intsrc *, int);
87 void (*pic_eoi_source)(struct intsrc *);
88 void (*pic_enable_intr)(struct intsrc *);
89 void (*pic_disable_intr)(struct intsrc *);
90 int (*pic_vector)(struct intsrc *);
91 int (*pic_source_pending)(struct intsrc *);
92 void (*pic_suspend)(struct pic *);
93 void (*pic_resume)(struct pic *);
94 int (*pic_config_intr)(struct intsrc *, enum intr_trigger,
95 enum intr_polarity);
96 void (*pic_assign_cpu)(struct intsrc *, u_int apic_id);
97 STAILQ_ENTRY(pic) pics;
98 };
99
100 /* Flags for pic_disable_source() */
101 enum {
102 PIC_EOI,
103 PIC_NO_EOI,
104 };
105
106 /*
107 * An interrupt source. The upper-layer code uses the PIC methods to
108 * control a given source. The lower-layer PIC drivers can store additional
109 * private data in a given interrupt source such as an interrupt pin number
110 * or an I/O APIC pointer.
111 */
112 struct intsrc {
113 struct pic *is_pic;
114 struct intr_event *is_event;
115 u_long *is_count;
116 u_long *is_straycount;
117 u_int is_index;
118 u_int is_handlers;
119 };
120
121 struct trapframe;
122
123 extern struct mtx icu_lock;
124 extern int elcr_found;
125
126 #ifndef DEV_ATPIC
127 void atpic_reset(void);
128 #endif
129 /* XXX: The elcr_* prototypes probably belong somewhere else. */
130 int elcr_probe(void);
131 enum intr_trigger elcr_read_trigger(u_int irq);
132 void elcr_resume(void);
133 void elcr_write_trigger(u_int irq, enum intr_trigger trigger);
134 #ifdef SMP
135 void intr_add_cpu(u_int cpu);
136 #endif
137 int intr_add_handler(const char *name, int vector, driver_filter_t filter,
138 driver_intr_t handler, void *arg, enum intr_type flags,
139 void **cookiep);
140 #ifdef SMP
141 int intr_bind(u_int vector, u_char cpu);
142 #endif
143 int intr_config_intr(int vector, enum intr_trigger trig,
144 enum intr_polarity pol);
145 void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame);
146 struct intsrc *intr_lookup_source(int vector);
147 int intr_register_pic(struct pic *pic);
148 int intr_register_source(struct intsrc *isrc);
149 int intr_remove_handler(void *cookie);
150 void intr_resume(void);
151 void intr_suspend(void);
152 void intrcnt_add(const char *name, u_long **countp);
153 void nexus_add_irq(u_long irq);
154 int msi_alloc(device_t dev, int count, int maxcount, int *irqs);
155 void msi_init(void);
156 int msi_map(int irq, uint64_t *addr, uint32_t *data);
157 int msi_release(int *irqs, int count);
158 int msix_alloc(device_t dev, int *irq);
159 int msix_release(int irq);
160
161 #endif /* !LOCORE */
162 #endif /* _KERNEL */
163 #endif /* !__MACHINE_INTR_MACHDEP_H__ */
164 Cache object: efe96755b1fe1b9aa5d44f78866d3abf
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