FreeBSD/Linux Kernel Cross Reference
sys/amd64/isa/clock.c
1 /*-
2 * Copyright (c) 1990 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 4. Neither the name of the University nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
33 */
34
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
37
38 /*
39 * Routines to handle clock hardware.
40 */
41
42 /*
43 * inittodr, settodr and support routines written
44 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
45 *
46 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
47 */
48
49 #include "opt_clock.h"
50 #include "opt_isa.h"
51
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/bus.h>
55 #include <sys/lock.h>
56 #include <sys/kdb.h>
57 #include <sys/mutex.h>
58 #include <sys/proc.h>
59 #include <sys/time.h>
60 #include <sys/timetc.h>
61 #include <sys/kernel.h>
62 #include <sys/limits.h>
63 #include <sys/module.h>
64 #include <sys/sysctl.h>
65 #include <sys/cons.h>
66 #include <sys/power.h>
67
68 #include <machine/clock.h>
69 #include <machine/frame.h>
70 #include <machine/intr_machdep.h>
71 #include <machine/md_var.h>
72 #include <machine/psl.h>
73 #ifdef SMP
74 #include <machine/smp.h>
75 #endif
76 #include <machine/specialreg.h>
77
78 #include <amd64/isa/isa.h>
79 #include <isa/rtc.h>
80 #ifdef DEV_ISA
81 #include <isa/isavar.h>
82 #endif
83 #include <amd64/isa/timerreg.h>
84
85 /*
86 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
87 * can use a simple formula for leap years.
88 */
89 #define LEAPYEAR(y) (((u_int)(y) % 4 == 0) ? 1 : 0)
90 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
91
92 #define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x))
93
94 int adjkerntz; /* local offset from GMT in seconds */
95 int clkintr_pending;
96 int disable_rtc_set; /* disable resettodr() if != 0 */
97 int pscnt = 1;
98 int psdiv = 1;
99 int statclock_disable;
100 #ifndef TIMER_FREQ
101 #define TIMER_FREQ 1193182
102 #endif
103 u_int timer_freq = TIMER_FREQ;
104 int timer0_max_count;
105 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
106 struct mtx clock_lock;
107
108 static int beeping = 0;
109 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
110 static u_int hardclock_max_count;
111 static struct intsrc *i8254_intsrc;
112 static u_int32_t i8254_lastcount;
113 static u_int32_t i8254_offset;
114 static int (*i8254_pending)(struct intsrc *);
115 static int i8254_ticked;
116 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
117 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
118
119 /* Values for timerX_state: */
120 #define RELEASED 0
121 #define RELEASE_PENDING 1
122 #define ACQUIRED 2
123 #define ACQUIRE_PENDING 3
124
125 static u_char timer2_state;
126
127 static unsigned i8254_get_timecount(struct timecounter *tc);
128 static void set_timer_freq(u_int freq, int intr_freq);
129
130 static struct timecounter i8254_timecounter = {
131 i8254_get_timecount, /* get_timecount */
132 0, /* no poll_pps */
133 ~0u, /* counter_mask */
134 0, /* frequency */
135 "i8254", /* name */
136 0 /* quality */
137 };
138
139 static void
140 clkintr(struct clockframe *frame)
141 {
142
143 if (timecounter->tc_get_timecount == i8254_get_timecount) {
144 mtx_lock_spin(&clock_lock);
145 if (i8254_ticked)
146 i8254_ticked = 0;
147 else {
148 i8254_offset += timer0_max_count;
149 i8254_lastcount = 0;
150 }
151 clkintr_pending = 0;
152 mtx_unlock_spin(&clock_lock);
153 }
154 hardclock(frame);
155 #ifdef SMP
156 forward_hardclock();
157 #endif
158 }
159
160 int
161 acquire_timer2(int mode)
162 {
163
164 if (timer2_state != RELEASED)
165 return (-1);
166 timer2_state = ACQUIRED;
167
168 /*
169 * This access to the timer registers is as atomic as possible
170 * because it is a single instruction. We could do better if we
171 * knew the rate. Use of splclock() limits glitches to 10-100us,
172 * and this is probably good enough for timer2, so we aren't as
173 * careful with it as with timer0.
174 */
175 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
176
177 return (0);
178 }
179
180 int
181 release_timer2()
182 {
183
184 if (timer2_state != ACQUIRED)
185 return (-1);
186 timer2_state = RELEASED;
187 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
188 return (0);
189 }
190
191 /*
192 * This routine receives statistical clock interrupts from the RTC.
193 * As explained above, these occur at 128 interrupts per second.
194 * When profiling, we receive interrupts at a rate of 1024 Hz.
195 *
196 * This does not actually add as much overhead as it sounds, because
197 * when the statistical clock is active, the hardclock driver no longer
198 * needs to keep (inaccurate) statistics on its own. This decouples
199 * statistics gathering from scheduling interrupts.
200 *
201 * The RTC chip requires that we read status register C (RTC_INTR)
202 * to acknowledge an interrupt, before it will generate the next one.
203 * Under high interrupt load, rtcintr() can be indefinitely delayed and
204 * the clock can tick immediately after the read from RTC_INTR. In this
205 * case, the mc146818A interrupt signal will not drop for long enough
206 * to register with the 8259 PIC. If an interrupt is missed, the stat
207 * clock will halt, considerably degrading system performance. This is
208 * why we use 'while' rather than a more straightforward 'if' below.
209 * Stat clock ticks can still be lost, causing minor loss of accuracy
210 * in the statistics, but the stat clock will no longer stop.
211 */
212 static void
213 rtcintr(struct clockframe *frame)
214 {
215
216 while (rtcin(RTC_INTR) & RTCIR_PERIOD) {
217 if (profprocs != 0) {
218 if (--pscnt == 0)
219 pscnt = psdiv;
220 profclock(frame);
221 }
222 if (pscnt == psdiv)
223 statclock(frame);
224 #ifdef SMP
225 forward_statclock();
226 #endif
227 }
228 }
229
230 #include "opt_ddb.h"
231 #ifdef DDB
232 #include <ddb/ddb.h>
233
234 DB_SHOW_COMMAND(rtc, rtc)
235 {
236 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
237 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
238 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
239 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
240 }
241 #endif /* DDB */
242
243 static int
244 getit(void)
245 {
246 int high, low;
247
248 mtx_lock_spin(&clock_lock);
249
250 /* Select timer0 and latch counter value. */
251 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
252
253 low = inb(TIMER_CNTR0);
254 high = inb(TIMER_CNTR0);
255
256 mtx_unlock_spin(&clock_lock);
257 return ((high << 8) | low);
258 }
259
260 /*
261 * Wait "n" microseconds.
262 * Relies on timer 1 counting down from (timer_freq / hz)
263 * Note: timer had better have been programmed before this is first used!
264 */
265 void
266 DELAY(int n)
267 {
268 int delta, prev_tick, tick, ticks_left;
269
270 #ifdef DELAYDEBUG
271 int getit_calls = 1;
272 int n1;
273 static int state = 0;
274
275 if (state == 0) {
276 state = 1;
277 for (n1 = 1; n1 <= 10000000; n1 *= 10)
278 DELAY(n1);
279 state = 2;
280 }
281 if (state == 1)
282 printf("DELAY(%d)...", n);
283 #endif
284 /*
285 * Guard against the timer being uninitialized if we are called
286 * early for console i/o.
287 */
288 if (timer0_max_count == 0)
289 set_timer_freq(timer_freq, hz);
290
291 /*
292 * Read the counter first, so that the rest of the setup overhead is
293 * counted. Guess the initial overhead is 20 usec (on most systems it
294 * takes about 1.5 usec for each of the i/o's in getit(). The loop
295 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
296 * multiplications and divisions to scale the count take a while).
297 *
298 * However, if ddb is active then use a fake counter since reading
299 * the i8254 counter involves acquiring a lock. ddb must not do
300 * locking for many reasons, but it calls here for at least atkbd
301 * input.
302 */
303 #ifdef KDB
304 if (kdb_active)
305 prev_tick = 1;
306 else
307 #endif
308 prev_tick = getit();
309 n -= 0; /* XXX actually guess no initial overhead */
310 /*
311 * Calculate (n * (timer_freq / 1e6)) without using floating point
312 * and without any avoidable overflows.
313 */
314 if (n <= 0)
315 ticks_left = 0;
316 else if (n < 256)
317 /*
318 * Use fixed point to avoid a slow division by 1000000.
319 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
320 * 2^15 is the first power of 2 that gives exact results
321 * for n between 0 and 256.
322 */
323 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
324 else
325 /*
326 * Don't bother using fixed point, although gcc-2.7.2
327 * generates particularly poor code for the long long
328 * division, since even the slow way will complete long
329 * before the delay is up (unless we're interrupted).
330 */
331 ticks_left = ((u_int)n * (long long)timer_freq + 999999)
332 / 1000000;
333
334 while (ticks_left > 0) {
335 #ifdef KDB
336 if (kdb_active) {
337 inb(0x84);
338 tick = prev_tick - 1;
339 if (tick <= 0)
340 tick = timer0_max_count;
341 } else
342 #endif
343 tick = getit();
344 #ifdef DELAYDEBUG
345 ++getit_calls;
346 #endif
347 delta = prev_tick - tick;
348 prev_tick = tick;
349 if (delta < 0) {
350 delta += timer0_max_count;
351 /*
352 * Guard against timer0_max_count being wrong.
353 * This shouldn't happen in normal operation,
354 * but it may happen if set_timer_freq() is
355 * traced.
356 */
357 if (delta < 0)
358 delta = 0;
359 }
360 ticks_left -= delta;
361 }
362 #ifdef DELAYDEBUG
363 if (state == 1)
364 printf(" %d calls to getit() at %d usec each\n",
365 getit_calls, (n + 5) / getit_calls);
366 #endif
367 }
368
369 static void
370 sysbeepstop(void *chan)
371 {
372 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
373 release_timer2();
374 beeping = 0;
375 }
376
377 int
378 sysbeep(int pitch, int period)
379 {
380 int x = splclock();
381
382 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
383 if (!beeping) {
384 /* Something else owns it. */
385 splx(x);
386 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
387 }
388 mtx_lock_spin(&clock_lock);
389 outb(TIMER_CNTR2, pitch);
390 outb(TIMER_CNTR2, (pitch>>8));
391 mtx_unlock_spin(&clock_lock);
392 if (!beeping) {
393 /* enable counter2 output to speaker */
394 outb(IO_PPI, inb(IO_PPI) | 3);
395 beeping = period;
396 timeout(sysbeepstop, (void *)NULL, period);
397 }
398 splx(x);
399 return (0);
400 }
401
402 /*
403 * RTC support routines
404 */
405
406 int
407 rtcin(reg)
408 int reg;
409 {
410 int s;
411 u_char val;
412
413 s = splhigh();
414 outb(IO_RTC, reg);
415 inb(0x84);
416 val = inb(IO_RTC + 1);
417 inb(0x84);
418 splx(s);
419 return (val);
420 }
421
422 static __inline void
423 writertc(u_char reg, u_char val)
424 {
425 int s;
426
427 s = splhigh();
428 inb(0x84);
429 outb(IO_RTC, reg);
430 inb(0x84);
431 outb(IO_RTC + 1, val);
432 inb(0x84); /* XXX work around wrong order in rtcin() */
433 splx(s);
434 }
435
436 static __inline int
437 readrtc(int port)
438 {
439 return(bcd2bin(rtcin(port)));
440 }
441
442 static u_int
443 calibrate_clocks(void)
444 {
445 u_int count, prev_count, tot_count;
446 int sec, start_sec, timeout;
447
448 if (bootverbose)
449 printf("Calibrating clock(s) ... ");
450 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
451 goto fail;
452 timeout = 100000000;
453
454 /* Read the mc146818A seconds counter. */
455 for (;;) {
456 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
457 sec = rtcin(RTC_SEC);
458 break;
459 }
460 if (--timeout == 0)
461 goto fail;
462 }
463
464 /* Wait for the mC146818A seconds counter to change. */
465 start_sec = sec;
466 for (;;) {
467 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
468 sec = rtcin(RTC_SEC);
469 if (sec != start_sec)
470 break;
471 }
472 if (--timeout == 0)
473 goto fail;
474 }
475
476 /* Start keeping track of the i8254 counter. */
477 prev_count = getit();
478 if (prev_count == 0 || prev_count > timer0_max_count)
479 goto fail;
480 tot_count = 0;
481
482 /*
483 * Wait for the mc146818A seconds counter to change. Read the i8254
484 * counter for each iteration since this is convenient and only
485 * costs a few usec of inaccuracy. The timing of the final reads
486 * of the counters almost matches the timing of the initial reads,
487 * so the main cause of inaccuracy is the varying latency from
488 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
489 * rtcin(RTC_SEC) that returns a changed seconds count. The
490 * maximum inaccuracy from this cause is < 10 usec on 486's.
491 */
492 start_sec = sec;
493 for (;;) {
494 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
495 sec = rtcin(RTC_SEC);
496 count = getit();
497 if (count == 0 || count > timer0_max_count)
498 goto fail;
499 if (count > prev_count)
500 tot_count += prev_count - (count - timer0_max_count);
501 else
502 tot_count += prev_count - count;
503 prev_count = count;
504 if (sec != start_sec)
505 break;
506 if (--timeout == 0)
507 goto fail;
508 }
509
510 if (bootverbose) {
511 printf("i8254 clock: %u Hz\n", tot_count);
512 }
513 return (tot_count);
514
515 fail:
516 if (bootverbose)
517 printf("failed, using default i8254 clock of %u Hz\n",
518 timer_freq);
519 return (timer_freq);
520 }
521
522 static void
523 set_timer_freq(u_int freq, int intr_freq)
524 {
525 int new_timer0_max_count;
526
527 mtx_lock_spin(&clock_lock);
528 timer_freq = freq;
529 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq);
530 if (new_timer0_max_count != timer0_max_count) {
531 timer0_max_count = new_timer0_max_count;
532 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
533 outb(TIMER_CNTR0, timer0_max_count & 0xff);
534 outb(TIMER_CNTR0, timer0_max_count >> 8);
535 }
536 mtx_unlock_spin(&clock_lock);
537 }
538
539 /*
540 * Initialize 8254 timer 0 early so that it can be used in DELAY().
541 * XXX initialization of other timers is unintentionally left blank.
542 */
543 void
544 startrtclock()
545 {
546 u_int delta, freq;
547
548 writertc(RTC_STATUSA, rtc_statusa);
549 writertc(RTC_STATUSB, RTCSB_24HR);
550
551 set_timer_freq(timer_freq, hz);
552 freq = calibrate_clocks();
553 #ifdef CLK_CALIBRATION_LOOP
554 if (bootverbose) {
555 printf(
556 "Press a key on the console to abort clock calibration\n");
557 while (cncheckc() == -1)
558 calibrate_clocks();
559 }
560 #endif
561
562 /*
563 * Use the calibrated i8254 frequency if it seems reasonable.
564 * Otherwise use the default, and don't use the calibrated i586
565 * frequency.
566 */
567 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq;
568 if (delta < timer_freq / 100) {
569 #ifndef CLK_USE_I8254_CALIBRATION
570 if (bootverbose)
571 printf(
572 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
573 freq = timer_freq;
574 #endif
575 timer_freq = freq;
576 } else {
577 if (bootverbose)
578 printf(
579 "%d Hz differs from default of %d Hz by more than 1%%\n",
580 freq, timer_freq);
581 }
582
583 set_timer_freq(timer_freq, hz);
584 i8254_timecounter.tc_frequency = timer_freq;
585 tc_init(&i8254_timecounter);
586
587 init_TSC();
588 }
589
590 /*
591 * Initialize the time of day register, based on the time base which is, e.g.
592 * from a filesystem.
593 */
594 void
595 inittodr(time_t base)
596 {
597 unsigned long sec, days;
598 int year, month;
599 int y, m, s;
600 struct timespec ts;
601
602 if (base) {
603 s = splclock();
604 ts.tv_sec = base;
605 ts.tv_nsec = 0;
606 tc_setclock(&ts);
607 splx(s);
608 }
609
610 /* Look if we have a RTC present and the time is valid */
611 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
612 goto wrong_time;
613
614 /* wait for time update to complete */
615 /* If RTCSA_TUP is zero, we have at least 244us before next update */
616 s = splhigh();
617 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
618 splx(s);
619 s = splhigh();
620 }
621
622 days = 0;
623 #ifdef USE_RTC_CENTURY
624 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
625 #else
626 year = readrtc(RTC_YEAR) + 1900;
627 if (year < 1970)
628 year += 100;
629 #endif
630 if (year < 1970) {
631 splx(s);
632 goto wrong_time;
633 }
634 month = readrtc(RTC_MONTH);
635 for (m = 1; m < month; m++)
636 days += daysinmonth[m-1];
637 if ((month > 2) && LEAPYEAR(year))
638 days ++;
639 days += readrtc(RTC_DAY) - 1;
640 for (y = 1970; y < year; y++)
641 days += DAYSPERYEAR + LEAPYEAR(y);
642 sec = ((( days * 24 +
643 readrtc(RTC_HRS)) * 60 +
644 readrtc(RTC_MIN)) * 60 +
645 readrtc(RTC_SEC));
646 /* sec now contains the number of seconds, since Jan 1 1970,
647 in the local time zone */
648
649 sec += tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
650
651 y = time_second - sec;
652 if (y <= -2 || y >= 2) {
653 /* badly off, adjust it */
654 ts.tv_sec = sec;
655 ts.tv_nsec = 0;
656 tc_setclock(&ts);
657 }
658 splx(s);
659 return;
660
661 wrong_time:
662 printf("Invalid time in real time clock.\n");
663 printf("Check and reset the date immediately!\n");
664 }
665
666 /*
667 * Write system time back to RTC
668 */
669 void
670 resettodr()
671 {
672 unsigned long tm;
673 int y, m, s;
674
675 if (disable_rtc_set)
676 return;
677
678 s = splclock();
679 tm = time_second;
680 splx(s);
681
682 /* Disable RTC updates and interrupts. */
683 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
684
685 /* Calculate local time to put in RTC */
686
687 tm -= tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
688
689 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
690 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
691 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
692
693 /* We have now the days since 01-01-1970 in tm */
694 writertc(RTC_WDAY, (tm + 4) % 7 + 1); /* Write back Weekday */
695 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
696 tm >= m;
697 y++, m = DAYSPERYEAR + LEAPYEAR(y))
698 tm -= m;
699
700 /* Now we have the years in y and the day-of-the-year in tm */
701 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
702 #ifdef USE_RTC_CENTURY
703 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
704 #endif
705 for (m = 0; ; m++) {
706 int ml;
707
708 ml = daysinmonth[m];
709 if (m == 1 && LEAPYEAR(y))
710 ml++;
711 if (tm < ml)
712 break;
713 tm -= ml;
714 }
715
716 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
717 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
718
719 /* Reenable RTC updates and interrupts. */
720 writertc(RTC_STATUSB, rtc_statusb);
721 rtcin(RTC_INTR);
722 }
723
724
725 /*
726 * Start both clocks running.
727 */
728 void
729 cpu_initclocks()
730 {
731 int diag;
732
733 if (statclock_disable) {
734 /*
735 * The stat interrupt mask is different without the
736 * statistics clock. Also, don't set the interrupt
737 * flag which would normally cause the RTC to generate
738 * interrupts.
739 */
740 rtc_statusb = RTCSB_24HR;
741 } else {
742 /* Setting stathz to nonzero early helps avoid races. */
743 stathz = RTC_NOPROFRATE;
744 profhz = RTC_PROFRATE;
745 }
746
747 /* Finish initializing 8254 timer 0. */
748 intr_add_handler("clk", 0, (driver_intr_t *)clkintr, NULL,
749 INTR_TYPE_CLK | INTR_FAST, NULL);
750 i8254_intsrc = intr_lookup_source(0);
751 if (i8254_intsrc != NULL)
752 i8254_pending = i8254_intsrc->is_pic->pic_source_pending;
753
754 /* Initialize RTC. */
755 writertc(RTC_STATUSA, rtc_statusa);
756 writertc(RTC_STATUSB, RTCSB_24HR);
757
758 /* Don't bother enabling the statistics clock. */
759 if (!statclock_disable) {
760 diag = rtcin(RTC_DIAG);
761 if (diag != 0)
762 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
763
764 intr_add_handler("rtc", 8, (driver_intr_t *)rtcintr, NULL,
765 INTR_TYPE_CLK | INTR_FAST, NULL);
766
767 writertc(RTC_STATUSB, rtc_statusb);
768 rtcin(RTC_INTR);
769 }
770
771 init_TSC_tc();
772 }
773
774 void
775 cpu_startprofclock(void)
776 {
777
778 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
779 writertc(RTC_STATUSA, rtc_statusa);
780 psdiv = pscnt = psratio;
781 }
782
783 void
784 cpu_stopprofclock(void)
785 {
786
787 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
788 writertc(RTC_STATUSA, rtc_statusa);
789 psdiv = pscnt = 1;
790 }
791
792 static int
793 sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS)
794 {
795 int error;
796 u_int freq;
797
798 /*
799 * Use `i8254' instead of `timer' in external names because `timer'
800 * is is too generic. Should use it everywhere.
801 */
802 freq = timer_freq;
803 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
804 if (error == 0 && req->newptr != NULL) {
805 set_timer_freq(freq, hz);
806 i8254_timecounter.tc_frequency = freq;
807 }
808 return (error);
809 }
810
811 SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
812 0, sizeof(u_int), sysctl_machdep_i8254_freq, "IU", "");
813
814 static unsigned
815 i8254_get_timecount(struct timecounter *tc)
816 {
817 u_int count;
818 u_int high, low;
819 u_long rflags;
820
821 rflags = read_rflags();
822 mtx_lock_spin(&clock_lock);
823
824 /* Select timer0 and latch counter value. */
825 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
826
827 low = inb(TIMER_CNTR0);
828 high = inb(TIMER_CNTR0);
829 count = timer0_max_count - ((high << 8) | low);
830 if (count < i8254_lastcount ||
831 (!i8254_ticked && (clkintr_pending ||
832 ((count < 20 || (!(rflags & PSL_I) && count < timer0_max_count / 2u)) &&
833 i8254_intsrc != NULL && i8254_pending(i8254_intsrc))))) {
834 i8254_ticked = 1;
835 i8254_offset += timer0_max_count;
836 }
837 i8254_lastcount = count;
838 count += i8254_offset;
839 mtx_unlock_spin(&clock_lock);
840 return (count);
841 }
842
843 #ifdef DEV_ISA
844 /*
845 * Attach to the ISA PnP descriptors for the timer and realtime clock.
846 */
847 static struct isa_pnp_id attimer_ids[] = {
848 { 0x0001d041 /* PNP0100 */, "AT timer" },
849 { 0x000bd041 /* PNP0B00 */, "AT realtime clock" },
850 { 0 }
851 };
852
853 static int
854 attimer_probe(device_t dev)
855 {
856 int result;
857
858 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids)) <= 0)
859 device_quiet(dev);
860 return(result);
861 }
862
863 static int
864 attimer_attach(device_t dev)
865 {
866 return(0);
867 }
868
869 static device_method_t attimer_methods[] = {
870 /* Device interface */
871 DEVMETHOD(device_probe, attimer_probe),
872 DEVMETHOD(device_attach, attimer_attach),
873 DEVMETHOD(device_detach, bus_generic_detach),
874 DEVMETHOD(device_shutdown, bus_generic_shutdown),
875 DEVMETHOD(device_suspend, bus_generic_suspend), /* XXX stop statclock? */
876 DEVMETHOD(device_resume, bus_generic_resume), /* XXX restart statclock? */
877 { 0, 0 }
878 };
879
880 static driver_t attimer_driver = {
881 "attimer",
882 attimer_methods,
883 1, /* no softc */
884 };
885
886 static devclass_t attimer_devclass;
887
888 DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0);
889 DRIVER_MODULE(attimer, acpi, attimer_driver, attimer_devclass, 0, 0);
890 #endif /* DEV_ISA */
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