pci_cfgreg.c

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    1 /*-
    2  * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
    3  * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
    4  * Copyright (c) 2000, BSDi
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice unmodified, this list of conditions, and the following
   12  *    disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   27  */
   28 
   29 #include <sys/cdefs.h>
   30 __FBSDID("$FreeBSD$");
   31 
   32 #include <sys/param.h>
   33 #include <sys/systm.h>
   34 #include <sys/bus.h>
   35 #include <sys/lock.h>
   36 #include <sys/kernel.h>
   37 #include <sys/mutex.h>
   38 #include <sys/sysctl.h>
   39 #include <dev/pci/pcivar.h>
   40 #include <dev/pci/pcireg.h>
   41 #include <vm/vm.h>
   42 #include <vm/pmap.h>
   43 #include <machine/pci_cfgreg.h>
   44 
   45 enum {
   46         CFGMECH_NONE = 0,
   47         CFGMECH_1,
   48         CFGMECH_PCIE,
   49 };
   50 
   51 static uint32_t pci_docfgregread(int bus, int slot, int func, int reg,
   52                     int bytes);
   53 static int      pciereg_cfgread(int bus, unsigned slot, unsigned func,
   54                     unsigned reg, unsigned bytes);
   55 static void     pciereg_cfgwrite(int bus, unsigned slot, unsigned func,
   56                     unsigned reg, int data, unsigned bytes);
   57 static int      pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
   58 static void     pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
   59 
   60 SYSCTL_DECL(_hw_pci);
   61 
   62 static int cfgmech;
   63 static vm_offset_t pcie_base;
   64 static int pcie_minbus, pcie_maxbus;
   65 static uint32_t pcie_badslots;
   66 static struct mtx pcicfg_mtx;
   67 MTX_SYSINIT(pcicfg_mtx, &pcicfg_mtx, "pcicfg_mtx", MTX_SPIN);
   68 static int mcfg_enable = 1;
   69 TUNABLE_INT("hw.pci.mcfg", &mcfg_enable);
   70 SYSCTL_INT(_hw_pci, OID_AUTO, mcfg, CTLFLAG_RDTUN, &mcfg_enable, 0,
   71     "Enable support for PCI-e memory mapped config access");
   72 
   73 /* 
   74  * Initialise access to PCI configuration space 
   75  */
   76 int
   77 pci_cfgregopen(void)
   78 {
   79         uint64_t pciebar;
   80         uint16_t did, vid;
   81 
   82         if (cfgmech != CFGMECH_NONE)
   83                 return (1);
   84         cfgmech = CFGMECH_1;
   85 
   86         /*
   87          * Grope around in the PCI config space to see if this is a
   88          * chipset that is capable of doing memory-mapped config cycles.
   89          * This also implies that it can do PCIe extended config cycles.
   90          */
   91 
   92         /* Check for supported chipsets */
   93         vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2);
   94         did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2);
   95         switch (vid) {
   96         case 0x8086:
   97                 switch (did) {
   98                 case 0x3590:
   99                 case 0x3592:
  100                         /* Intel 7520 or 7320 */
  101                         pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
  102                         pcie_cfgregopen(pciebar, 0, 255);
  103                         break;
  104                 case 0x2580:
  105                 case 0x2584:
  106                 case 0x2590:
  107                         /* Intel 915, 925, or 915GM */
  108                         pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
  109                         pcie_cfgregopen(pciebar, 0, 255);
  110                         break;
  111                 }
  112         }
  113 
  114         return (1);
  115 }
  116 
  117 static uint32_t
  118 pci_docfgregread(int bus, int slot, int func, int reg, int bytes)
  119 {
  120 
  121         if (cfgmech == CFGMECH_PCIE &&
  122             (bus >= pcie_minbus && bus <= pcie_maxbus) &&
  123             (bus != 0 || !(1 << slot & pcie_badslots)))
  124                 return (pciereg_cfgread(bus, slot, func, reg, bytes));
  125         else
  126                 return (pcireg_cfgread(bus, slot, func, reg, bytes));
  127 }
  128 
  129 /* 
  130  * Read configuration space register
  131  */
  132 u_int32_t
  133 pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
  134 {
  135         uint32_t line;
  136 
  137         if (cfgmech == CFGMECH_NONE)
  138                 return (0xffffffff);
  139 
  140         /*
  141          * Some BIOS writers seem to want to ignore the spec and put
  142          * 0 in the intline rather than 255 to indicate none.  Some use
  143          * numbers in the range 128-254 to indicate something strange and
  144          * apparently undocumented anywhere.  Assume these are completely bogus
  145          * and map them to 255, which the rest of the PCI code recognizes as
  146          * as an invalid IRQ.
  147          */
  148         if (reg == PCIR_INTLINE && bytes == 1) {
  149                 line = pci_docfgregread(bus, slot, func, PCIR_INTLINE, 1);
  150                 if (line == 0 || line >= 128)
  151                         line = PCI_INVALID_IRQ;
  152                 return (line);
  153         }
  154         return (pci_docfgregread(bus, slot, func, reg, bytes));
  155 }
  156 
  157 /* 
  158  * Write configuration space register 
  159  */
  160 void
  161 pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
  162 {
  163 
  164         if (cfgmech == CFGMECH_NONE)
  165                 return;
  166 
  167         if (cfgmech == CFGMECH_PCIE &&
  168             (bus >= pcie_minbus && bus <= pcie_maxbus) &&
  169             (bus != 0 || !(1 << slot & pcie_badslots)))
  170                 pciereg_cfgwrite(bus, slot, func, reg, data, bytes);
  171         else
  172                 pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
  173 }
  174 
  175 /* 
  176  * Configuration space access using direct register operations
  177  */
  178 
  179 /* enable configuration space accesses and return data port address */
  180 static int
  181 pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
  182 {
  183         int dataport = 0;
  184 
  185         if (bus <= PCI_BUSMAX && slot <= PCI_SLOTMAX && func <= PCI_FUNCMAX &&
  186             (unsigned)reg <= PCI_REGMAX && bytes != 3 &&
  187             (unsigned)bytes <= 4 && (reg & (bytes - 1)) == 0) {
  188                 outl(CONF1_ADDR_PORT, (1U << 31) | (bus << 16) | (slot << 11) 
  189                     | (func << 8) | (reg & ~0x03));
  190                 dataport = CONF1_DATA_PORT + (reg & 0x03);
  191         }
  192         return (dataport);
  193 }
  194 
  195 /* disable configuration space accesses */
  196 static void
  197 pci_cfgdisable(void)
  198 {
  199 
  200         /*
  201          * Do nothing.  Writing a 0 to the address port can apparently
  202          * confuse some bridges and cause spurious access failures.
  203          */
  204 }
  205 
  206 static int
  207 pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
  208 {
  209         int data = -1;
  210         int port;
  211 
  212         mtx_lock_spin(&pcicfg_mtx);
  213         port = pci_cfgenable(bus, slot, func, reg, bytes);
  214         if (port != 0) {
  215                 switch (bytes) {
  216                 case 1:
  217                         data = inb(port);
  218                         break;
  219                 case 2:
  220                         data = inw(port);
  221                         break;
  222                 case 4:
  223                         data = inl(port);
  224                         break;
  225                 }
  226                 pci_cfgdisable();
  227         }
  228         mtx_unlock_spin(&pcicfg_mtx);
  229         return (data);
  230 }
  231 
  232 static void
  233 pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
  234 {
  235         int port;
  236 
  237         mtx_lock_spin(&pcicfg_mtx);
  238         port = pci_cfgenable(bus, slot, func, reg, bytes);
  239         if (port != 0) {
  240                 switch (bytes) {
  241                 case 1:
  242                         outb(port, data);
  243                         break;
  244                 case 2:
  245                         outw(port, data);
  246                         break;
  247                 case 4:
  248                         outl(port, data);
  249                         break;
  250                 }
  251                 pci_cfgdisable();
  252         }
  253         mtx_unlock_spin(&pcicfg_mtx);
  254 }
  255 
  256 int
  257 pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
  258 {
  259         uint32_t val1, val2;
  260         int slot;
  261 
  262         if (!mcfg_enable)
  263                 return (0);
  264 
  265         if (minbus != 0)
  266                 return (0);
  267 
  268         if (bootverbose)
  269                 printf("PCIe: Memory Mapped configuration base @ 0x%lx\n",
  270                     base);
  271 
  272         /* XXX: We should make sure this really fits into the direct map. */
  273         pcie_base = (vm_offset_t)pmap_mapdev(base, (maxbus + 1) << 20);
  274         pcie_minbus = minbus;
  275         pcie_maxbus = maxbus;
  276         cfgmech = CFGMECH_PCIE;
  277 
  278         /*
  279          * On some AMD systems, some of the devices on bus 0 are
  280          * inaccessible using memory-mapped PCI config access.  Walk
  281          * bus 0 looking for such devices.  For these devices, we will
  282          * fall back to using type 1 config access instead.
  283          */
  284         if (pci_cfgregopen() != 0) {
  285                 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
  286                         val1 = pcireg_cfgread(0, slot, 0, 0, 4);
  287                         if (val1 == 0xffffffff)
  288                                 continue;
  289 
  290                         val2 = pciereg_cfgread(0, slot, 0, 0, 4);
  291                         if (val2 != val1)
  292                                 pcie_badslots |= (1 << slot);
  293                 }
  294         }
  295 
  296         return (1);
  297 }
  298 
  299 #define PCIE_VADDR(base, reg, bus, slot, func)  \
  300         ((base)                         +       \
  301         ((((bus) & 0xff) << 20)         |       \
  302         (((slot) & 0x1f) << 15)         |       \
  303         (((func) & 0x7) << 12)          |       \
  304         ((reg) & 0xfff)))
  305 
  306 /*
  307  * AMD BIOS And Kernel Developer's Guides for CPU families starting with 10h
  308  * have a requirement that all accesses to the memory mapped PCI configuration
  309  * space are done using AX class of registers.
  310  * Since other vendors do not currently have any contradicting requirements
  311  * the AMD access pattern is applied universally.
  312  */
  313 
  314 static int
  315 pciereg_cfgread(int bus, unsigned slot, unsigned func, unsigned reg,
  316     unsigned bytes)
  317 {
  318         vm_offset_t va;
  319         int data = -1;
  320 
  321         if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
  322             func > PCI_FUNCMAX || reg > PCIE_REGMAX)
  323                 return (-1);
  324 
  325         va = PCIE_VADDR(pcie_base, reg, bus, slot, func);
  326 
  327         switch (bytes) {
  328         case 4:
  329                 __asm("movl %1, %0" : "=a" (data)
  330                     : "m" (*(volatile uint32_t *)va));
  331                 break;
  332         case 2:
  333                 __asm("movzwl %1, %0" : "=a" (data)
  334                     : "m" (*(volatile uint16_t *)va));
  335                 break;
  336         case 1:
  337                 __asm("movzbl %1, %0" : "=a" (data)
  338                     : "m" (*(volatile uint8_t *)va));
  339                 break;
  340         }
  341 
  342         return (data);
  343 }
  344 
  345 static void
  346 pciereg_cfgwrite(int bus, unsigned slot, unsigned func, unsigned reg, int data,
  347     unsigned bytes)
  348 {
  349         vm_offset_t va;
  350 
  351         if (bus < pcie_minbus || bus > pcie_maxbus || slot > PCI_SLOTMAX ||
  352             func > PCI_FUNCMAX || reg > PCIE_REGMAX)
  353                 return;
  354 
  355         va = PCIE_VADDR(pcie_base, reg, bus, slot, func);
  356 
  357         switch (bytes) {
  358         case 4:
  359                 __asm("movl %1, %0" : "=m" (*(volatile uint32_t *)va)
  360                     : "a" (data));
  361                 break;
  362         case 2:
  363                 __asm("movw %1, %0" : "=m" (*(volatile uint16_t *)va)
  364                     : "a" ((uint16_t)data));
  365                 break;
  366         case 1:
  367                 __asm("movb %1, %0" : "=m" (*(volatile uint8_t *)va)
  368                     : "a" ((uint8_t)data));
  369                 break;
  370         }
  371 }
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FreeBSD/Linux Kernel Cross Reference sys/amd64/pci/pci_cfgreg.c

FreeBSD/Linux Kernel Cross Reference
sys/amd64/pci/pci_cfgreg.c
