FreeBSD/Linux Kernel Cross Reference
sys/amd64/pci/pci_cfgreg.c

     /*-
      * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
      * Copyright (c) 2000, Michael Smith <msmith@freebsd.org>
      * Copyright (c) 2000, BSDi
      * All rights reserved.
      *
      * Redistribution and use in source and binary forms, with or without
      * modification, are permitted provided that the following conditions
      * are met:
     * 1. Redistributions of source code must retain the above copyright
     *    notice unmodified, this list of conditions, and the following
     *    disclaimer.
     * 2. Redistributions in binary form must reproduce the above copyright
     *    notice, this list of conditions and the following disclaimer in the
     *    documentation and/or other materials provided with the distribution.
     *
     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     */
    
    #include <sys/cdefs.h>
    __FBSDID("$FreeBSD$");
    
    #include <sys/param.h>
    #include <sys/systm.h>
    #include <sys/bus.h>
    #include <sys/lock.h>
    #include <sys/mutex.h>
    #include <dev/pci/pcivar.h>
    #include <dev/pci/pcireg.h>
    #include <machine/pci_cfgreg.h>
    
    static int      pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
    static void     pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
    
    static struct mtx pcicfg_mtx;
    
    /* 
     * Initialise access to PCI configuration space 
     */
    int
    pci_cfgregopen(void)
    {
            static int              opened = 0;
    
            if (opened)
                    return (1);
            mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
            opened = 1;
            return (1);
    }
    
    /* 
     * Read configuration space register
     */
    u_int32_t
    pci_cfgregread(int bus, int slot, int func, int reg, int bytes)
    {
            uint32_t line;
    
            /*
             * Some BIOS writers seem to want to ignore the spec and put
             * 0 in the intline rather than 255 to indicate none.  Some use
             * numbers in the range 128-254 to indicate something strange and
             * apparently undocumented anywhere.  Assume these are completely bogus
             * and map them to 255, which the rest of the PCI code recognizes as
             * as an invalid IRQ.
             */
            if (reg == PCIR_INTLINE && bytes == 1) {
                    line = pcireg_cfgread(bus, slot, func, PCIR_INTLINE, 1);
                    if (line == 0 || line >= 128)
                            line = PCI_INVALID_IRQ;
                    return (line);
            }
            return (pcireg_cfgread(bus, slot, func, reg, bytes));
    }
    
    /* 
     * Write configuration space register 
     */
    void
    pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
    {
    
            pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
    }
    
    /* 
     * Configuration space access using direct register operations
     */
    
   /* enable configuration space accesses and return data port address */
   static int
   pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
   {
           int dataport = 0;
   
           if (bus <= PCI_BUSMAX && slot < 32 && func <= PCI_FUNCMAX &&
               reg <= PCI_REGMAX && bytes != 3 && (unsigned) bytes <= 4 &&
               (reg & (bytes - 1)) == 0) {
                   outl(CONF1_ADDR_PORT, (1 << 31) | (bus << 16) | (slot << 11) 
                       | (func << 8) | (reg & ~0x03));
                   dataport = CONF1_DATA_PORT + (reg & 0x03);
           }
           return (dataport);
   }
   
   /* disable configuration space accesses */
   static void
   pci_cfgdisable(void)
   {
   
           /*
            * Do nothing.  Writing a 0 to the address port can apparently
            * confuse some bridges and cause spurious access failures.
            */
   }
   
   static int
   pcireg_cfgread(int bus, int slot, int func, int reg, int bytes)
   {
           int data = -1;
           int port;
   
           mtx_lock_spin(&pcicfg_mtx);
           port = pci_cfgenable(bus, slot, func, reg, bytes);
           if (port != 0) {
                   switch (bytes) {
                   case 1:
                           data = inb(port);
                           break;
                   case 2:
                           data = inw(port);
                           break;
                   case 4:
                           data = inl(port);
                           break;
                   }
                   pci_cfgdisable();
           }
           mtx_unlock_spin(&pcicfg_mtx);
           return (data);
   }
   
   static void
   pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
   {
           int port;
   
           mtx_lock_spin(&pcicfg_mtx);
           port = pci_cfgenable(bus, slot, func, reg, bytes);
           if (port != 0) {
                   switch (bytes) {
                   case 1:
                           outb(port, data);
                           break;
                   case 2:
                           outw(port, data);
                           break;
                   case 4:
                           outl(port, data);
                           break;
                   }
                   pci_cfgdisable();
           }
           mtx_unlock_spin(&pcicfg_mtx);
   }

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