The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arch/amiga/dev/atzscreg.h

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    1 /*      $NetBSD: atzscreg.h,v 1.5 2005/12/11 12:16:28 christos Exp $    */
    2 
    3 /*
    4  * Copyright (c) 1982, 1990 The Regents of the University of California.
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. Neither the name of the University nor the names of its contributors
   16  *    may be used to endorse or promote products derived from this software
   17  *    without specific prior written permission.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  *
   31  *      @(#)dmareg.h
   32  */
   33 /*
   34  * Copyright (c) 1994 Christian E. Hopps
   35  *
   36  * Redistribution and use in source and binary forms, with or without
   37  * modification, are permitted provided that the following conditions
   38  * are met:
   39  * 1. Redistributions of source code must retain the above copyright
   40  *    notice, this list of conditions and the following disclaimer.
   41  * 2. Redistributions in binary form must reproduce the above copyright
   42  *    notice, this list of conditions and the following disclaimer in the
   43  *    documentation and/or other materials provided with the distribution.
   44  * 3. All advertising materials mentioning features or use of this software
   45  *    must display the following acknowledgement:
   46  *      This product includes software developed by the University of
   47  *      California, Berkeley and its contributors.
   48  * 4. Neither the name of the University nor the names of its contributors
   49  *    may be used to endorse or promote products derived from this software
   50  *    without specific prior written permission.
   51  *
   52  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   53  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   54  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   55  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   56  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   57  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   58  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   59  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   60  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   61  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   62  * SUCH DAMAGE.
   63  *
   64  *      @(#)dmareg.h
   65  */
   66 #ifndef _AMIGA_DEV_ATZSCREG_H_
   67 #define _AMIGA_DEV_ATZSCREG_H_
   68 
   69 /*
   70  * Hardware layout of the A2091 SDMAC. This also contains the
   71  * registers for the sbic chip, but in favor of separating DMA and
   72  * scsi, the scsi-driver doesn't make use of this dependency
   73  */
   74 
   75 #define v_char          volatile char
   76 #define v_int           volatile int
   77 #define vu_char         volatile u_char
   78 #define vu_short        volatile u_short
   79 #define vu_int          volatile u_int
   80 
   81 /* This chip definition only defines the registers also present on the
   82    A3000 SDMAC. */
   83 
   84 struct sdmac {
   85         short           pad0[0x20];
   86         vu_short ISTR;          /* Interrupt Status Register RO */
   87         vu_short CNTR;          /* Control Register RW */
   88         short           pad1[0x1e];
   89         vu_int   WTC;           /* Word Transfer Count Register RW */
   90         vu_int   ACR;           /* Address Count Register RW */
   91         short           pad2[0x03];
   92         vu_short DAWR;          /* DACK Width Register WO */
   93         char            pad3;
   94         vu_char  SASR;          /* sbic asr */
   95         char            pad4;
   96         vu_char  SCMD;          /* sbic data */
   97         short           pad5[0x26];
   98         vu_short ST_DMA;        /* Start DMA Transfers RW-Strobe */
   99         vu_short SP_DMA;        /* Stop DMA Transfers RW-Strobe */
  100         vu_short CINT;          /* Clear Interrupts RW-Strobe */
  101         short           pad6;
  102         vu_short FLUSH;         /* Flush FIFO RW-Strobe */
  103 };
  104 
  105 /*
  106  * value to go into DAWR
  107  */
  108 #define DAWR_ATZSC      3       /* according to A3000T service-manual */
  109 
  110 /*
  111  * bits defined for CNTR
  112  */
  113 #define CNTR_TCEN       (1<<7)  /* Terminal Count Enable */
  114 #define CNTR_PREST      (1<<6)  /* Perp Reset (not implemented :-((( ) */
  115 #define CNTR_PDMD       (1<<5)  /* Perp Device Mode Select (1=SCSI,0=XT/AT) */
  116 #define CNTR_INTEN      (1<<4)  /* Interrupt Enable */
  117 #define CNTR_DDIR       (1<<3)  /* Device Direction. 1==rd host, wr to perp */
  118 
  119 /*
  120  * bits defined for ISTR
  121  */
  122 #define ISTR_INTX       (1<<8)  /* XT/AT Interrupt pending */
  123 #define ISTR_INT_F      (1<<7)  /* Interrupt Follow */
  124 #define ISTR_INTS       (1<<6)  /* SCSI Peripheral Interrupt */
  125 #define ISTR_E_INT      (1<<5)  /* End-Of-Process Interrupt */
  126 #define ISTR_INT_P      (1<<4)  /* Interrupt Pending */
  127 #define ISTR_UE_INT     (1<<3)  /* Under-Run FIFO Error Interrupt */
  128 #define ISTR_OE_INT     (1<<2)  /* Over-Run FIFO Error Interrupt */
  129 #define ISTR_FF_FLG     (1<<1)  /* FIFO-Full Flag */
  130 #define ISTR_FE_FLG     (1<<0)  /* FIFO-Empty Flag */
  131 
  132 #endif /* _AMIGA_DEV_ATZSCREG_H_ */

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