The Design and Implementation of the FreeBSD Operating System, Second Edition
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sys/arch/mips/include/cpuregs.h

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    1 /*      $NetBSD: cpuregs.h,v 1.83 2011/04/06 05:42:45 matt Exp $        */
    2 
    3 /*
    4  * Copyright (c) 1992, 1993
    5  *      The Regents of the University of California.  All rights reserved.
    6  *
    7  * This code is derived from software contributed to Berkeley by
    8  * Ralph Campbell and Rick Macklem.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. Neither the name of the University nor the names of its contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   32  * SUCH DAMAGE.
   33  *
   34  *      @(#)machConst.h 8.1 (Berkeley) 6/10/93
   35  *
   36  * machConst.h --
   37  *
   38  *      Machine dependent constants.
   39  *
   40  *      Copyright (C) 1989 Digital Equipment Corporation.
   41  *      Permission to use, copy, modify, and distribute this software and
   42  *      its documentation for any purpose and without fee is hereby granted,
   43  *      provided that the above copyright notice appears in all copies.
   44  *      Digital Equipment Corporation makes no representations about the
   45  *      suitability of this software for any purpose.  It is provided "as is"
   46  *      without express or implied warranty.
   47  *
   48  * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
   49  *      v 9.2 89/10/21 15:55:22 jhh Exp  SPRITE (DECWRL)
   50  * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
   51  *      v 1.2 89/08/15 18:28:21 rab Exp  SPRITE (DECWRL)
   52  * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
   53  *      v 9.1 89/09/18 17:33:00 shirriff Exp  SPRITE (DECWRL)
   54  */
   55 
   56 #ifndef _MIPS_CPUREGS_H_
   57 #define _MIPS_CPUREGS_H_
   58 
   59 #include <sys/cdefs.h>          /* For __CONCAT() */
   60 
   61 #if defined(_KERNEL_OPT)
   62 #include "opt_cputype.h"
   63 #endif
   64 
   65 /*
   66  * Address space.
   67  * 32-bit mips CPUS partition their 32-bit address space into four segments:
   68  *
   69  * kuseg   0x00000000 - 0x7fffffff  User virtual mem,  mapped
   70  * kseg0   0x80000000 - 0x9fffffff  Physical memory, cached, unmapped
   71  * kseg1   0xa0000000 - 0xbfffffff  Physical memory, uncached, unmapped
   72  * kseg2   0xc0000000 - 0xffffffff  kernel-virtual,  mapped
   73  *
   74  * mips1 physical memory is limited to 512Mbytes, which is
   75  * doubly mapped in kseg0 (cached) and kseg1 (uncached.)
   76  * Caching of mapped addresses is controlled by bits in the TLB entry.
   77  */
   78 
   79 #ifdef _LP64
   80 #define MIPS_XUSEG_START                (0L << 62)
   81 #define MIPS_XUSEG_P(x)                 (((uint64_t)(x) >> 62) == 0)
   82 #define MIPS_USEG_P(x)                  ((uintptr_t)(x) < 0x80000000L)
   83 #define MIPS_XSSEG_START                (1L << 62)
   84 #define MIPS_XSSEG_P(x)                 (((uint64_t)(x) >> 62) == 1)
   85 #endif
   86 
   87 /*
   88  * MIPS addresses are signed and we defining as negative so that
   89  * in LP64 kern they get sign-extended correctly.
   90  */
   91 #ifndef _LOCORE
   92 #define MIPS_KSEG0_START                (-0x7fffffffL-1) /* 0x80000000 */
   93 #define MIPS_KSEG1_START                -0x60000000L    /* 0xa0000000 */
   94 #define MIPS_KSEG2_START                -0x40000000L    /* 0xc0000000 */
   95 #define MIPS_MAX_MEM_ADDR               -0x42000000L    /* 0xbe000000 */
   96 #define MIPS_RESERVED_ADDR              -0x40380000L    /* 0xbfc80000 */
   97 #endif
   98 
   99 #define MIPS_PHYS_MASK                  0x1fffffff
  100 
  101 #define MIPS_KSEG0_TO_PHYS(x)   ((uintptr_t)(x) & MIPS_PHYS_MASK)
  102 #define MIPS_PHYS_TO_KSEG0(x)   ((uintptr_t)(x) | (intptr_t)MIPS_KSEG0_START)
  103 #define MIPS_KSEG1_TO_PHYS(x)   ((uintptr_t)(x) & MIPS_PHYS_MASK)
  104 #define MIPS_PHYS_TO_KSEG1(x)   ((uintptr_t)(x) | (intptr_t)MIPS_KSEG1_START)
  105 
  106 #define MIPS_KSEG0_P(x)         (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG0_START)
  107 #define MIPS_KSEG1_P(x)         (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG1_START)
  108 #define MIPS_KSEG2_P(x)         ((uintptr_t)MIPS_KSEG2_START <= (uintptr_t)(x))
  109 
  110 /* Map virtual address to index in mips3 r4k virtually-indexed cache */
  111 #define MIPS3_VA_TO_CINDEX(x) \
  112                 (((intptr_t)(x) & 0xffffff) | MIPS_KSEG0_START) 
  113 
  114 #ifndef _LOCORE
  115 #define MIPS_XSEG_MASK          (0x3fffffffffffffffLL)
  116 #define MIPS_XKSEG_START        (0x3ULL << 62)
  117 #define MIPS_XKSEG_P(x)         (((uint64_t)(x) >> 62) == 3)
  118 
  119 #define MIPS_XKPHYS_START       (0x2ULL << 62)
  120 #define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \
  121         (MIPS_XKPHYS_START | ((uint64_t)(CCA_UNCACHED) << 59) | (x))
  122 #define MIPS_PHYS_TO_XKPHYS_CACHED(x) \
  123         (mips_options.mips3_xkphys_cached | (x))
  124 #define MIPS_PHYS_TO_XKPHYS(cca,x) \
  125         (MIPS_XKPHYS_START | ((uint64_t)(cca) << 59) | (x))
  126 #define MIPS_XKPHYS_TO_PHYS(x)  ((uint64_t)(x) & 0x07ffffffffffffffLL)
  127 #define MIPS_XKPHYS_TO_CCA(x)   (((uint64_t)(x) >> 59) & 7)
  128 #define MIPS_XKPHYS_P(x)        (((uint64_t)(x) >> 62) == 2)
  129 #endif  /* _LOCORE */
  130 
  131 #define CCA_UNCACHED            2
  132 #define CCA_CACHEABLE           3       /* cacheable non-coherent */
  133 
  134 /* CPU dependent mtc0 hazard hook */
  135 #if (MIPS32R2 + MIPS64R2) > 0
  136 # if (MIPS1 + MIPS3 + MIPS32 + MIPS64) == 0
  137 #  define COP0_SYNC             sll $0,$0,3     /* EHB */
  138 #  define JR_HB_RA              .set push; .set mips32r2; jr.hb ra; nop; .set pop
  139 # else
  140 #  define COP0_SYNC             sll $0,$0,1; sll $0,$0,1; sll $0,$0,3
  141 #  define JR_HB_RA              sll $0,$0,1; sll $0,$0,1; jr ra; sll $0,$0,3
  142 # endif
  143 #elif (MIPS32 + MIPS64) > 0
  144 # define COP0_SYNC              sll $0,$0,1; sll $0,$0,1; sll $0,$0,1
  145 # define JR_HB_RA               sll $0,$0,1; sll $0,$0,1; jr ra; sll $0,$0,1
  146 #elif MIPS3 > 0
  147 # define COP0_SYNC              nop; nop; nop
  148 # define JR_HB_RA               nop; nop; jr ra; nop
  149 #else
  150 # define COP0_SYNC              nop
  151 # define JR_HB_RA               jr ra; nop
  152 #endif
  153 #define COP0_HAZARD_FPUENABLE   nop; nop; nop; nop;
  154 
  155 /*
  156  * The bits in the cause register.
  157  *
  158  * Bits common to r3000 and r4000:
  159  *
  160  *      MIPS_CR_BR_DELAY        Exception happened in branch delay slot.
  161  *      MIPS_CR_COP_ERR         Coprocessor error.
  162  *      MIPS_CR_IP              Interrupt pending bits defined below.
  163  *                              (same meaning as in CAUSE register).
  164  *      MIPS_CR_EXC_CODE        The exception type (see exception codes below).
  165  *
  166  * Differences:
  167  *  r3k has 4 bits of exception type, r4k has 5 bits.
  168  */
  169 #define MIPS_CR_BR_DELAY        0x80000000
  170 #define MIPS_CR_COP_ERR         0x30000000
  171 #define MIPS1_CR_EXC_CODE       0x0000003C      /* four bits */
  172 #define MIPS3_CR_EXC_CODE       0x0000007C      /* five bits */
  173 #define MIPS_CR_IP              0x0000FF00
  174 #define MIPS_CR_EXC_CODE_SHIFT  2
  175 
  176 /*
  177  * The bits in the status register.  All bits are active when set to 1.
  178  *
  179  *      R3000 status register fields:
  180  *      MIPS_SR_COP_USABILITY   Control the usability of the four coprocessors.
  181  *      MIPS_SR_TS              TLB shutdown.
  182  *
  183  *      MIPS_SR_INT_IE          Master (current) interrupt enable bit.
  184  *
  185  * Differences:
  186  *      r3k has cache control is via frobbing SR register bits, whereas the
  187  *      r4k cache control is via explicit instructions.
  188  *      r3k has a 3-entry stack of kernel/user bits, whereas the
  189  *      r4k has kernel/supervisor/user.
  190  */
  191 #define MIPS_SR_COP_USABILITY   0xf0000000
  192 #define MIPS_SR_COP_0_BIT       0x10000000
  193 #define MIPS_SR_COP_1_BIT       0x20000000
  194 #define MIPS_SR_COP_2_BIT       0x40000000
  195 
  196         /* r4k and r3k differences, see below */
  197 
  198 #define MIPS_SR_MX              0x01000000      /* MIPS64 */
  199 #define MIPS_SR_PX              0x00800000      /* MIPS64 */
  200 #define MIPS_SR_BEV             0x00400000      /* Use boot exception vector */
  201 #define MIPS_SR_TS              0x00200000
  202 
  203         /* r4k and r3k differences, see below */
  204 
  205 #define MIPS_SR_INT_IE          0x00000001
  206 /*#define MIPS_SR_MBZ           0x0f8000c0*/    /* Never used, true for r3k */
  207 /*#define MIPS_SR_INT_MASK      0x0000ff00*/
  208 
  209 
  210 /*
  211  * The R2000/R3000-specific status register bit definitions.
  212  * all bits are active when set to 1.
  213  *
  214  *      MIPS_SR_PARITY_ERR      Parity error.
  215  *      MIPS_SR_CACHE_MISS      Most recent D-cache load resulted in a miss.
  216  *      MIPS_SR_PARITY_ZERO     Zero replaces outgoing parity bits.
  217  *      MIPS_SR_SWAP_CACHES     Swap I-cache and D-cache.
  218  *      MIPS_SR_ISOL_CACHES     Isolate D-cache from main memory.
  219  *                              Interrupt enable bits defined below.
  220  *      MIPS_SR_KU_OLD          Old kernel/user mode bit. 1 => user mode.
  221  *      MIPS_SR_INT_ENA_OLD     Old interrupt enable bit.
  222  *      MIPS_SR_KU_PREV         Previous kernel/user mode bit. 1 => user mode.
  223  *      MIPS_SR_INT_ENA_PREV    Previous interrupt enable bit.
  224  *      MIPS_SR_KU_CUR          Current kernel/user mode bit. 1 => user mode.
  225  */
  226 
  227 #define MIPS1_PARITY_ERR        0x00100000
  228 #define MIPS1_CACHE_MISS        0x00080000
  229 #define MIPS1_PARITY_ZERO       0x00040000
  230 #define MIPS1_SWAP_CACHES       0x00020000
  231 #define MIPS1_ISOL_CACHES       0x00010000
  232 
  233 #define MIPS1_SR_KU_OLD         0x00000020      /* 2nd stacked KU/IE*/
  234 #define MIPS1_SR_INT_ENA_OLD    0x00000010      /* 2nd stacked KU/IE*/
  235 #define MIPS1_SR_KU_PREV        0x00000008      /* 1st stacked KU/IE*/
  236 #define MIPS1_SR_INT_ENA_PREV   0x00000004      /* 1st stacked KU/IE*/
  237 #define MIPS1_SR_KU_CUR         0x00000002      /* current KU */
  238 
  239 /* backwards compatibility */
  240 #define MIPS_SR_PARITY_ERR      MIPS1_PARITY_ERR
  241 #define MIPS_SR_CACHE_MISS      MIPS1_CACHE_MISS
  242 #define MIPS_SR_PARITY_ZERO     MIPS1_PARITY_ZERO
  243 #define MIPS_SR_SWAP_CACHES     MIPS1_SWAP_CACHES
  244 #define MIPS_SR_ISOL_CACHES     MIPS1_ISOL_CACHES
  245 
  246 #define MIPS_SR_KU_OLD          MIPS1_SR_KU_OLD
  247 #define MIPS_SR_INT_ENA_OLD     MIPS1_SR_INT_ENA_OLD
  248 #define MIPS_SR_KU_PREV         MIPS1_SR_KU_PREV
  249 #define MIPS_SR_KU_CUR          MIPS1_SR_KU_CUR
  250 #define MIPS_SR_INT_ENA_PREV    MIPS1_SR_INT_ENA_PREV
  251 
  252 /*
  253  * R4000 status register bit definitons,
  254  * where different from r2000/r3000.
  255  */
  256 #define MIPS3_SR_XX             0x80000000
  257 #define MIPS3_SR_RP             0x08000000
  258 #define MIPS3_SR_FR             0x04000000
  259 #define MIPS3_SR_RE             0x02000000
  260 
  261 #define MIPS3_SR_DIAG_DL        0x01000000              /* QED 52xx */
  262 #define MIPS3_SR_DIAG_IL        0x00800000              /* QED 52xx */
  263 #define MIPS3_SR_PX             0x00800000              /* MIPS64 */
  264 #define MIPS3_SR_SR             0x00100000
  265 #define MIPS3_SR_NMI            0x00080000              /* MIPS32/64 */
  266 #define MIPS3_SR_DIAG_CH        0x00040000
  267 #define MIPS3_SR_DIAG_CE        0x00020000
  268 #define MIPS3_SR_DIAG_PE        0x00010000
  269 #define MIPS3_SR_KX             0x00000080
  270 #define MIPS3_SR_SX             0x00000040
  271 #define MIPS3_SR_UX             0x00000020
  272 #define MIPS3_SR_KSU_MASK       0x00000018
  273 #define MIPS3_SR_KSU_USER       0x00000010
  274 #define MIPS3_SR_KSU_SUPER      0x00000008
  275 #define MIPS3_SR_KSU_KERNEL     0x00000000
  276 #define MIPS3_SR_ERL            0x00000004
  277 #define MIPS3_SR_EXL            0x00000002
  278 
  279 #define MIPS_SR_SOFT_RESET      MIPS3_SR_SOFT_RESET
  280 #define MIPS_SR_DIAG_CH         MIPS3_SR_DIAG_CH
  281 #define MIPS_SR_DIAG_CE         MIPS3_SR_DIAG_CE
  282 #define MIPS_SR_DIAG_PE         MIPS3_SR_DIAG_PE
  283 #define MIPS_SR_KX              MIPS3_SR_KX
  284 #define MIPS_SR_SX              MIPS3_SR_SX
  285 #define MIPS_SR_UX              MIPS3_SR_UX
  286 
  287 #define MIPS_SR_KSU_MASK        MIPS3_SR_KSU_MASK
  288 #define MIPS_SR_KSU_USER        MIPS3_SR_KSU_USER
  289 #define MIPS_SR_KSU_SUPER       MIPS3_SR_KSU_SUPER
  290 #define MIPS_SR_KSU_KERNEL      MIPS3_SR_KSU_KERNEL
  291 #define MIPS_SR_ERL             MIPS3_SR_ERL
  292 #define MIPS_SR_EXL             MIPS3_SR_EXL
  293 
  294 
  295 /*
  296  * The interrupt masks.
  297  * If a bit in the mask is 1 then the interrupt is enabled (or pending).
  298  */
  299 #define MIPS_INT_MASK           0xff00
  300 #define MIPS_INT_MASK_5         0x8000
  301 #define MIPS_INT_MASK_4         0x4000
  302 #define MIPS_INT_MASK_3         0x2000
  303 #define MIPS_INT_MASK_2         0x1000
  304 #define MIPS_INT_MASK_1         0x0800
  305 #define MIPS_INT_MASK_0         0x0400
  306 #define MIPS_HARD_INT_MASK      0xfc00
  307 #define MIPS_SOFT_INT_MASK_1    0x0200
  308 #define MIPS_SOFT_INT_MASK_0    0x0100
  309 #define MIPS_SOFT_INT_MASK      0x0300
  310 #define MIPS_INT_MASK_SHIFT     8
  311 
  312 /*
  313  * mips3 CPUs have on-chip timer at INT_MASK_5.  Each platform can
  314  * choose to enable this interrupt.
  315  */
  316 #if defined(MIPS3_ENABLE_CLOCK_INTR)
  317 #define MIPS3_INT_MASK                  MIPS_INT_MASK
  318 #define MIPS3_HARD_INT_MASK             MIPS_HARD_INT_MASK
  319 #else
  320 #define MIPS3_INT_MASK                  (MIPS_INT_MASK &  ~MIPS_INT_MASK_5)
  321 #define MIPS3_HARD_INT_MASK             (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
  322 #endif
  323 
  324 /*
  325  * The bits in the context register.
  326  */
  327 #define MIPS1_CNTXT_PTE_BASE    0xFFE00000
  328 #define MIPS1_CNTXT_BAD_VPN     0x001FFFFC
  329 
  330 #define MIPS3_CNTXT_PTE_BASE    0xFF800000
  331 #define MIPS3_CNTXT_BAD_VPN2    0x007FFFF0
  332 
  333 /*
  334  * The bits in the MIPS3 config register.
  335  *
  336  *      bit 0..5: R/W, Bit 6..31: R/O
  337  */
  338 
  339 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
  340 #define MIPS3_CONFIG_K0_MASK    0x00000007
  341 
  342 /*
  343  * R/W Update on Store Conditional
  344  *      0: Store Conditional uses coherency algorithm specified by TLB
  345  *      1: Store Conditional uses cacheable coherent update on write
  346  */
  347 #define MIPS3_CONFIG_CU         0x00000008
  348 
  349 #define MIPS3_CONFIG_DB         0x00000010      /* Primary D-cache line size */
  350 #define MIPS3_CONFIG_IB         0x00000020      /* Primary I-cache line size */
  351 #define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \
  352         (((config) & (bit)) ? 32 : 16)
  353 
  354 #define MIPS3_CONFIG_DC_MASK    0x000001c0      /* Primary D-cache size */
  355 #define MIPS3_CONFIG_DC_SHIFT   6
  356 #define MIPS3_CONFIG_IC_MASK    0x00000e00      /* Primary I-cache size */
  357 #define MIPS3_CONFIG_IC_SHIFT   9
  358 #define MIPS3_CONFIG_C_DEFBASE  0x1000          /* default base 2^12 */
  359 
  360 /* Cache size mode indication: available only on Vr41xx CPUs */
  361 #define MIPS3_CONFIG_CS         0x00001000
  362 #define MIPS3_CONFIG_C_4100BASE 0x0400          /* base is 2^10 if CS=1 */
  363 #define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \
  364         ((base) << (((config) & (mask)) >> (shift)))
  365 
  366 /* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */
  367 #define MIPS3_CONFIG_SE         0x00001000
  368 
  369 /* Block ordering: 0: sequential, 1: sub-block */
  370 #define MIPS3_CONFIG_EB         0x00002000
  371 
  372 /* ECC mode - 0: ECC mode, 1: parity mode */
  373 #define MIPS3_CONFIG_EM         0x00004000
  374 
  375 /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
  376 #define MIPS3_CONFIG_BE         0x00008000
  377 
  378 /* Dirty Shared coherency state - 0: enabled, 1: disabled */
  379 #define MIPS3_CONFIG_SM         0x00010000
  380 
  381 /* Secondary Cache - 0: present, 1: not present */
  382 #define MIPS3_CONFIG_SC         0x00020000
  383 
  384 /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */
  385 #define MIPS3_CONFIG_EW_MASK    0x000c0000
  386 #define MIPS3_CONFIG_EW_SHIFT   18
  387 
  388 /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
  389 #define MIPS3_CONFIG_SW         0x00100000
  390 
  391 /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
  392 #define MIPS3_CONFIG_SS         0x00200000
  393 
  394 /* Secondary Cache line size */
  395 #define MIPS3_CONFIG_SB_MASK    0x00c00000
  396 #define MIPS3_CONFIG_SB_SHIFT   22
  397 #define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \
  398         (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT))
  399 
  400 /* Write back data rate */
  401 #define MIPS3_CONFIG_EP_MASK    0x0f000000
  402 #define MIPS3_CONFIG_EP_SHIFT   24
  403 
  404 /* System clock ratio - this value is CPU dependent */
  405 #define MIPS3_CONFIG_EC_MASK    0x70000000
  406 #define MIPS3_CONFIG_EC_SHIFT   28
  407 
  408 /* Master-Checker Mode - 1: enabled */
  409 #define MIPS3_CONFIG_CM         0x80000000
  410 
  411 /*
  412  * The bits in the MIPS4 config register.
  413  */
  414 
  415 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
  416 #define MIPS4_CONFIG_K0_MASK    MIPS3_CONFIG_K0_MASK
  417 #define MIPS4_CONFIG_DN_MASK    0x00000018      /* Device number */
  418 #define MIPS4_CONFIG_CT         0x00000020      /* CohPrcReqTar */
  419 #define MIPS4_CONFIG_PE         0x00000040      /* PreElmReq */
  420 #define MIPS4_CONFIG_PM_MASK    0x00000180      /* PreReqMax */
  421 #define MIPS4_CONFIG_EC_MASK    0x00001e00      /* SysClkDiv */
  422 #define MIPS4_CONFIG_SB         0x00002000      /* SCBlkSize */
  423 #define MIPS4_CONFIG_SK         0x00004000      /* SCColEn */
  424 #define MIPS4_CONFIG_BE         0x00008000      /* MemEnd */
  425 #define MIPS4_CONFIG_SS_MASK    0x00070000      /* SCSize */
  426 #define MIPS4_CONFIG_SC_MASK    0x00380000      /* SCClkDiv */
  427 #define MIPS4_CONFIG_RESERVED   0x03c00000      /* Reserved wired 0 */
  428 #define MIPS4_CONFIG_DC_MASK    0x1c000000      /* Primary D-Cache size */
  429 #define MIPS4_CONFIG_IC_MASK    0xe0000000      /* Primary I-Cache size */
  430 
  431 #define MIPS4_CONFIG_DC_SHIFT   26
  432 #define MIPS4_CONFIG_IC_SHIFT   29
  433 
  434 #define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift)              \
  435         ((base) << (((config) & (mask)) >> (shift)))
  436 
  437 #define MIPS4_CONFIG_CACHE_L2_LSIZE(config)                             \
  438         (((config) & MIPS4_CONFIG_SB) ? 128 : 64)
  439 
  440 /*
  441  * Location of exception vectors.
  442  *
  443  * Common vectors:  reset and UTLB miss.
  444  */
  445 #define MIPS_RESET_EXC_VEC      MIPS_PHYS_TO_KSEG1(0x1FC00000)
  446 #define MIPS_UTLB_MISS_EXC_VEC  MIPS_PHYS_TO_KSEG0(0)
  447 
  448 /*
  449  * MIPS-1 general exception vector (everything else)
  450  */
  451 #define MIPS1_GEN_EXC_VEC       MIPS_PHYS_TO_KSEG0(0x0080)
  452 
  453 /*
  454  * MIPS-III exception vectors
  455  */
  456 #define MIPS3_XTLB_MISS_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080)
  457 #define MIPS3_CACHE_ERR_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0100)
  458 #define MIPS3_GEN_EXC_VEC       MIPS_PHYS_TO_KSEG0(0x0180)
  459 
  460 /*
  461  * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
  462  */
  463 #define MIPS3_INTR_EXC_VEC      MIPS_PHYS_TO_KSEG0(0x0200)
  464 
  465 /*
  466  * Coprocessor 0 registers:
  467  *
  468  *                              v--- width for mips I,III,32,64
  469  *                                   (3=32bit, 6=64bit, i=impl dep)
  470  *  0   MIPS_COP_0_TLB_INDEX    3333 TLB Index.
  471  *  1   MIPS_COP_0_TLB_RANDOM   3333 TLB Random.
  472  *  2   MIPS_COP_0_TLB_LOW      3... r3k TLB entry low.
  473  *  2   MIPS_COP_0_TLB_LO0      .636 r4k TLB entry low.
  474  *  3   MIPS_COP_0_TLB_LO1      .636 r4k TLB entry low, extended.
  475  *  4   MIPS_COP_0_TLB_CONTEXT  3636 TLB Context.
  476  *  4/2 MIPS_COP_0_USERLOCAL    ..36 UserLocal.
  477  *  5   MIPS_COP_0_TLB_PG_MASK  .333 TLB Page Mask register.
  478  *  6   MIPS_COP_0_TLB_WIRED    .333 Wired TLB number.
  479  *  7   MIPS_COP_0_HWRENA       ..33 rdHWR Enable.
  480  *  8   MIPS_COP_0_BAD_VADDR    3636 Bad virtual address.
  481  *  9   MIPS_COP_0_COUNT        .333 Count register.
  482  * 10   MIPS_COP_0_TLB_HI       3636 TLB entry high.
  483  * 11   MIPS_COP_0_COMPARE      .333 Compare (against Count).
  484  * 12   MIPS_COP_0_STATUS       3333 Status register.
  485  * 12/1 MIPS_COP_0_INTCTL       ..33 Interrupt Control.
  486  * 12/2 MIPS_COP_0_SRSCTL       ..33 Shadow Register Set Selectors.
  487  * 12/3 MIPS_COP_0_SRSMAP       ..33 Shadow Set Map.
  488  * 13   MIPS_COP_0_CAUSE        3333 Exception cause register.
  489  * 14   MIPS_COP_0_EXC_PC       3636 Exception PC.
  490  * 15   MIPS_COP_0_PRID         3333 Processor revision identifier.
  491  * 15/1 MIPS_COP_0_EBASE        ..33 Exception Base.
  492  * 16   MIPS_COP_0_CONFIG       3333 Configuration register.
  493  * 16/1 MIPS_COP_0_CONFIG1      ..33 Configuration register 1.
  494  * 16/2 MIPS_COP_0_CONFIG2      ..33 Configuration register 2.
  495  * 16/3 MIPS_COP_0_CONFIG3      ..33 Configuration register 3.
  496  * 16/6 MIPS_COP_0_CONFIG6      ..33 Configuration register 6.
  497  * 16/7 MIPS_COP_0_CONFIG7      ..33 Configuration register 7.
  498  * 17   MIPS_COP_0_LLADDR       .336 Load Linked Address.
  499  * 18   MIPS_COP_0_WATCH_LO     .336 WatchLo register.
  500  * 19   MIPS_COP_0_WATCH_HI     .333 WatchHi register.
  501  * 20   MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register.
  502  * 22   MIPS_COP_0_OSSCRATCH    ...6 [RMI] OS Scratch register. (select 0..7)
  503  * 23   MIPS_COP_0_DEBUG        .... Debug JTAG register.
  504  * 24   MIPS_COP_0_DEPC         .... DEPC JTAG register.
  505  * 25   MIPS_COP_0_PERFCNT      ..36 Performance Counter register.
  506  * 26   MIPS_COP_0_ECC          .3ii ECC / Error Control register.
  507  * 27   MIPS_COP_0_CACHE_ERR    .3ii Cache Error register.
  508  * 28/0 MIPS_COP_0_TAG_LO       .3ii Cache TagLo register (instr).
  509  * 28/1 MIPS_COP_0_DATA_LO      ..ii Cache DataLo register (instr).
  510  * 28/2 MIPS_COP_0_TAG_LO       ..ii Cache TagLo register (data).
  511  * 28/3 MIPS_COP_0_DATA_LO      ..ii Cache DataLo register (data).
  512  * 29/0 MIPS_COP_0_TAG_HI       .3ii Cache TagHi register (instr).
  513  * 29/1 MIPS_COP_0_DATA_HI      ..ii Cache DataHi register (instr).
  514  * 29/2 MIPS_COP_0_TAG_HI       ..ii Cache TagHi register (data).
  515  * 29/3 MIPS_COP_0_DATA_HI      ..ii Cache DataHi register (data).
  516  * 30   MIPS_COP_0_ERROR_PC     .636 Error EPC register.
  517  * 31   MIPS_COP_0_DESAVE       .... DESAVE JTAG register.
  518  */
  519 #ifdef _LOCORE
  520 #define _(n)    __CONCAT($,n)
  521 #else
  522 #define _(n)    n
  523 #endif
  524 #define MIPS_COP_0_TLB_INDEX    _(0)
  525 #define MIPS_COP_0_TLB_RANDOM   _(1)
  526         /* Name and meaning of  TLB bits for $2 differ on r3k and r4k. */
  527 
  528 #define MIPS_COP_0_TLB_CONTEXT  _(4)
  529                                         /* $5 and $6 new with MIPS-III */
  530 #define MIPS_COP_0_BAD_VADDR    _(8)
  531 #define MIPS_COP_0_TLB_HI       _(10)
  532 #define MIPS_COP_0_STATUS       _(12)
  533 #define MIPS_COP_0_CAUSE        _(13)
  534 #define MIPS_COP_0_EXC_PC       _(14)
  535 #define MIPS_COP_0_PRID         _(15)
  536 
  537 
  538 /* MIPS-I */
  539 #define MIPS_COP_0_TLB_LOW      _(2)
  540 
  541 /* MIPS-III */
  542 #define MIPS_COP_0_TLB_LO0      _(2)
  543 #define MIPS_COP_0_TLB_LO1      _(3)
  544 
  545 #define MIPS_COP_0_TLB_PG_MASK  _(5)
  546 #define MIPS_COP_0_TLB_WIRED    _(6)
  547 
  548 #define MIPS_COP_0_COUNT        _(9)
  549 #define MIPS_COP_0_COMPARE      _(11)
  550 
  551 #define MIPS_COP_0_CONFIG       _(16)
  552 #define MIPS_COP_0_LLADDR       _(17)
  553 #define MIPS_COP_0_WATCH_LO     _(18)
  554 #define MIPS_COP_0_WATCH_HI     _(19)
  555 #define MIPS_COP_0_TLB_XCONTEXT _(20)
  556 #define MIPS_COP_0_ECC          _(26)
  557 #define MIPS_COP_0_CACHE_ERR    _(27)
  558 #define MIPS_COP_0_TAG_LO       _(28)
  559 #define MIPS_COP_0_TAG_HI       _(29)
  560 #define MIPS_COP_0_ERROR_PC     _(30)
  561 
  562 /* MIPS32/64 */
  563 #define MIPS_COP_0_HWRENA       _(7)
  564 #define MIPS_COP_0_OSSCRATCH    _(22)
  565 #define MIPS_COP_0_DEBUG        _(23)
  566 #define MIPS_COP_0_DEPC         _(24)
  567 #define MIPS_COP_0_PERFCNT      _(25)
  568 #define MIPS_COP_0_DATA_LO      _(28)
  569 #define MIPS_COP_0_DATA_HI      _(29)
  570 #define MIPS_COP_0_DESAVE       _(31)
  571 
  572 /*
  573  * Values for the code field in a break instruction.
  574  */
  575 #define MIPS_BREAK_INSTR        0x0000000d
  576 #define MIPS_BREAK_VAL_MASK     0x03ff0000
  577 #define MIPS_BREAK_VAL_SHIFT    16
  578 #define MIPS_BREAK_KDB_VAL      512
  579 #define MIPS_BREAK_SSTEP_VAL    513
  580 #define MIPS_BREAK_BRKPT_VAL    514
  581 #define MIPS_BREAK_SOVER_VAL    515
  582 #define MIPS_BREAK_KDB          (MIPS_BREAK_INSTR | \
  583                                 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT))
  584 #define MIPS_BREAK_SSTEP        (MIPS_BREAK_INSTR | \
  585                                 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT))
  586 #define MIPS_BREAK_BRKPT        (MIPS_BREAK_INSTR | \
  587                                 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT))
  588 #define MIPS_BREAK_SOVER        (MIPS_BREAK_INSTR | \
  589                                 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT))
  590 
  591 /*
  592  * Mininum and maximum cache sizes.
  593  */
  594 #define MIPS_MIN_CACHE_SIZE     (16 * 1024)
  595 #define MIPS_MAX_CACHE_SIZE     (256 * 1024)
  596 #define MIPS3_MAX_PCACHE_SIZE   (32 * 1024)     /* max. primary cache size */
  597 
  598 /*
  599  * The floating point version and status registers.
  600  */
  601 #define MIPS_FPU_ID     $0
  602 #define MIPS_FPU_CSR    $31
  603 
  604 /*
  605  * The floating point coprocessor status register bits.
  606  */
  607 #define MIPS_FPU_ROUNDING_BITS          0x00000003
  608 #define MIPS_FPU_ROUND_RN               0x00000000
  609 #define MIPS_FPU_ROUND_RZ               0x00000001
  610 #define MIPS_FPU_ROUND_RP               0x00000002
  611 #define MIPS_FPU_ROUND_RM               0x00000003
  612 #define MIPS_FPU_STICKY_BITS            0x0000007c
  613 #define MIPS_FPU_STICKY_INEXACT         0x00000004
  614 #define MIPS_FPU_STICKY_UNDERFLOW       0x00000008
  615 #define MIPS_FPU_STICKY_OVERFLOW        0x00000010
  616 #define MIPS_FPU_STICKY_DIV0            0x00000020
  617 #define MIPS_FPU_STICKY_INVALID         0x00000040
  618 #define MIPS_FPU_ENABLE_BITS            0x00000f80
  619 #define MIPS_FPU_ENABLE_INEXACT         0x00000080
  620 #define MIPS_FPU_ENABLE_UNDERFLOW       0x00000100
  621 #define MIPS_FPU_ENABLE_OVERFLOW        0x00000200
  622 #define MIPS_FPU_ENABLE_DIV0            0x00000400
  623 #define MIPS_FPU_ENABLE_INVALID         0x00000800
  624 #define MIPS_FPU_EXCEPTION_BITS         0x0003f000
  625 #define MIPS_FPU_EXCEPTION_INEXACT      0x00001000
  626 #define MIPS_FPU_EXCEPTION_UNDERFLOW    0x00002000
  627 #define MIPS_FPU_EXCEPTION_OVERFLOW     0x00004000
  628 #define MIPS_FPU_EXCEPTION_DIV0         0x00008000
  629 #define MIPS_FPU_EXCEPTION_INVALID      0x00010000
  630 #define MIPS_FPU_EXCEPTION_UNIMPL       0x00020000
  631 #define MIPS_FPU_COND_BIT               0x00800000
  632 #define MIPS_FPU_FLUSH_BIT              0x01000000      /* r4k,  MBZ on r3k */
  633 #define MIPS1_FPC_MBZ_BITS              0xff7c0000
  634 #define MIPS3_FPC_MBZ_BITS              0xfe7c0000
  635 
  636 
  637 /*
  638  * Constants to determine if have a floating point instruction.
  639  */
  640 #define MIPS_OPCODE_SHIFT       26
  641 #define MIPS_OPCODE_C1          0x11
  642 
  643 
  644 /*
  645  * The low part of the TLB entry.
  646  */
  647 #define MIPS1_TLB_PFN                   0xfffff000
  648 #define MIPS1_TLB_NON_CACHEABLE_BIT     0x00000800
  649 #define MIPS1_TLB_DIRTY_BIT             0x00000400
  650 #define MIPS1_TLB_VALID_BIT             0x00000200
  651 #define MIPS1_TLB_GLOBAL_BIT            0x00000100
  652 
  653 #define MIPS3_TLB_PFN                   0x3fffffc0
  654 #define MIPS3_TLB_ATTR_MASK             0x00000038
  655 #define MIPS3_TLB_ATTR_SHIFT            3
  656 #define MIPS3_TLB_DIRTY_BIT             0x00000004
  657 #define MIPS3_TLB_VALID_BIT             0x00000002
  658 #define MIPS3_TLB_GLOBAL_BIT            0x00000001
  659 
  660 #define MIPS1_TLB_PHYS_PAGE_SHIFT       12
  661 #define MIPS3_TLB_PHYS_PAGE_SHIFT       6
  662 #define MIPS1_TLB_PF_NUM                MIPS1_TLB_PFN
  663 #define MIPS3_TLB_PF_NUM                MIPS3_TLB_PFN
  664 #define MIPS1_TLB_MOD_BIT               MIPS1_TLB_DIRTY_BIT
  665 #define MIPS3_TLB_MOD_BIT               MIPS3_TLB_DIRTY_BIT
  666 
  667 /*
  668  * MIPS3_TLB_ATTR (CCA) values - coherency algorithm:
  669  * 0: cacheable, noncoherent, write-through, no write allocate
  670  * 1: cacheable, noncoherent, write-through, write allocate
  671  * 2: uncached
  672  * 3: cacheable, noncoherent, write-back (noncoherent)
  673  * 4: cacheable, coherent, write-back, exclusive (exclusive)
  674  * 5: cacheable, coherent, write-back, exclusive on write (sharable)
  675  * 6: cacheable, coherent, write-back, update on write (update)
  676  * 7: uncached, accelerated (gather STORE operations)
  677  */
  678 #define MIPS3_TLB_ATTR_WT               0 /* IDT */
  679 #define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */
  680 #define MIPS3_TLB_ATTR_UNCACHED         2 /* R4000/R4400, IDT */
  681 #define MIPS3_TLB_ATTR_WB_NONCOHERENT   3 /* R4000/R4400, IDT */
  682 #define MIPS3_TLB_ATTR_WB_EXCLUSIVE     4 /* R4000/R4400 */
  683 #define MIPS3_TLB_ATTR_WB_SHARABLE      5 /* R4000/R4400 */
  684 #define MIPS3_TLB_ATTR_WB_UPDATE        6 /* R4000/R4400 */
  685 #define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */
  686 
  687 
  688 /*
  689  * The high part of the TLB entry.
  690  */
  691 #define MIPS1_TLB_VPN                   0xfffff000
  692 #define MIPS1_TLB_PID                   0x00000fc0
  693 #define MIPS1_TLB_PID_SHIFT             6
  694 
  695 #define MIPS3_TLB_VPN2                  0xffffe000
  696 #define MIPS3_TLB_ASID                  0x000000ff
  697 
  698 #define MIPS1_TLB_VIRT_PAGE_NUM         MIPS1_TLB_VPN
  699 #define MIPS3_TLB_VIRT_PAGE_NUM         MIPS3_TLB_VPN2
  700 #define MIPS3_TLB_PID                   MIPS3_TLB_ASID
  701 #define MIPS_TLB_VIRT_PAGE_SHIFT        12
  702 
  703 /*
  704  * r3000: shift count to put the index in the right spot.
  705  */
  706 #define MIPS1_TLB_INDEX_SHIFT           8
  707 
  708 /*
  709  * The first TLB that write random hits.
  710  */
  711 #define MIPS1_TLB_FIRST_RAND_ENTRY      8
  712 #define MIPS3_TLB_WIRED_UPAGES          1
  713 
  714 /*
  715  * The number of process id entries.
  716  */
  717 #define MIPS1_TLB_NUM_PIDS              64
  718 #define MIPS3_TLB_NUM_ASIDS             256
  719 
  720 /*
  721  * Patch codes to hide CPU design differences between MIPS1 and MIPS3.
  722  */
  723 
  724 /* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */
  725 
  726 #if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 0 && MIPS1 != 0
  727 #define MIPS_TLB_PID_SHIFT              MIPS1_TLB_PID_SHIFT
  728 #define MIPS_TLB_PID                    MIPS1_TLB_PID
  729 #define MIPS_TLB_NUM_PIDS               MIPS1_TLB_NUM_PIDS
  730 #endif
  731 
  732 #if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) != 0 && MIPS1 == 0
  733 #define MIPS_TLB_PID_SHIFT              0
  734 #define MIPS_TLB_PID                    MIPS3_TLB_PID
  735 #define MIPS_TLB_NUM_PIDS               MIPS3_TLB_NUM_ASIDS
  736 #endif
  737 
  738 
  739 #if !defined(MIPS_TLB_PID_SHIFT)
  740 #define MIPS_TLB_PID_SHIFT \
  741     ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT)
  742 
  743 #define MIPS_TLB_PID \
  744     ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_PID : MIPS1_TLB_PID)
  745 
  746 #define MIPS_TLB_NUM_PIDS \
  747     ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS)
  748 #endif
  749 
  750 /*
  751  * Bits defined for for the HWREna (CP0 register 7, select 0).
  752  */
  753 #define MIPS_HWRENA_IMPL31              __BIT(31)
  754 #define MIPS_HWRENA_IMPL30              __BIT(30)
  755 #define MIPS_HWRENA_UL                  __BIT(29)       /* Userlocal */
  756 #define MIPS_HWRENA_CCRES               __BIT(3)
  757 #define MIPS_HWRENA_CC                  __BIT(2)
  758 #define MIPS_HWRENA_SYNCI_STEP          __BIT(1)
  759 #define MIPS_HWRENA_CPUNUM              __BIT(0)
  760 
  761 /*
  762  * Hints for the prefetch instruction
  763  */
  764 
  765 /*
  766  * Prefetched data is expected to be read (not modified)
  767  */
  768 #define PREF_LOAD               0       
  769 #define PREF_LOAD_STREAMED      4       /* but not reused extensively; it */
  770                                         /* "streams" through cache.  */
  771 #define PREF_LOAD_RETAINED      6       /* and reused extensively; it should */
  772                                         /* be "retained" in the cache.  */
  773 
  774 /*
  775  * Prefetched data is expected to be stored or modified
  776  */
  777 #define PREF_STORE              1       
  778 #define PREF_STORE_STREAMED     5       /* but not reused extensively; it */
  779                                         /* "streams" through cache.  */
  780 #define PREF_STORE_RETAINED     7       /* and reused extensively; it should */
  781                                         /* be "retained" in the cache.  */
  782 
  783 /*
  784  * data is no longer expected to be used.  For a WB cache, schedule a
  785  * writeback of any dirty data and afterwards free the cache lines.
  786  */
  787 #define PREF_WB_INV             25      
  788 #define PREF_NUDGE              PREF_WB_INV
  789 
  790 /*
  791  * Prepare for writing an entire cache line without the overhead
  792  * involved in filling the line from memory.
  793  */
  794 #define PREF_PREPAREFORSTORE    30      
  795 
  796 /*
  797  * CPU processor revision IDs for company ID == 0 (non mips32/64 chips)
  798  */
  799 #define MIPS_R2000      0x01    /* MIPS R2000                   ISA I   */
  800 #define MIPS_R3000      0x02    /* MIPS R3000                   ISA I   */
  801 #define MIPS_R6000      0x03    /* MIPS R6000                   ISA II  */
  802 #define MIPS_R4000      0x04    /* MIPS R4000/R4400             ISA III */
  803 #define MIPS_R3LSI      0x05    /* LSI Logic R3000 derivative   ISA I   */
  804 #define MIPS_R6000A     0x06    /* MIPS R6000A                  ISA II  */
  805 #define MIPS_R3IDT      0x07    /* IDT R3041 or RC36100         ISA I   */
  806 #define MIPS_R10000     0x09    /* MIPS R10000                  ISA IV  */
  807 #define MIPS_R4200      0x0a    /* NEC VR4200                   ISA III */
  808 #define MIPS_R4300      0x0b    /* NEC VR4300                   ISA III */
  809 #define MIPS_R4100      0x0c    /* NEC VR4100                   ISA III */
  810 #define MIPS_R12000     0x0e    /* MIPS R12000                  ISA IV  */
  811 #define MIPS_R14000     0x0f    /* MIPS R14000                  ISA IV  */
  812 #define MIPS_R8000      0x10    /* MIPS R8000 Blackbird/TFP     ISA IV  */
  813 #define MIPS_RC32300    0x18    /* IDT RC32334,332,355          ISA 32  */
  814 #define MIPS_R4600      0x20    /* QED R4600 Orion              ISA III */
  815 #define MIPS_R4700      0x21    /* QED R4700 Orion              ISA III */
  816 #define MIPS_R3SONY     0x21    /* Sony R3000 based             ISA I   */
  817 #define MIPS_R4650      0x22    /* QED R4650                    ISA III */
  818 #define MIPS_TX3900     0x22    /* Toshiba TX39 family          ISA I   */
  819 #define MIPS_R5000      0x23    /* MIPS R5000                   ISA IV  */
  820 #define MIPS_R3NKK      0x23    /* NKK R3000 based              ISA I   */
  821 #define MIPS_RC32364    0x26    /* IDT RC32364                  ISA 32  */
  822 #define MIPS_RM7000     0x27    /* QED RM7000                   ISA IV  */
  823 #define MIPS_RM5200     0x28    /* QED RM5200s                  ISA IV  */
  824 #define MIPS_TX4900     0x2d    /* Toshiba TX49 family          ISA III */
  825 #define MIPS_R5900      0x2e    /* Toshiba R5900 (EECore)       ISA --- */
  826 #define MIPS_RC64470    0x30    /* IDT RC64474/RC64475          ISA III */
  827 #define MIPS_TX7900     0x38    /* Toshiba TX79                 ISA III+*/
  828 #define MIPS_R5400      0x54    /* NEC VR5400                   ISA IV  */
  829 #define MIPS_R5500      0x55    /* NEC VR5500                   ISA IV  */
  830 #define MIPS_LOONGSON2  0x63    /* ICT Loongson-2               ISA III */
  831 
  832 /*
  833  * CPU revision IDs for some prehistoric processors.
  834  */
  835 
  836 /* For MIPS_R3000 */
  837 #define MIPS_REV_R2000A         0x16    /* R2000A uses R3000 proc revision */
  838 #define MIPS_REV_R3000          0x20
  839 #define MIPS_REV_R3000A         0x30
  840 
  841 /* For MIPS_TX3900 */
  842 #define MIPS_REV_TX3912         0x10
  843 #define MIPS_REV_TX3922         0x30
  844 #define MIPS_REV_TX3927         0x40
  845 
  846 /* For MIPS_R4000 */
  847 #define MIPS_REV_R4000_A        0x00
  848 #define MIPS_REV_R4000_B        0x22
  849 #define MIPS_REV_R4000_C        0x30
  850 #define MIPS_REV_R4400_A        0x40
  851 #define MIPS_REV_R4400_B        0x50
  852 #define MIPS_REV_R4400_C        0x60
  853 
  854 /* For MIPS_TX4900 */
  855 #define MIPS_REV_TX4927         0x22
  856 
  857 /* For MIPS_LOONGSON2 */
  858 #define MIPS_REV_LOONGSON2E     0x02
  859 #define MIPS_REV_LOONGSON2F     0x03
  860 
  861 /*
  862  * CPU processor revision IDs for company ID == 1 (MIPS)
  863  */
  864 #define MIPS_4Kc        0x80    /* MIPS 4Kc                     ISA 32  */
  865 #define MIPS_5Kc        0x81    /* MIPS 5Kc                     ISA 64  */
  866 #define MIPS_20Kc       0x82    /* MIPS 20Kc                    ISA 64  */
  867 #define MIPS_4Kmp       0x83    /* MIPS 4Km/4Kp                 ISA 32  */
  868 #define MIPS_4KEc       0x84    /* MIPS 4KEc                    ISA 32  */
  869 #define MIPS_4KEmp      0x85    /* MIPS 4KEm/4KEp               ISA 32  */
  870 #define MIPS_4KSc       0x86    /* MIPS 4KSc                    ISA 32  */
  871 #define MIPS_M4K        0x87    /* MIPS M4K                     ISA 32  Rel 2 */
  872 #define MIPS_25Kf       0x88    /* MIPS 25Kf                    ISA 64  */
  873 #define MIPS_5KE        0x89    /* MIPS 5KE                     ISA 64  Rel 2 */
  874 #define MIPS_4KEc_R2    0x90    /* MIPS 4KEc_R2                 ISA 32  Rel 2 */
  875 #define MIPS_4KEmp_R2   0x91    /* MIPS 4KEm/4KEp_R2            ISA 32  Rel 2 */
  876 #define MIPS_4KSd       0x92    /* MIPS 4KSd                    ISA 32  Rel 2 */
  877 #define MIPS_24K        0x93    /* MIPS 24Kc/24Kf               ISA 32  Rel 2 */
  878 #define MIPS_34K        0x95    /* MIPS 34K                     ISA 32  R2 MT */
  879 #define MIPS_24KE       0x96    /* MIPS 24KEc                   ISA 32  Rel 2 */
  880 #define MIPS_74K        0x97    /* MIPS 74Kc/74Kf               ISA 32  Rel 2 */
  881 #define MIPS_1004K      0x99    /* MIPS 1004Kc/1004Kf           ISA 32  Rel 2 */
  882 
  883 /*
  884  * Alchemy (company ID 3) use the processor ID field to donote the CPU core
  885  * revision and the company options field do donate the SOC chip type.
  886  */
  887 /* CPU processor revision IDs */
  888 #define MIPS_AU_REV1    0x01    /* Alchemy Au1000 (Rev 1)       ISA 32  */
  889 #define MIPS_AU_REV2    0x02    /* Alchemy Au1000 (Rev 2)       ISA 32  */
  890 /* CPU company options IDs */
  891 #define MIPS_AU1000     0x00
  892 #define MIPS_AU1500     0x01
  893 #define MIPS_AU1100     0x02
  894 #define MIPS_AU1550     0x03
  895 
  896 /*
  897  * CPU processor revision IDs for company ID == 4 (SiByte)
  898  */
  899 #define MIPS_SB1        0x01    /* SiByte SB1                   ISA 64  */
  900 
  901 /*
  902  * CPU processor revision IDs for company ID == 5 (SandCraft)
  903  */
  904 #define MIPS_SR7100     0x04    /* SandCraft SR7100             ISA 64  */
  905 
  906 /*
  907  * CPU revision IDs for company ID == 12 (RMI)
  908  * note: unlisted Rev values may indicate pre-production silicon
  909  */
  910 #define MIPS_XLR_B2     0x04    /* RMI XLR Production Rev B2            */
  911 #define MIPS_XLR_C4     0x91    /* RMI XLR Production Rev C4            */
  912 
  913 /*
  914  * CPU processor IDs for company ID == 12 (RMI)
  915  */
  916 #define MIPS_XLR308B    0x06    /* RMI XLR308-B                 ISA 64  */
  917 #define MIPS_XLR508B    0x07    /* RMI XLR508-B                 ISA 64  */
  918 #define MIPS_XLR516B    0x08    /* RMI XLR516-B                 ISA 64  */
  919 #define MIPS_XLR532B    0x09    /* RMI XLR532-B                 ISA 64  */
  920 #define MIPS_XLR716B    0x0a    /* RMI XLR716-B                 ISA 64  */
  921 #define MIPS_XLR732B    0x0b    /* RMI XLR732-B                 ISA 64  */
  922 #define MIPS_XLR732C    0x00    /* RMI XLR732-C                 ISA 64  */
  923 #define MIPS_XLR716C    0x02    /* RMI XLR716-C                 ISA 64  */
  924 #define MIPS_XLR532C    0x08    /* RMI XLR532-C                 ISA 64  */
  925 #define MIPS_XLR516C    0x0a    /* RMI XLR516-C                 ISA 64  */
  926 #define MIPS_XLR508C    0x0b    /* RMI XLR508-C                 ISA 64  */
  927 #define MIPS_XLR308C    0x0f    /* RMI XLR308-C                 ISA 64  */
  928 #define MIPS_XLS616     0x40    /* RMI XLS616                   ISA 64  */
  929 #define MIPS_XLS416     0x44    /* RMI XLS416                   ISA 64  */
  930 #define MIPS_XLS608     0x4A    /* RMI XLS608                   ISA 64  */
  931 #define MIPS_XLS408     0x4E    /* RMI XLS406                   ISA 64  */
  932 #define MIPS_XLS404     0x4F    /* RMI XLS404                   ISA 64  */
  933 #define MIPS_XLS408LITE 0x88    /* RMI XLS408-Lite              ISA 64  */
  934 #define MIPS_XLS404LITE 0x8C    /* RMI XLS404-Lite              ISA 64  */
  935 #define MIPS_XLS208     0x8E    /* RMI XLS208                   ISA 64  */
  936 #define MIPS_XLS204     0x8F    /* RMI XLS204                   ISA 64  */
  937 #define MIPS_XLS108     0xCE    /* RMI XLS108                   ISA 64  */
  938 #define MIPS_XLS104     0xCF    /* RMI XLS104                   ISA 64  */
  939 
  940 /*
  941  * CPU processor revision IDs for company ID == 7 (Microsoft)
  942  */
  943 #define MIPS_eMIPS      0x04    /* MSR's eMIPS */
  944 
  945 /*
  946  * FPU processor revision ID
  947  */
  948 #define MIPS_SOFT       0x00    /* Software emulation           ISA I   */
  949 #define MIPS_R2360      0x01    /* MIPS R2360 FPC               ISA I   */
  950 #define MIPS_R2010      0x02    /* MIPS R2010 FPC               ISA I   */
  951 #define MIPS_R3010      0x03    /* MIPS R3010 FPC               ISA I   */
  952 #define MIPS_R6010      0x04    /* MIPS R6010 FPC               ISA II  */
  953 #define MIPS_R4010      0x05    /* MIPS R4010 FPC               ISA II  */
  954 #define MIPS_R31LSI     0x06    /* LSI Logic derivate           ISA I   */
  955 #define MIPS_R3TOSH     0x22    /* Toshiba R3000 based FPU      ISA I   */
  956 
  957 #ifdef ENABLE_MIPS_TX3900
  958 #include <mips/r3900regs.h>
  959 #endif
  960 #ifdef MIPS64_SB1
  961 #include <mips/sb1regs.h>
  962 #endif
  963 #if defined(MIPS64_XLP) || defined(MIPS64_XLR) || defined(MIPS64_XLS)
  964 #include <mips/rmi/rmixlreg.h>
  965 #endif
  966 
  967 #endif /* _MIPS_CPUREGS_H_ */

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