FreeBSD/Linux Kernel Cross Reference
sys/arch/sandpoint/

	Name	Size	Last modified (GMT)	Description
	Parent directory		2011-05-23 18:02:13
	compile/		2008-12-02 20:13:47
	conf/		2008-12-02 20:13:47
	include/		2008-12-02 20:13:48
	isa/		2008-12-02 20:13:48
	pci/		2008-12-02 20:13:48
	sandpoint/		2008-12-02 20:13:48
	stand/		2011-05-23 18:02:10
	Makefile	109 bytes	2003-01-06 17:40:47
	README	6050 bytes	2007-10-17 19:56:54
	README.NAS	1210 bytes	2008-04-07 16:36:50

     /*      $NetBSD: README,v 1.3 2007/10/17 19:56:54 garbled Exp $ */
     
     Overview
     
     This is a port to the Motorola "SandPoint" evaluation system.  The
     SandPoint is the successor to the "Yellowknife" system.  The system
     can be fitted with different PMCs (Processor Mezzanine Cards).  This
     port is specifically for the rev X2 motherboard system with the PPC
     8240 PMC rev X4 installed.  It also works with the Altimus X2 PMC
    (MPC7400 with MPC107).
    
    All references (cf) listed here are for the MPC8240 Integrated Processor
    User's Manual.
    
    Information on the Sandpoint can be found on Motorola's web site:
    http://www.mot.com/SPS/PowerPC/teksupport/refdesigns/sandpoint.html
    
    
    SandPoint Hardware Configuration
    
    This port was developed on a Sandpoint X2 motherboard with a Unity X4 PMC.
    
    This port assumes that the jumpers are set as follows:
            S3/S4   - Mode 1: PMC w/o IDE (switches opposite, one nearest PCI
                      slot toward near edge)
            S5      - Interrupt to PMC normal (switch toward near edge)
            S6      - Local I/O shared with slot 2 (switch toward near edge)
    
    Mode 0 (PMC w/ IDE) does not appear to work right with ISA interrupts.  The
    interrupts from the Winbond chip do not appear at the PMC.
    
    On the PPMC, we assume a 100MHz clock.
    on PPMC: (C == closed, or "on")
        SW2:
            C       ROM on PCI bus (DINK32 on mainboard)
            -       Map "B": CHRP
            C       Motorola PPMC
            C       Wait for initialization (peripheral mode)
            -       Program mode: Normal mode
            -       Select normal ROM
            -       33 MHz only
            -       COP only resets local CPU/MPC107
        SW3:
            -C--C   PCI 33, Mem 66, PPC 266
            --      0.5 - 0.9 ns PCI hold time
            C       25 ohm PCI drive strength
    
    
    Address Map
    
    For this port, we choose the "Address Map B" (CHRP-compatible) for the
    system (see SW2, #2, above):
    
     (Processor View)
    0000 0000   0009 FFFF   System Memory
    000A 0000   000F FFFF   Compatibility Hole (programmable to go to PCI space
                            or system memory--programmed for system memory--cf 5.8)
    0010 0000   3FFF FFFF   System memory
    4000 0000   7FFF FFFF   Reserved (programmed to give a memory select
                            error if accessed--cf 5.7.2)
    8000 0000   FCFF FFFF   PCI memory space
    FD00 0000   FDFF FFFF   PCI/ISA memory space (see 5.8, CPU_FD_ALIAS_EN)
    FE00 0000   FE7F FFFF   PCI/ISA I/O space (Forwarded to PCI address space
                            with high byte zeroed, but FE01 0000 and up are
                            reserved)
    FE80 0000   FEBF FFFF   PCI I/O space (Forwarded to PCI I/O space with high
                            byte zeroed)
    FEC0 0000   FEDF FFFF   PCI configuration address register (Each word in this
                            range is aliased to the PCI CONFIG_ADDR register)
    FEE0 0000   FEEF FFFF   PCI configuration data register (Each word in this
                            range is aliased to the PCI CONFIG_DATA register)
    FEF0 0000   FEFF FFFF   PCI interrupt acknowledge
    FF00 0000   FF7F FFFF   32- or 64-bit Flash/ROM space (Can hit either local
                            memory or PCI bus -- cf. 5.6)
    FF80 0000   FFFF FFFF   8-, 32- or 64-bit Flash/ROM space (Can hit either
                            local memory or PCI bus -- cf. 5.6)
    
    This is a host-mode port, so the inbound and output translation windows
    are unused.
    
    The Embedded Utilities Memory Block (EUMB) is set to be 1M below the end
    of the PCI memory space: FC00 0000, so EUMBBAR is FC00 0000, giving us
    
    Message unit (I2O) base : FC00 0000     (cf. 10.2, 10.2.3, 10.3)
    DMA base                : FC00 1000     (cf. 9.2)
    ATU base                : FC00 2000     (cf. 4.3.3)
    I2C base                : FC00 3000     (cf. 11.3)
    EPIC base               : FC04 0000     (cf. 12.2)
    
    
    
    Boot Information
    
    The SandPoint ships with the Motorola DINK32 ROM.  This is a rather
    basic ROM with only serial-download (S-Record) capability for
    loading the kernel.  Basically, the kernel is loaded to a specified
    address and you jump to it.  The ROM takes care of initializing
    the MICRs and MCCRs.  There is really no boot information to pass.
    
   It would be nice to have a much more complete ROM interface, allowing
   settings for, say, bootp/tftp boot, automatic boot, and persistent
   settings (for console rate, auto boot, bootp, etc), and that might
   be provided at some point, but that's not available as of this
   writing.
   
   So, the kernel is hard-coded to boot w/ 32MB for now.
   
   
   
   Interrupt Configuration
   
   The 8240 has the internal EPIC.  For the SandPoint, the EPIC is programmed
   in mixed-mode (GCR) with direct interrupts (EICR).  With this configuration,
   there are 13 available interrupts:
           4 global timers
           5 direct IRQs
                   IRQ0 - PCI Slot #0 INTA#
                   IRQ1 - PCI Slot #1 INTA# / shared with WinBond I/O
                   IRQ2 - PCI Slot #2 INTA#
                   IRQ3 - PCI Slot #3 INTA#
                   IRQ4 - On-PPMC 16552 interrupt (Unity X2)
                   IRQ4 - pulled down w/ resistor (Unity X4)
           4 internal interrupts
                   I2C
                   DMA Ch0
                   DMA Ch1
                   I2O message unit
   
   The SandPoint can run in one of 4 interrupt modes:
     0 - PMC host with IDE (3.3v PCI slots are unavailable)
     1 - PMC host w/o IDE (all PCI slots are available)
     2 - PMC agent, Winbond providing arbitration & interrupt to INTA# on PMC
     3 - Yellowknife mode--just like #2, except drives INTA# on 4th PCI slot
   
   We choose to run in mode 1 as Motorola recommends modes 0 or 1 for
   all new development.  Unfortunately, mode 0 does not appear to
   work--"ISA" interrupts are lost.  In this mode, with interrupts
   routed to PCI slot 3, we have to check for both a Winbond (ISA)
   interrupt, and a PCI slot interrupt.  So basically, we have a
   two-level interrupt configuration for Winbond interrupts.  The ISA
   bus attachment registers an interrupt for PCI slot 3 with its own
   interrupt handler.  Drivers for ISA devices on the Winbond will
   register interrupts with the ISA interrupt handler.  The sticky
   part of this is how to deal with one global interrupt priority.
   
   
   
   SandPoint III "SP3" Interrupt Configuration
   
   With a help of additional logic circuit SP3 organizes external
   interrupt sources as EPIC serial mode interrupts.
           16 serial IRQs
                   IRQ0 - WinBond South bridge i8259 PIC, polarity inverted
                   IRQ1 - reserved
                   IRQ2 - PCI Slot #1, INTA#
                   IRQ3 - PCI Slot #2, INTA#
                   IRQ4 - PCI Slot #3, INTA#
                   IRQ5 - PCI Slot #4, INTA#
                   IRQ6 - WinBond INTA#
                   IRQ7 - WinBond INTB#
                   IRQ8 - WinBond INTC#
                   IRQ9 - WinBond INTD#
                   IRQ10 thru 15 - reserved
   SP3 provides switch selections to emulate SP1/2 compatible EPIC
   direct mode interrupt assignments.