The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/arm/allwinner/a10_dmac.h

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    1 /*-
    2  * Copyright (c) 2014-2016 Jared D. McNeill <jmcneill@invisible.ca>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   17  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   18  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
   19  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
   20  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
   21  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
   22  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD$
   27  */
   28 
   29 #ifndef _A10_DMAC_H_
   30 #define _A10_DMAC_H_
   31 
   32 #define AWIN_DMA_IRQ_EN_REG             0x0000
   33 #define AWIN_DMA_IRQ_PEND_STA_REG       0x0004
   34 #define AWIN_NDMA_AUTO_GATE_REG         0x0008
   35 #define AWIN_NDMA_REG(n)                (0x100+0x20*(n))
   36 #define AWIN_NDMA_CTL_REG               0x0000
   37 #define AWIN_NDMA_SRC_ADDR_REG          0x0004
   38 #define AWIN_NDMA_DEST_ADDR_REG         0x0008
   39 #define AWIN_NDMA_BC_REG                0x000c
   40 #define AWIN_DDMA_REG(n)                (0x300+0x20*(n))
   41 #define AWIN_DDMA_CTL_REG               0x0000
   42 #define AWIN_DDMA_SRC_START_ADDR_REG    0x0004
   43 #define AWIN_DDMA_DEST_START_ADDR_REG   0x0008
   44 #define AWIN_DDMA_BC_REG                0x000c
   45 #define AWIN_DDMA_PARA_REG              0x0018
   46 #define AWIN_DMA_IRQ_END_MASK           0xaaaaaaaa
   47 #define AWIN_DMA_IRQ_HF_MASK            0x55555555
   48 #define AWIN_DMA_IRQ_DDMA               0xffff0000
   49 #define AWIN_DMA_IRQ_DDMA_END(n)        (1U << (17+2*(n)))
   50 #define AWIN_DMA_IRQ_DDMA_HF(n)         (1U << (16+2*(n)))
   51 #define AWIN_DMA_IRQ_NDMA               0x0000ffff
   52 #define AWIN_DMA_IRQ_NDMA_END(n)        (1U << (1+2*(n)))
   53 #define AWIN_DMA_IRQ_NDMA_HF(n)         (1U << (0+2*(n)))
   54 #define AWIN_NDMA_AUTO_GATING_DIS       (1U << 16)
   55 #define AWIN_DMA_CTL_DST_DATA_WIDTH_SHIFT 25
   56 #define AWIN_DMA_CTL_DST_DATA_WIDTH_MASK (3U << AWIN_DMA_CTL_DST_DATA_WIDTH_SHIFT)
   57 #define AWIN_DMA_CTL_DATA_WIDTH_8       0
   58 #define AWIN_DMA_CTL_DATA_WIDTH_16      1
   59 #define AWIN_DMA_CTL_DATA_WIDTH_32      2
   60 #define AWIN_DMA_CTL_DST_BURST_LEN_SHIFT 23
   61 #define AWIN_DMA_CTL_DST_BURST_LEN_MASK (3 << AWIN_DMA_CTL_DST_BURST_LEN_SHIFT)
   62 #define AWIN_DMA_CTL_BURST_LEN_1        0
   63 #define AWIN_DMA_CTL_BURST_LEN_4        1
   64 #define AWIN_DMA_CTL_BURST_LEN_8        2
   65 #define AWIN_DMA_CTL_DST_DRQ_TYPE_SHIFT 16
   66 #define AWIN_DMA_CTL_DST_DRQ_TYPE_MASK  (0x1f << AWIN_DMA_CTL_DST_DRQ_TYPE_SHIFT)
   67 #define AWIN_DMA_CTL_BC_REMAINING       (1U << 15)
   68 #define AWIN_DMA_CTL_SRC_DATA_WIDTH_SHIFT 9
   69 #define AWIN_DMA_CTL_SRC_DATA_WIDTH_MASK (3U << AWIN_DMA_CTL_SRC_DATA_WIDTH_SHIFT)
   70 #define AWIN_DMA_CTL_SRC_BURST_LEN_SHIFT 7
   71 #define AWIN_DMA_CTL_SRC_BURST_LEN_MASK (3U << AWIN_DMA_CTL_SRC_BURST_LEN_SHIFT)
   72 #define AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT 0
   73 #define AWIN_DMA_CTL_SRC_DRQ_TYPE_MASK  (0x1f << AWIN_DMA_CTL_SRC_DRQ_TYPE_SHIFT)
   74 #define AWIN_NDMA_CTL_DMA_LOADING       (1U << 31)
   75 #define AWIN_NDMA_CTL_DMA_CONTIN_MODE   (1U << 30)
   76 #define AWIN_NDMA_CTL_WAIT_STATE_LOG2_SHIFT 27
   77 #define AWIN_NDMA_CTL_WAIT_STATE_LOG2_MASK (7U << AWIN_NDMA_CTL_WAIT_STATE_LOG2_SHIFT)
   78 #define AWIN_NDMA_CTL_DST_NON_SECURE    (1U << 22)
   79 #define AWIN_NDMA_CTL_DST_ADDR_NOINCR   (1U << 21)
   80 #define AWIN_NDMA_CTL_DRQ_IRO           0
   81 #define AWIN_NDMA_CTL_DRQ_IR1           1
   82 #define AWIN_NDMA_CTL_DRQ_SPDIF         2
   83 #define AWIN_NDMA_CTL_DRQ_IISO          3
   84 #define AWIN_NDMA_CTL_DRQ_IIS1          4
   85 #define AWIN_NDMA_CTL_DRQ_AC97          5
   86 #define AWIN_NDMA_CTL_DRQ_IIS2          6
   87 #define AWIN_NDMA_CTL_DRQ_UARTO         8
   88 #define AWIN_NDMA_CTL_DRQ_UART1         9
   89 #define AWIN_NDMA_CTL_DRQ_UART2         10
   90 #define AWIN_NDMA_CTL_DRQ_UART3         11
   91 #define AWIN_NDMA_CTL_DRQ_UART4         12
   92 #define AWIN_NDMA_CTL_DRQ_UART5         13
   93 #define AWIN_NDMA_CTL_DRQ_UART6         14
   94 #define AWIN_NDMA_CTL_DRQ_UART7         15
   95 #define AWIN_NDMA_CTL_DRQ_DDC           16
   96 #define AWIN_NDMA_CTL_DRQ_USB_EP1       17
   97 #define AWIN_NDMA_CTL_DRQ_CODEC         19
   98 #define AWIN_NDMA_CTL_DRQ_SRAM          21
   99 #define AWIN_NDMA_CTL_DRQ_SDRAM         22
  100 #define AWIN_NDMA_CTL_DRQ_TP_AD         23
  101 #define AWIN_NDMA_CTL_DRQ_SPI0          24
  102 #define AWIN_NDMA_CTL_DRQ_SPI1          25
  103 #define AWIN_NDMA_CTL_DRQ_SPI2          26
  104 #define AWIN_NDMA_CTL_DRQ_SPI3          27
  105 #define AWIN_NDMA_CTL_DRQ_USB_EP2       28
  106 #define AWIN_NDMA_CTL_DRQ_USB_EP3       29
  107 #define AWIN_NDMA_CTL_DRQ_USB_EP4       30
  108 #define AWIN_NDMA_CTL_DRQ_USB_EP5       31
  109 #define AWIN_NDMA_CTL_SRC_NON_SECURE    (1U << 6)
  110 #define AWIN_NDMA_CTL_SRC_ADDR_NOINCR   (1U << 5)
  111 #define AWIN_NDMA_BC_COUNT              0x0003ffff
  112 #define AWIN_DDMA_CTL_DMA_LOADING       (1U << 31)
  113 #define AWIN_DDMA_CTL_BUSY              (1U << 30)
  114 #define AWIN_DDMA_CTL_DMA_CONTIN_MODE   (1U << 29)
  115 #define AWIN_DDMA_CTL_DST_NON_SECURE    (1U << 28)
  116 #define AWIN_DDMA_CTL_DST_ADDR_MODE_SHIFT 21
  117 #define AWIN_DDMA_CTL_DST_ADDR_MODE_MASK (3U << AWIN_DDMA_CTL_DST_ADDR_MODE_SHIFT)
  118 #define AWIN_DDMA_CTL_DMA_ADDR_LINEAR   0
  119 #define AWIN_DDMA_CTL_DMA_ADDR_IO       1
  120 #define AWIN_DDMA_CTL_DMA_ADDR_HPAGE    2
  121 #define AWIN_DDMA_CTL_DMA_ADDR_VPAGE    3
  122 #define AWIN_DDMA_CTL_DST_DRQ_TYPE_SHIFT 16
  123 #define AWIN_DDMA_CTL_DST_DRQ_TYPE_MASK (0x1f << AWIN_DDMA_CTL_DST_DRQ_TYPE_SHIFT)
  124 #define AWIN_DDMA_CTL_DRQ_SRAM          0
  125 #define AWIN_DDMA_CTL_DRQ_SDRAM         1
  126 #define AWIN_DDMA_CTL_DRQ_NFC           3
  127 #define AWIN_DDMA_CTL_DRQ_USB0          4
  128 #define AWIN_DDMA_CTL_DRQ_EMAC_TX       6
  129 #define AWIN_DDMA_CTL_DRQ_EMAC_RX       7
  130 #define AWIN_DDMA_CTL_DRQ_SPI1_TX       8
  131 #define AWIN_DDMA_CTL_DRQ_SPI1_RX       9
  132 #define AWIN_DDMA_CTL_DRQ_SS_TX         10
  133 #define AWIN_DDMA_CTL_DRQ_SS_RX         11
  134 #define AWIN_DDMA_CTL_DRQ_TCON0         14
  135 #define AWIN_DDMA_CTL_DRQ_TCON1         15
  136 #define AWIN_DDMA_CTL_DRQ_MS_TX         23
  137 #define AWIN_DDMA_CTL_DRQ_MS_RX         23
  138 #define AWIN_DDMA_CTL_DRQ_HDMI_AUDIO    24
  139 #define AWIN_DDMA_CTL_DRQ_SPI0_TX       26
  140 #define AWIN_DDMA_CTL_DRQ_SPI0_RX       27
  141 #define AWIN_DDMA_CTL_DRQ_SPI2_TX       28
  142 #define AWIN_DDMA_CTL_DRQ_SPI2_RX       29
  143 #define AWIN_DDMA_CTL_DRQ_SPI3_TX       30
  144 #define AWIN_DDMA_CTL_DRQ_SPI3_RX       31
  145 #define AWIN_DDMA_CTL_SRC_NON_SECURE    (1U << 12)
  146 #define AWIN_DDMA_CTL_SRC_ADDR_MODE_SHIFT 5
  147 #define AWIN_DDMA_CTL_SRC_ADDR_MODE_MASK (3U << AWIN_DDMA_CTL_SRC_ADDR_MODE_SHIFT)
  148 #define AWIN_DDMA_BC_COUNT              0x00003fff
  149 #define AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_SHIFT 24
  150 #define AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_MASK (0xff << AWIN_DDMA_PARA_DST_DATA_BLK_SIZ_SHIFT)
  151 #define AWIN_DDMA_PARA_DST_WAIT_CYC_SHIFT 16
  152 #define AWIN_DDMA_PARA_DST_WAIT_CYC_MASK (0xff << AWIN_DDMA_PARA_DST_WAIT_CYC_SHIFT)
  153 #define AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_SHIFT 8
  154 #define AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_MASK (0xff << AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ_SHIFT)
  155 #define AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT 0
  156 #define AWIN_DDMA_PARA_SRC_WAIT_CYC_MASK (0xff << AWIN_DDMA_PARA_SRC_WAIT_CYC_SHIFT)
  157 
  158 #endif /* !_A10_DMAC_H_ */

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