1 /*-
2 * Copyright (c) 2012 Ganbold Tsagaankhuu <ganbold@gmail.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: releng/10.0/sys/arm/allwinner/aintc.c 245900 2013-01-25 07:21:22Z ganbold $");
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/kernel.h>
34 #include <sys/ktr.h>
35 #include <sys/module.h>
36 #include <sys/rman.h>
37 #include <machine/bus.h>
38 #include <machine/intr.h>
39
40 #include <dev/fdt/fdt_common.h>
41 #include <dev/ofw/openfirm.h>
42 #include <dev/ofw/ofw_bus.h>
43 #include <dev/ofw/ofw_bus_subr.h>
44
45 /**
46 * Interrupt controller registers
47 *
48 */
49 #define SW_INT_VECTOR_REG 0x00
50 #define SW_INT_BASE_ADR_REG 0x04
51 #define SW_INT_PROTECTION_REG 0x08
52 #define SW_INT_NMI_CTRL_REG 0x0c
53
54 #define SW_INT_IRQ_PENDING_REG0 0x10
55 #define SW_INT_IRQ_PENDING_REG1 0x14
56 #define SW_INT_IRQ_PENDING_REG2 0x18
57
58 #define SW_INT_FIQ_PENDING_REG0 0x20
59 #define SW_INT_FIQ_PENDING_REG1 0x24
60 #define SW_INT_FIQ_PENDING_REG2 0x28
61
62 #define SW_INT_SELECT_REG0 0x30
63 #define SW_INT_SELECT_REG1 0x34
64 #define SW_INT_SELECT_REG2 0x38
65
66 #define SW_INT_ENABLE_REG0 0x40
67 #define SW_INT_ENABLE_REG1 0x44
68 #define SW_INT_ENABLE_REG2 0x48
69
70 #define SW_INT_MASK_REG0 0x50
71 #define SW_INT_MASK_REG1 0x54
72 #define SW_INT_MASK_REG2 0x58
73
74 #define SW_INT_IRQNO_ENMI 0
75
76 #define SW_INT_IRQ_PENDING_REG(_b) (0x10 + ((_b) * 4))
77 #define SW_INT_FIQ_PENDING_REG(_b) (0x20 + ((_b) * 4))
78 #define SW_INT_SELECT_REG(_b) (0x30 + ((_b) * 4))
79 #define SW_INT_ENABLE_REG(_b) (0x40 + ((_b) * 4))
80 #define SW_INT_MASK_REG(_b) (0x50 + ((_b) * 4))
81
82 struct a10_aintc_softc {
83 device_t sc_dev;
84 struct resource * aintc_res;
85 bus_space_tag_t aintc_bst;
86 bus_space_handle_t aintc_bsh;
87 uint8_t ver;
88 };
89
90 static struct a10_aintc_softc *a10_aintc_sc = NULL;
91
92 #define aintc_read_4(reg) \
93 bus_space_read_4(a10_aintc_sc->aintc_bst, a10_aintc_sc->aintc_bsh, reg)
94 #define aintc_write_4(reg, val) \
95 bus_space_write_4(a10_aintc_sc->aintc_bst, a10_aintc_sc->aintc_bsh, reg, val)
96
97 static int
98 a10_aintc_probe(device_t dev)
99 {
100 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-ic"))
101 return (ENXIO);
102 device_set_desc(dev, "A10 AINTC Interrupt Controller");
103 return (BUS_PROBE_DEFAULT);
104 }
105
106 static int
107 a10_aintc_attach(device_t dev)
108 {
109 struct a10_aintc_softc *sc = device_get_softc(dev);
110 int rid = 0;
111 int i;
112
113 sc->sc_dev = dev;
114
115 if (a10_aintc_sc)
116 return (ENXIO);
117
118 sc->aintc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
119 if (!sc->aintc_res) {
120 device_printf(dev, "could not allocate resource\n");
121 return (ENXIO);
122 }
123
124 sc->aintc_bst = rman_get_bustag(sc->aintc_res);
125 sc->aintc_bsh = rman_get_bushandle(sc->aintc_res);
126
127 a10_aintc_sc = sc;
128
129 /* Disable & clear all interrupts */
130 for (i = 0; i < 3; i++) {
131 aintc_write_4(SW_INT_ENABLE_REG(i), 0);
132 aintc_write_4(SW_INT_MASK_REG(i), 0xffffffff);
133 }
134 /* enable protection mode*/
135 aintc_write_4(SW_INT_PROTECTION_REG, 0x01);
136
137 /* config the external interrupt source type*/
138 aintc_write_4(SW_INT_NMI_CTRL_REG, 0x00);
139
140 return (0);
141 }
142
143 static device_method_t a10_aintc_methods[] = {
144 DEVMETHOD(device_probe, a10_aintc_probe),
145 DEVMETHOD(device_attach, a10_aintc_attach),
146 { 0, 0 }
147 };
148
149 static driver_t a10_aintc_driver = {
150 "aintc",
151 a10_aintc_methods,
152 sizeof(struct a10_aintc_softc),
153 };
154
155 static devclass_t a10_aintc_devclass;
156
157 DRIVER_MODULE(aintc, simplebus, a10_aintc_driver, a10_aintc_devclass, 0, 0);
158
159 int
160 arm_get_next_irq(int last_irq)
161 {
162 uint32_t value;
163 int i, b;
164
165 for (i = 0; i < 3; i++) {
166 value = aintc_read_4(SW_INT_IRQ_PENDING_REG(i));
167 for (b = 0; b < 32; b++)
168 if (value & (1 << b)) {
169 return (i * 32 + b);
170 }
171 }
172
173 return (-1);
174 }
175
176 void
177 arm_mask_irq(uintptr_t nb)
178 {
179 uint32_t bit, block, value;
180
181 bit = (nb % 32);
182 block = (nb / 32);
183
184 value = aintc_read_4(SW_INT_ENABLE_REG(block));
185 value &= ~(1 << bit);
186 aintc_write_4(SW_INT_ENABLE_REG(block), value);
187
188 value = aintc_read_4(SW_INT_MASK_REG(block));
189 value |= (1 << bit);
190 aintc_write_4(SW_INT_MASK_REG(block), value);
191 }
192
193 void
194 arm_unmask_irq(uintptr_t nb)
195 {
196 uint32_t bit, block, value;
197
198 bit = (nb % 32);
199 block = (nb / 32);
200
201 value = aintc_read_4(SW_INT_ENABLE_REG(block));
202 value |= (1 << bit);
203 aintc_write_4(SW_INT_ENABLE_REG(block), value);
204
205 value = aintc_read_4(SW_INT_MASK_REG(block));
206 value &= ~(1 << bit);
207 aintc_write_4(SW_INT_MASK_REG(block), value);
208
209 if(nb == SW_INT_IRQNO_ENMI) /* must clear pending bit when enabled */
210 aintc_write_4(SW_INT_IRQ_PENDING_REG(0), (1 << SW_INT_IRQNO_ENMI));
211 }
Cache object: 844308c49cd1f4d3ce587fb2a416a3c5
|