Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/allwinner/aw_cir.c
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1 /*- 2 * Copyright (c) 2016 Ganbold Tsagaankhuu <ganbold@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Allwinner Consumer IR controller 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/rman.h> 40 #include <sys/sysctl.h> 41 #include <machine/bus.h> 42 43 #include <dev/ofw/openfirm.h> 44 #include <dev/ofw/ofw_bus.h> 45 #include <dev/ofw/ofw_bus_subr.h> 46 #include <dev/extres/clk/clk.h> 47 #include <dev/extres/hwreset/hwreset.h> 48 49 #include <dev/evdev/input.h> 50 #include <dev/evdev/evdev.h> 51 52 #define READ(_sc, _r) bus_read_4((_sc)->res[0], (_r)) 53 #define WRITE(_sc, _r, _v) bus_write_4((_sc)->res[0], (_r), (_v)) 54 55 /* IR Control */ 56 #define AW_IR_CTL 0x00 57 /* Global Enable */ 58 #define AW_IR_CTL_GEN (1 << 0) 59 /* RX enable */ 60 #define AW_IR_CTL_RXEN (1 << 1) 61 /* CIR mode enable */ 62 #define AW_IR_CTL_MD (1 << 4) | (1 << 5) 63 64 /* RX Config Reg */ 65 #define AW_IR_RXCTL 0x10 66 /* Pulse Polarity Invert flag */ 67 #define AW_IR_RXCTL_RPPI (1 << 2) 68 69 /* RX Data */ 70 #define AW_IR_RXFIFO 0x20 71 72 /* RX Interrupt Control */ 73 #define AW_IR_RXINT 0x2C 74 /* RX FIFO Overflow */ 75 #define AW_IR_RXINT_ROI_EN (1 << 0) 76 /* RX Packet End */ 77 #define AW_IR_RXINT_RPEI_EN (1 << 1) 78 /* RX FIFO Data Available */ 79 #define AW_IR_RXINT_RAI_EN (1 << 4) 80 /* RX FIFO available byte level */ 81 #define AW_IR_RXINT_RAL(val) ((val) << 8) 82 83 /* RX Interrupt Status Reg */ 84 #define AW_IR_RXSTA 0x30 85 /* RX FIFO Get Available Counter */ 86 #define AW_IR_RXSTA_COUNTER(val) (((val) >> 8) & (sc->fifo_size * 2 - 1)) 87 /* Clear all interrupt status */ 88 #define AW_IR_RXSTA_CLEARALL 0xff 89 90 /* IR Sample Configure Reg */ 91 #define AW_IR_CIR 0x34 92 93 /* 94 * Frequency sample: 23437.5Hz (Cycle: 42.7us) 95 * Pulse of NEC Remote > 560us 96 */ 97 /* Filter Threshold = 8 * 42.7 = ~341us < 500us */ 98 #define AW_IR_RXFILT_VAL (((8) & 0x3f) << 2) 99 /* Idle Threshold = (2 + 1) * 128 * 42.7 = ~16.4ms > 9ms */ 100 #define AW_IR_RXIDLE_VAL (((2) & 0xff) << 8) 101 102 /* Bit 15 - value (pulse/space) */ 103 #define VAL_MASK 0x80 104 /* Bits 0:14 - sample duration */ 105 #define PERIOD_MASK 0x7f 106 107 /* Clock rate for IR0 or IR1 clock in CIR mode */ 108 #define AW_IR_BASE_CLK 3000000 109 /* Frequency sample 3MHz/64 = 46875Hz (21.3us) */ 110 #define AW_IR_SAMPLE_64 (0 << 0) 111 /* Frequency sample 3MHz/128 = 23437.5Hz (42.7us) */ 112 #define AW_IR_SAMPLE_128 (1 << 0) 113 114 #define AW_IR_ERROR_CODE 0xffffffff 115 #define AW_IR_REPEAT_CODE 0x0 116 117 /* 80 * 42.7 = ~3.4ms, Lead1(4.5ms) > AW_IR_L1_MIN */ 118 #define AW_IR_L1_MIN 80 119 /* 40 * 42.7 = ~1.7ms, Lead0(4.5ms) Lead0R(2.25ms) > AW_IR_L0_MIN */ 120 #define AW_IR_L0_MIN 40 121 /* 26 * 42.7 = ~1109us ~= 561 * 2, Pulse < AW_IR_PMAX */ 122 #define AW_IR_PMAX 26 123 /* 26 * 42.7 = ~1109us ~= 561 * 2, D1 > AW_IR_DMID, D0 <= AW_IR_DMID */ 124 #define AW_IR_DMID 26 125 /* 53 * 42.7 = ~2263us ~= 561 * 4, D < AW_IR_DMAX */ 126 #define AW_IR_DMAX 53 127 128 /* Active Thresholds */ 129 #define AW_IR_ACTIVE_T_VAL AW_IR_L1_MIN 130 #define AW_IR_ACTIVE_T (((AW_IR_ACTIVE_T_VAL - 1) & 0xff) << 16) 131 #define AW_IR_ACTIVE_T_C_VAL 0 132 #define AW_IR_ACTIVE_T_C ((AW_IR_ACTIVE_T_C_VAL & 0xff) << 23) 133 134 /* Code masks */ 135 #define CODE_MASK 0x00ff00ff 136 #define INV_CODE_MASK 0xff00ff00 137 #define VALID_CODE_MASK 0x00ff0000 138 139 enum { 140 A10_IR = 1, 141 A13_IR, 142 A31_IR, 143 }; 144 145 #define AW_IR_RAW_BUF_SIZE 128 146 147 SYSCTL_NODE(_hw, OID_AUTO, aw_cir, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 148 "aw_cir driver"); 149 150 static int aw_cir_debug = 0; 151 SYSCTL_INT(_hw_aw_cir, OID_AUTO, debug, CTLFLAG_RWTUN, &aw_cir_debug, 0, 152 "Debug 1=on 0=off"); 153 154 struct aw_ir_softc { 155 device_t dev; 156 struct resource *res[2]; 157 void * intrhand; 158 int fifo_size; 159 int dcnt; /* Packet Count */ 160 unsigned char buf[AW_IR_RAW_BUF_SIZE]; 161 struct evdev_dev *sc_evdev; 162 }; 163 164 static struct resource_spec aw_ir_spec[] = { 165 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 166 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 167 { -1, 0 } 168 }; 169 170 static struct ofw_compat_data compat_data[] = { 171 { "allwinner,sun4i-a10-ir", A10_IR }, 172 { "allwinner,sun5i-a13-ir", A13_IR }, 173 { "allwinner,sun6i-a31-ir", A31_IR }, 174 { NULL, 0 } 175 }; 176 177 static void 178 aw_ir_buf_reset(struct aw_ir_softc *sc) 179 { 180 181 sc->dcnt = 0; 182 } 183 184 static void 185 aw_ir_buf_write(struct aw_ir_softc *sc, unsigned char data) 186 { 187 188 if (sc->dcnt < AW_IR_RAW_BUF_SIZE) 189 sc->buf[sc->dcnt++] = data; 190 else 191 if (bootverbose) 192 device_printf(sc->dev, "IR RX Buffer Full!\n"); 193 } 194 195 static int 196 aw_ir_buf_full(struct aw_ir_softc *sc) 197 { 198 199 return (sc->dcnt >= AW_IR_RAW_BUF_SIZE); 200 } 201 202 static unsigned char 203 aw_ir_read_data(struct aw_ir_softc *sc) 204 { 205 206 return (unsigned char)(READ(sc, AW_IR_RXFIFO) & 0xff); 207 } 208 209 static unsigned long 210 aw_ir_decode_packets(struct aw_ir_softc *sc) 211 { 212 unsigned int len, code; 213 unsigned int active_delay; 214 unsigned char val, last; 215 int i, bitcount; 216 217 if (bootverbose && __predict_false(aw_cir_debug) != 0) 218 device_printf(sc->dev, "sc->dcnt = %d\n", sc->dcnt); 219 220 /* Find Lead 1 (bit separator) */ 221 active_delay = AW_IR_ACTIVE_T_VAL * 222 (AW_IR_ACTIVE_T_C_VAL != 0 ? 128 : 1); 223 len = active_delay; 224 if (bootverbose && __predict_false(aw_cir_debug) != 0) 225 device_printf(sc->dev, "Initial len: %d\n", len); 226 for (i = 0; i < sc->dcnt; i++) { 227 val = sc->buf[i]; 228 if (val & VAL_MASK) 229 len += (val & PERIOD_MASK) + 1; 230 else { 231 if (len > AW_IR_L1_MIN) 232 break; 233 len = 0; 234 } 235 } 236 if (bootverbose && __predict_false(aw_cir_debug) != 0) 237 device_printf(sc->dev, "len = %d\n", len); 238 if ((val & VAL_MASK) || (len <= AW_IR_L1_MIN)) { 239 if (bootverbose && __predict_false(aw_cir_debug) != 0) 240 device_printf(sc->dev, "Bit separator error\n"); 241 goto error_code; 242 } 243 244 /* Find Lead 0 (bit length) */ 245 len = 0; 246 for (; i < sc->dcnt; i++) { 247 val = sc->buf[i]; 248 if (val & VAL_MASK) { 249 if(len > AW_IR_L0_MIN) 250 break; 251 len = 0; 252 } else 253 len += (val & PERIOD_MASK) + 1; 254 } 255 if ((!(val & VAL_MASK)) || (len <= AW_IR_L0_MIN)) { 256 if (bootverbose && __predict_false(aw_cir_debug) != 0) 257 device_printf(sc->dev, "Bit length error\n"); 258 goto error_code; 259 } 260 261 /* Start decoding */ 262 code = 0; 263 bitcount = 0; 264 last = 1; 265 len = 0; 266 for (; i < sc->dcnt; i++) { 267 val = sc->buf[i]; 268 if (last) { 269 if (val & VAL_MASK) 270 len += (val & PERIOD_MASK) + 1; 271 else { 272 if (len > AW_IR_PMAX) { 273 if (bootverbose) 274 device_printf(sc->dev, 275 "Pulse error, len=%d\n", 276 len); 277 goto error_code; 278 } 279 last = 0; 280 len = (val & PERIOD_MASK) + 1; 281 } 282 } else { 283 if (val & VAL_MASK) { 284 if (len > AW_IR_DMAX) { 285 if (bootverbose) 286 device_printf(sc->dev, 287 "Distance error, len=%d\n", 288 len); 289 goto error_code; 290 } else { 291 if (len > AW_IR_DMID) { 292 /* Decode */ 293 code |= 1 << bitcount; 294 } 295 bitcount++; 296 if (bitcount == 32) 297 break; /* Finish decoding */ 298 } 299 last = 1; 300 len = (val & PERIOD_MASK) + 1; 301 } else 302 len += (val & PERIOD_MASK) + 1; 303 } 304 } 305 return (code); 306 307 error_code: 308 309 return (AW_IR_ERROR_CODE); 310 } 311 312 static int 313 aw_ir_validate_code(unsigned long code) 314 { 315 unsigned long v1, v2; 316 317 /* Don't check address */ 318 v1 = code & CODE_MASK; 319 v2 = (code & INV_CODE_MASK) >> 8; 320 321 if (((v1 ^ v2) & VALID_CODE_MASK) == VALID_CODE_MASK) 322 return (0); /* valid */ 323 else 324 return (1); /* invalid */ 325 } 326 327 static void 328 aw_ir_intr(void *arg) 329 { 330 struct aw_ir_softc *sc; 331 uint32_t val; 332 int i, dcnt; 333 unsigned long ir_code; 334 int stat; 335 336 sc = (struct aw_ir_softc *)arg; 337 338 /* Read RX interrupt status */ 339 val = READ(sc, AW_IR_RXSTA); 340 if (bootverbose && __predict_false(aw_cir_debug) != 0) 341 device_printf(sc->dev, "RX interrupt status: %x\n", val); 342 343 /* Clean all pending interrupt statuses */ 344 WRITE(sc, AW_IR_RXSTA, val | AW_IR_RXSTA_CLEARALL); 345 346 /* When Rx FIFO Data available or Packet end */ 347 if (val & (AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RPEI_EN)) { 348 if (bootverbose && __predict_false(aw_cir_debug) != 0) 349 device_printf(sc->dev, 350 "RX FIFO Data available or Packet end\n"); 351 /* Get available message count in RX FIFO */ 352 dcnt = AW_IR_RXSTA_COUNTER(val); 353 /* Read FIFO */ 354 for (i = 0; i < dcnt; i++) { 355 if (aw_ir_buf_full(sc)) { 356 if (bootverbose) 357 device_printf(sc->dev, 358 "raw buffer full\n"); 359 break; 360 } else 361 aw_ir_buf_write(sc, aw_ir_read_data(sc)); 362 } 363 } 364 365 if (val & AW_IR_RXINT_RPEI_EN) { 366 /* RX Packet end */ 367 if (bootverbose && __predict_false(aw_cir_debug) != 0) 368 device_printf(sc->dev, "RX Packet end\n"); 369 ir_code = aw_ir_decode_packets(sc); 370 stat = aw_ir_validate_code(ir_code); 371 if (stat == 0) { 372 evdev_push_event(sc->sc_evdev, 373 EV_MSC, MSC_SCAN, ir_code); 374 evdev_sync(sc->sc_evdev); 375 } 376 if (bootverbose && __predict_false(aw_cir_debug) != 0) { 377 device_printf(sc->dev, "Final IR code: %lx\n", 378 ir_code); 379 device_printf(sc->dev, "IR code status: %d\n", 380 stat); 381 } 382 aw_ir_buf_reset(sc); 383 } 384 if (val & AW_IR_RXINT_ROI_EN) { 385 /* RX FIFO overflow */ 386 if (bootverbose) 387 device_printf(sc->dev, "RX FIFO overflow\n"); 388 /* Flush raw buffer */ 389 aw_ir_buf_reset(sc); 390 } 391 } 392 393 static int 394 aw_ir_probe(device_t dev) 395 { 396 397 if (!ofw_bus_status_okay(dev)) 398 return (ENXIO); 399 400 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 401 return (ENXIO); 402 403 device_set_desc(dev, "Allwinner CIR controller"); 404 return (BUS_PROBE_DEFAULT); 405 } 406 407 static int 408 aw_ir_attach(device_t dev) 409 { 410 struct aw_ir_softc *sc; 411 hwreset_t rst_apb; 412 clk_t clk_ir, clk_gate; 413 int err; 414 uint32_t val = 0; 415 416 clk_ir = clk_gate = NULL; 417 rst_apb = NULL; 418 419 sc = device_get_softc(dev); 420 sc->dev = dev; 421 422 if (bus_alloc_resources(dev, aw_ir_spec, sc->res) != 0) { 423 device_printf(dev, "could not allocate memory resource\n"); 424 return (ENXIO); 425 } 426 427 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 428 case A10_IR: 429 sc->fifo_size = 16; 430 break; 431 case A13_IR: 432 case A31_IR: 433 sc->fifo_size = 64; 434 break; 435 } 436 437 /* De-assert reset */ 438 if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst_apb) == 0) { 439 err = hwreset_deassert(rst_apb); 440 if (err != 0) { 441 device_printf(dev, "cannot de-assert reset\n"); 442 goto error; 443 } 444 } 445 446 /* Reset buffer */ 447 aw_ir_buf_reset(sc); 448 449 /* Get clocks and enable them */ 450 err = clk_get_by_ofw_name(dev, 0, "apb", &clk_gate); 451 if (err != 0) { 452 device_printf(dev, "Cannot get gate clock\n"); 453 goto error; 454 } 455 err = clk_get_by_ofw_name(dev, 0, "ir", &clk_ir); 456 if (err != 0) { 457 device_printf(dev, "Cannot get IR clock\n"); 458 goto error; 459 } 460 /* Set clock rate */ 461 err = clk_set_freq(clk_ir, AW_IR_BASE_CLK, 0); 462 if (err != 0) { 463 device_printf(dev, "cannot set IR clock rate\n"); 464 goto error; 465 } 466 /* Enable clocks */ 467 err = clk_enable(clk_gate); 468 if (err != 0) { 469 device_printf(dev, "Cannot enable clk gate\n"); 470 goto error; 471 } 472 err = clk_enable(clk_ir); 473 if (err != 0) { 474 device_printf(dev, "Cannot enable IR clock\n"); 475 goto error; 476 } 477 478 if (bus_setup_intr(dev, sc->res[1], 479 INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_ir_intr, sc, 480 &sc->intrhand)) { 481 bus_release_resources(dev, aw_ir_spec, sc->res); 482 device_printf(dev, "cannot setup interrupt handler\n"); 483 err = ENXIO; 484 goto error; 485 } 486 487 /* Enable CIR Mode */ 488 WRITE(sc, AW_IR_CTL, AW_IR_CTL_MD); 489 490 /* 491 * Set clock sample, filter, idle thresholds. 492 * Frequency sample = 3MHz/128 = 23437.5Hz (42.7us) 493 */ 494 val = AW_IR_SAMPLE_128; 495 val |= (AW_IR_RXFILT_VAL | AW_IR_RXIDLE_VAL); 496 val |= (AW_IR_ACTIVE_T | AW_IR_ACTIVE_T_C); 497 WRITE(sc, AW_IR_CIR, val); 498 499 /* Invert Input Signal */ 500 WRITE(sc, AW_IR_RXCTL, AW_IR_RXCTL_RPPI); 501 502 /* Clear All RX Interrupt Status */ 503 WRITE(sc, AW_IR_RXSTA, AW_IR_RXSTA_CLEARALL); 504 505 /* 506 * Enable RX interrupt in case of overflow, packet end 507 * and FIFO available. 508 * RX FIFO Threshold = FIFO size / 2 509 */ 510 WRITE(sc, AW_IR_RXINT, AW_IR_RXINT_ROI_EN | AW_IR_RXINT_RPEI_EN | 511 AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RAL((sc->fifo_size >> 1) - 1)); 512 513 /* Enable IR Module */ 514 val = READ(sc, AW_IR_CTL); 515 WRITE(sc, AW_IR_CTL, val | AW_IR_CTL_GEN | AW_IR_CTL_RXEN); 516 517 sc->sc_evdev = evdev_alloc(); 518 evdev_set_name(sc->sc_evdev, device_get_desc(sc->dev)); 519 evdev_set_phys(sc->sc_evdev, device_get_nameunit(sc->dev)); 520 evdev_set_id(sc->sc_evdev, BUS_HOST, 0, 0, 0); 521 evdev_support_event(sc->sc_evdev, EV_SYN); 522 evdev_support_event(sc->sc_evdev, EV_MSC); 523 evdev_support_msc(sc->sc_evdev, MSC_SCAN); 524 525 err = evdev_register(sc->sc_evdev); 526 if (err) { 527 device_printf(dev, 528 "failed to register evdev: error=%d\n", err); 529 goto error; 530 } 531 532 return (0); 533 error: 534 if (clk_gate != NULL) 535 clk_release(clk_gate); 536 if (clk_ir != NULL) 537 clk_release(clk_ir); 538 if (rst_apb != NULL) 539 hwreset_release(rst_apb); 540 evdev_free(sc->sc_evdev); 541 sc->sc_evdev = NULL; /* Avoid double free */ 542 543 bus_release_resources(dev, aw_ir_spec, sc->res); 544 return (ENXIO); 545 } 546 547 static device_method_t aw_ir_methods[] = { 548 DEVMETHOD(device_probe, aw_ir_probe), 549 DEVMETHOD(device_attach, aw_ir_attach), 550 551 DEVMETHOD_END 552 }; 553 554 static driver_t aw_ir_driver = { 555 "aw_ir", 556 aw_ir_methods, 557 sizeof(struct aw_ir_softc), 558 }; 559 560 DRIVER_MODULE(aw_ir, simplebus, aw_ir_driver, 0, 0); 561 MODULE_DEPEND(aw_ir, evdev, 1, 1, 1);
Cache object: 5e3bf153382f3851b31cc081bf8813d4
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