The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/arm/allwinner/aw_cir.c

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    1 /*-
    2  * Copyright (c) 2016 Ganbold Tsagaankhuu <ganbold@freebsd.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 /*
   28  * Allwinner Consumer IR controller
   29  */
   30 
   31 #include <sys/cdefs.h>
   32 __FBSDID("$FreeBSD$");
   33 
   34 #include <sys/param.h>
   35 #include <sys/systm.h>
   36 #include <sys/bus.h>
   37 #include <sys/kernel.h>
   38 #include <sys/module.h>
   39 #include <sys/rman.h>
   40 #include <sys/sysctl.h>
   41 #include <machine/bus.h>
   42 
   43 #include <dev/ofw/openfirm.h>
   44 #include <dev/ofw/ofw_bus.h>
   45 #include <dev/ofw/ofw_bus_subr.h>
   46 #include <dev/extres/clk/clk.h>
   47 #include <dev/extres/hwreset/hwreset.h>
   48 
   49 #include <dev/evdev/input.h>
   50 #include <dev/evdev/evdev.h>
   51 
   52 #define READ(_sc, _r)           bus_read_4((_sc)->res[0], (_r))
   53 #define WRITE(_sc, _r, _v)      bus_write_4((_sc)->res[0], (_r), (_v))
   54 
   55 /* IR Control */
   56 #define AW_IR_CTL                       0x00
   57 /* Global Enable */
   58 #define  AW_IR_CTL_GEN                  (1 << 0)
   59 /* RX enable */
   60 #define  AW_IR_CTL_RXEN                 (1 << 1)
   61 /* CIR mode enable */
   62 #define  AW_IR_CTL_MD                   (1 << 4) | (1 << 5)
   63 
   64 /* RX Config Reg */
   65 #define AW_IR_RXCTL                     0x10
   66 /* Pulse Polarity Invert flag */
   67 #define  AW_IR_RXCTL_RPPI               (1 << 2)
   68 
   69 /* RX Data */
   70 #define AW_IR_RXFIFO                    0x20
   71 
   72 /* RX Interrupt Control */
   73 #define AW_IR_RXINT                     0x2C
   74 /* RX FIFO Overflow */
   75 #define  AW_IR_RXINT_ROI_EN             (1 << 0)
   76 /* RX Packet End */
   77 #define  AW_IR_RXINT_RPEI_EN            (1 << 1)
   78 /* RX FIFO Data Available */
   79 #define  AW_IR_RXINT_RAI_EN             (1 << 4)
   80 /* RX FIFO available byte level */
   81 #define  AW_IR_RXINT_RAL(val)           ((val) << 8)
   82 
   83 /* RX Interrupt Status Reg */
   84 #define AW_IR_RXSTA                     0x30
   85 /* RX FIFO Get Available Counter */
   86 #define  AW_IR_RXSTA_COUNTER(val)       (((val) >> 8) & (sc->fifo_size * 2 - 1))
   87 /* Clear all interrupt status */
   88 #define  AW_IR_RXSTA_CLEARALL           0xff
   89 
   90 /* IR Sample Configure Reg */
   91 #define AW_IR_CIR                       0x34
   92 
   93 /*
   94  * Frequency sample: 23437.5Hz (Cycle: 42.7us)
   95  * Pulse of NEC Remote > 560us
   96  */
   97 /* Filter Threshold = 8 * 42.7 = ~341us < 500us */
   98 #define  AW_IR_RXFILT_VAL               (((8) & 0x3f) << 2)
   99 /* Idle Threshold = (2 + 1) * 128 * 42.7 = ~16.4ms > 9ms */
  100 #define  AW_IR_RXIDLE_VAL               (((2) & 0xff) << 8)
  101 
  102 /* Bit 15 - value (pulse/space) */
  103 #define VAL_MASK                        0x80
  104 /* Bits 0:14 - sample duration  */
  105 #define PERIOD_MASK                     0x7f
  106 
  107 /* Clock rate for IR0 or IR1 clock in CIR mode */
  108 #define AW_IR_BASE_CLK                  3000000
  109 /* Frequency sample 3MHz/64 = 46875Hz (21.3us) */
  110 #define AW_IR_SAMPLE_64                 (0 << 0)
  111 /* Frequency sample 3MHz/128 = 23437.5Hz (42.7us) */
  112 #define AW_IR_SAMPLE_128                (1 << 0)
  113 
  114 #define AW_IR_ERROR_CODE                0xffffffff
  115 #define AW_IR_REPEAT_CODE               0x0
  116 
  117 /* 80 * 42.7 = ~3.4ms, Lead1(4.5ms) > AW_IR_L1_MIN */
  118 #define AW_IR_L1_MIN                    80
  119 /* 40 * 42.7 = ~1.7ms, Lead0(4.5ms) Lead0R(2.25ms) > AW_IR_L0_MIN */
  120 #define AW_IR_L0_MIN                    40
  121 /* 26 * 42.7 = ~1109us ~= 561 * 2, Pulse < AW_IR_PMAX */
  122 #define AW_IR_PMAX                      26
  123 /* 26 * 42.7 = ~1109us ~= 561 * 2, D1 > AW_IR_DMID, D0 <= AW_IR_DMID */
  124 #define AW_IR_DMID                      26
  125 /* 53 * 42.7 = ~2263us ~= 561 * 4, D < AW_IR_DMAX */
  126 #define AW_IR_DMAX                      53
  127 
  128 /* Active Thresholds */
  129 #define AW_IR_ACTIVE_T_VAL              AW_IR_L1_MIN
  130 #define AW_IR_ACTIVE_T                  (((AW_IR_ACTIVE_T_VAL - 1) & 0xff) << 16)
  131 #define AW_IR_ACTIVE_T_C_VAL            0
  132 #define AW_IR_ACTIVE_T_C                ((AW_IR_ACTIVE_T_C_VAL & 0xff) << 23)
  133 
  134 /* Code masks */
  135 #define CODE_MASK                       0x00ff00ff
  136 #define INV_CODE_MASK                   0xff00ff00
  137 #define VALID_CODE_MASK                 0x00ff0000
  138 
  139 enum {
  140         A10_IR = 1,
  141         A13_IR,
  142         A31_IR,
  143 };
  144 
  145 #define AW_IR_RAW_BUF_SIZE              128
  146 
  147 struct aw_ir_softc {
  148         device_t                dev;
  149         struct resource         *res[2];
  150         void *                  intrhand;
  151         int                     fifo_size;
  152         int                     dcnt;   /* Packet Count */
  153         unsigned char           buf[AW_IR_RAW_BUF_SIZE];
  154         struct evdev_dev        *sc_evdev;
  155 };
  156 
  157 static struct resource_spec aw_ir_spec[] = {
  158         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
  159         { SYS_RES_IRQ,          0,      RF_ACTIVE | RF_SHAREABLE },
  160         { -1, 0 }
  161 };
  162 
  163 static struct ofw_compat_data compat_data[] = {
  164         { "allwinner,sun4i-a10-ir",     A10_IR },
  165         { "allwinner,sun5i-a13-ir",     A13_IR },
  166         { "allwinner,sun6i-a31-ir",     A31_IR },
  167         { NULL,                         0 }
  168 };
  169 
  170 static void
  171 aw_ir_buf_reset(struct aw_ir_softc *sc)
  172 {
  173 
  174         sc->dcnt = 0;
  175 }
  176 
  177 static void
  178 aw_ir_buf_write(struct aw_ir_softc *sc, unsigned char data)
  179 {
  180 
  181         if (sc->dcnt < AW_IR_RAW_BUF_SIZE)
  182                 sc->buf[sc->dcnt++] = data;
  183         else
  184                 if (bootverbose)
  185                         device_printf(sc->dev, "IR RX Buffer Full!\n");
  186 }
  187 
  188 static int
  189 aw_ir_buf_full(struct aw_ir_softc *sc)
  190 {
  191 
  192         return (sc->dcnt >= AW_IR_RAW_BUF_SIZE);
  193 }
  194 
  195 static unsigned char
  196 aw_ir_read_data(struct aw_ir_softc *sc)
  197 {
  198 
  199         return (unsigned char)(READ(sc, AW_IR_RXFIFO) & 0xff);
  200 }
  201 
  202 static unsigned long
  203 aw_ir_decode_packets(struct aw_ir_softc *sc)
  204 {
  205         unsigned int len, code;
  206         unsigned int active_delay;
  207         unsigned char val, last;
  208         int i, bitcount;
  209 
  210         if (bootverbose)
  211                 device_printf(sc->dev, "sc->dcnt = %d\n", sc->dcnt);
  212 
  213         /* Find Lead 1 (bit separator) */
  214         active_delay = AW_IR_ACTIVE_T_VAL *
  215             (AW_IR_ACTIVE_T_C_VAL != 0 ? 128 : 1);
  216         len = active_delay;
  217         if (bootverbose)
  218                 device_printf(sc->dev, "Initial len: %d\n", len);
  219         for (i = 0;  i < sc->dcnt; i++) {
  220                 val = sc->buf[i];
  221                 if (val & VAL_MASK)
  222                         len += (val & PERIOD_MASK) + 1;
  223                 else {
  224                         if (len > AW_IR_L1_MIN)
  225                                 break;
  226                         len = 0;
  227                 }
  228         }
  229         if (bootverbose)
  230                 device_printf(sc->dev, "len = %d\n", len);
  231         if ((val & VAL_MASK) || (len <= AW_IR_L1_MIN)) {
  232                 if (bootverbose)
  233                         device_printf(sc->dev, "Bit separator error\n");
  234                 goto error_code;
  235         }
  236 
  237         /* Find Lead 0 (bit length) */
  238         len = 0;
  239         for (; i < sc->dcnt; i++) {
  240                 val = sc->buf[i];
  241                 if (val & VAL_MASK) {
  242                         if(len > AW_IR_L0_MIN)
  243                                 break;
  244                         len = 0;
  245                 } else
  246                         len += (val & PERIOD_MASK) + 1;
  247         }
  248         if ((!(val & VAL_MASK)) || (len <= AW_IR_L0_MIN)) {
  249                 if (bootverbose)
  250                         device_printf(sc->dev, "Bit length error\n");
  251                 goto error_code;
  252         }
  253 
  254         /* Start decoding */
  255         code = 0;
  256         bitcount = 0;
  257         last = 1;
  258         len = 0;
  259         for (; i < sc->dcnt; i++) {
  260                 val = sc->buf[i];
  261                 if (last) {
  262                         if (val & VAL_MASK)
  263                                 len += (val & PERIOD_MASK) + 1;
  264                         else {
  265                                 if (len > AW_IR_PMAX) {
  266                                         if (bootverbose)
  267                                                 device_printf(sc->dev,
  268                                                     "Pulse error, len=%d\n",
  269                                                     len);
  270                                         goto error_code;
  271                                 }
  272                                 last = 0;
  273                                 len = (val & PERIOD_MASK) + 1;
  274                         }
  275                 } else {
  276                         if (val & VAL_MASK) {
  277                                 if (len > AW_IR_DMAX) {
  278                                         if (bootverbose)
  279                                                 device_printf(sc->dev,
  280                                                     "Distance error, len=%d\n",
  281                                                     len);
  282                                         goto error_code;
  283                                 } else {
  284                                         if (len > AW_IR_DMID) {
  285                                                 /* Decode */
  286                                                 code |= 1 << bitcount;
  287                                         }
  288                                         bitcount++;
  289                                         if (bitcount == 32)
  290                                                 break;  /* Finish decoding */
  291                                 }
  292                                 last = 1;
  293                                 len = (val & PERIOD_MASK) + 1;
  294                         } else
  295                                 len += (val & PERIOD_MASK) + 1;
  296                 }
  297         }
  298         return (code);
  299 
  300 error_code:
  301 
  302         return (AW_IR_ERROR_CODE);
  303 }
  304 
  305 static int
  306 aw_ir_validate_code(unsigned long code)
  307 {
  308         unsigned long v1, v2;
  309 
  310         /* Don't check address */
  311         v1 = code & CODE_MASK;
  312         v2 = (code & INV_CODE_MASK) >> 8;
  313 
  314         if (((v1 ^ v2) & VALID_CODE_MASK) == VALID_CODE_MASK)
  315                 return (0);     /* valid */
  316         else
  317                 return (1);     /* invalid */
  318 }
  319 
  320 static void
  321 aw_ir_intr(void *arg)
  322 {
  323         struct aw_ir_softc *sc;
  324         uint32_t val;
  325         int i, dcnt;
  326         unsigned long ir_code;
  327         int stat;
  328 
  329         sc = (struct aw_ir_softc *)arg;
  330 
  331         /* Read RX interrupt status */
  332         val = READ(sc, AW_IR_RXSTA);
  333         if (bootverbose)
  334                 device_printf(sc->dev, "RX interrupt status: %x\n", val);
  335 
  336         /* Clean all pending interrupt statuses */
  337         WRITE(sc, AW_IR_RXSTA, val | AW_IR_RXSTA_CLEARALL);
  338 
  339         /* When Rx FIFO Data available or Packet end */
  340         if (val & (AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RPEI_EN)) {
  341                 if (bootverbose)
  342                         device_printf(sc->dev,
  343                             "RX FIFO Data available or Packet end\n");
  344                 /* Get available message count in RX FIFO */
  345                 dcnt  = AW_IR_RXSTA_COUNTER(val);
  346                 /* Read FIFO */
  347                 for (i = 0; i < dcnt; i++) {
  348                         if (aw_ir_buf_full(sc)) {
  349                                 if (bootverbose)
  350                                         device_printf(sc->dev,
  351                                             "raw buffer full\n");
  352                                 break;
  353                         } else
  354                                 aw_ir_buf_write(sc, aw_ir_read_data(sc));
  355                 }
  356         }
  357 
  358         if (val & AW_IR_RXINT_RPEI_EN) {
  359                 /* RX Packet end */
  360                 if (bootverbose)
  361                         device_printf(sc->dev, "RX Packet end\n");
  362                 ir_code = aw_ir_decode_packets(sc);
  363                 stat = aw_ir_validate_code(ir_code);
  364                 if (stat == 0) {
  365                         evdev_push_event(sc->sc_evdev,
  366                             EV_MSC, MSC_SCAN, ir_code);
  367                         evdev_sync(sc->sc_evdev);
  368                 }
  369                 if (bootverbose) {
  370                         device_printf(sc->dev, "Final IR code: %lx\n",
  371                             ir_code);
  372                         device_printf(sc->dev, "IR code status: %d\n",
  373                             stat);
  374                 }
  375                 aw_ir_buf_reset(sc);
  376         }
  377         if (val & AW_IR_RXINT_ROI_EN) {
  378                 /* RX FIFO overflow */
  379                 if (bootverbose)
  380                         device_printf(sc->dev, "RX FIFO overflow\n");
  381                 /* Flush raw buffer */
  382                 aw_ir_buf_reset(sc);
  383         }
  384 }
  385 
  386 static int
  387 aw_ir_probe(device_t dev)
  388 {
  389 
  390         if (!ofw_bus_status_okay(dev))
  391                 return (ENXIO);
  392 
  393         if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
  394                 return (ENXIO);
  395 
  396         device_set_desc(dev, "Allwinner CIR controller");
  397         return (BUS_PROBE_DEFAULT);
  398 }
  399 
  400 static int
  401 aw_ir_attach(device_t dev)
  402 {
  403         struct aw_ir_softc *sc;
  404         hwreset_t rst_apb;
  405         clk_t clk_ir, clk_gate;
  406         int err;
  407         uint32_t val = 0;
  408 
  409         clk_ir = clk_gate = NULL;
  410         rst_apb = NULL;
  411 
  412         sc = device_get_softc(dev);
  413         sc->dev = dev;
  414 
  415         if (bus_alloc_resources(dev, aw_ir_spec, sc->res) != 0) {
  416                 device_printf(dev, "could not allocate memory resource\n");
  417                 return (ENXIO);
  418         }
  419 
  420         switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
  421         case A10_IR:
  422                 sc->fifo_size = 16;
  423                 break;
  424         case A13_IR:
  425         case A31_IR:
  426                 sc->fifo_size = 64;
  427                 break;
  428         }
  429 
  430         /* De-assert reset */
  431         if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst_apb) == 0) {
  432                 err = hwreset_deassert(rst_apb);
  433                 if (err != 0) {
  434                         device_printf(dev, "cannot de-assert reset\n");
  435                         goto error;
  436                 }
  437         }
  438 
  439         /* Reset buffer */
  440         aw_ir_buf_reset(sc);
  441 
  442         /* Get clocks and enable them */
  443         err = clk_get_by_ofw_name(dev, 0, "apb", &clk_gate);
  444         if (err != 0) {
  445                 device_printf(dev, "Cannot get gate clock\n");
  446                 goto error;
  447         }
  448         err = clk_get_by_ofw_name(dev, 0, "ir", &clk_ir);
  449         if (err != 0) {
  450                 device_printf(dev, "Cannot get IR clock\n");
  451                 goto error;
  452         }
  453         /* Set clock rate */
  454         err = clk_set_freq(clk_ir, AW_IR_BASE_CLK, 0);
  455         if (err != 0) {
  456                 device_printf(dev, "cannot set IR clock rate\n");
  457                 goto error;
  458         }
  459         /* Enable clocks */
  460         err = clk_enable(clk_gate);
  461         if (err != 0) {
  462                 device_printf(dev, "Cannot enable clk gate\n");
  463                 goto error;
  464         }
  465         err = clk_enable(clk_ir);
  466         if (err != 0) {
  467                 device_printf(dev, "Cannot enable IR clock\n");
  468                 goto error;
  469         }
  470 
  471         if (bus_setup_intr(dev, sc->res[1],
  472             INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_ir_intr, sc,
  473             &sc->intrhand)) {
  474                 bus_release_resources(dev, aw_ir_spec, sc->res);
  475                 device_printf(dev, "cannot setup interrupt handler\n");
  476                 err = ENXIO;
  477                 goto error;
  478         }
  479 
  480         /* Enable CIR Mode */
  481         WRITE(sc, AW_IR_CTL, AW_IR_CTL_MD);
  482 
  483         /*
  484          * Set clock sample, filter, idle thresholds.
  485          * Frequency sample = 3MHz/128 = 23437.5Hz (42.7us)
  486          */
  487         val = AW_IR_SAMPLE_128;
  488         val |= (AW_IR_RXFILT_VAL | AW_IR_RXIDLE_VAL);
  489         val |= (AW_IR_ACTIVE_T | AW_IR_ACTIVE_T_C);
  490         WRITE(sc, AW_IR_CIR, val);
  491 
  492         /* Invert Input Signal */
  493         WRITE(sc, AW_IR_RXCTL, AW_IR_RXCTL_RPPI);
  494 
  495         /* Clear All RX Interrupt Status */
  496         WRITE(sc, AW_IR_RXSTA, AW_IR_RXSTA_CLEARALL);
  497 
  498         /*
  499          * Enable RX interrupt in case of overflow, packet end
  500          * and FIFO available.
  501          * RX FIFO Threshold = FIFO size / 2
  502          */
  503         WRITE(sc, AW_IR_RXINT, AW_IR_RXINT_ROI_EN | AW_IR_RXINT_RPEI_EN |
  504             AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RAL((sc->fifo_size >> 1) - 1));
  505 
  506         /* Enable IR Module */
  507         val = READ(sc, AW_IR_CTL);
  508         WRITE(sc, AW_IR_CTL, val | AW_IR_CTL_GEN | AW_IR_CTL_RXEN);
  509 
  510         sc->sc_evdev = evdev_alloc();
  511         evdev_set_name(sc->sc_evdev, device_get_desc(sc->dev));
  512         evdev_set_phys(sc->sc_evdev, device_get_nameunit(sc->dev));
  513         evdev_set_id(sc->sc_evdev, BUS_HOST, 0, 0, 0);
  514         evdev_support_event(sc->sc_evdev, EV_SYN);
  515         evdev_support_event(sc->sc_evdev, EV_MSC);
  516         evdev_support_msc(sc->sc_evdev, MSC_SCAN);
  517 
  518         err = evdev_register(sc->sc_evdev);
  519         if (err) {
  520                 device_printf(dev,
  521                     "failed to register evdev: error=%d\n", err);
  522                 goto error;
  523         }
  524 
  525         return (0);
  526 error:
  527         if (clk_gate != NULL)
  528                 clk_release(clk_gate);
  529         if (clk_ir != NULL)
  530                 clk_release(clk_ir);
  531         if (rst_apb != NULL)
  532                 hwreset_release(rst_apb);
  533         evdev_free(sc->sc_evdev);
  534         sc->sc_evdev = NULL;    /* Avoid double free */
  535 
  536         bus_release_resources(dev, aw_ir_spec, sc->res);
  537         return (ENXIO);
  538 }
  539 
  540 static device_method_t aw_ir_methods[] = {
  541         DEVMETHOD(device_probe, aw_ir_probe),
  542         DEVMETHOD(device_attach, aw_ir_attach),
  543 
  544         DEVMETHOD_END
  545 };
  546 
  547 static driver_t aw_ir_driver = {
  548         "aw_ir",
  549         aw_ir_methods,
  550         sizeof(struct aw_ir_softc),
  551 };
  552 static devclass_t aw_ir_devclass;
  553 
  554 DRIVER_MODULE(aw_ir, simplebus, aw_ir_driver, aw_ir_devclass, 0, 0);
  555 MODULE_DEPEND(aw_ir, evdev, 1, 1, 1);

Cache object: 7a55f73b1725237bd8ae371aa4e8ff3c


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