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sys/arm/allwinner/aw_mmc.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * Copyright (c) 2013 Alexander Fedorov 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/module.h> 40 #include <sys/mutex.h> 41 #include <sys/resource.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 #include <sys/queue.h> 45 #include <sys/taskqueue.h> 46 47 #include <machine/bus.h> 48 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <dev/mmc/bridge.h> 53 #include <dev/mmc/mmcbrvar.h> 54 #include <dev/mmc/mmc_fdt_helpers.h> 55 56 #include <arm/allwinner/aw_mmc.h> 57 #include <dev/extres/clk/clk.h> 58 #include <dev/extres/hwreset/hwreset.h> 59 #include <dev/extres/regulator/regulator.h> 60 61 #include "opt_mmccam.h" 62 63 #ifdef MMCCAM 64 #include <cam/cam.h> 65 #include <cam/cam_ccb.h> 66 #include <cam/cam_debug.h> 67 #include <cam/cam_sim.h> 68 #include <cam/cam_xpt_sim.h> 69 #include <cam/mmc/mmc_sim.h> 70 71 #include "mmc_sim_if.h" 72 #endif 73 74 #include "mmc_pwrseq_if.h" 75 76 #define AW_MMC_MEMRES 0 77 #define AW_MMC_IRQRES 1 78 #define AW_MMC_RESSZ 2 79 #define AW_MMC_DMA_SEGS (PAGE_SIZE / sizeof(struct aw_mmc_dma_desc)) 80 #define AW_MMC_DMA_DESC_SIZE (sizeof(struct aw_mmc_dma_desc) * AW_MMC_DMA_SEGS) 81 #define AW_MMC_DMA_FTRGLEVEL 0x20070008 82 83 #define AW_MMC_RESET_RETRY 1000 84 85 #define CARD_ID_FREQUENCY 400000 86 87 struct aw_mmc_conf { 88 uint32_t dma_xferlen; 89 bool mask_data0; 90 bool can_calibrate; 91 bool new_timing; 92 }; 93 94 static const struct aw_mmc_conf a10_mmc_conf = { 95 .dma_xferlen = 0x2000, 96 }; 97 98 static const struct aw_mmc_conf a13_mmc_conf = { 99 .dma_xferlen = 0x10000, 100 }; 101 102 static const struct aw_mmc_conf a64_mmc_conf = { 103 .dma_xferlen = 0x10000, 104 .mask_data0 = true, 105 .can_calibrate = true, 106 .new_timing = true, 107 }; 108 109 static const struct aw_mmc_conf a64_emmc_conf = { 110 .dma_xferlen = 0x2000, 111 .can_calibrate = true, 112 }; 113 114 static struct ofw_compat_data compat_data[] = { 115 {"allwinner,sun4i-a10-mmc", (uintptr_t)&a10_mmc_conf}, 116 {"allwinner,sun5i-a13-mmc", (uintptr_t)&a13_mmc_conf}, 117 {"allwinner,sun7i-a20-mmc", (uintptr_t)&a13_mmc_conf}, 118 {"allwinner,sun50i-a64-mmc", (uintptr_t)&a64_mmc_conf}, 119 {"allwinner,sun50i-a64-emmc", (uintptr_t)&a64_emmc_conf}, 120 {NULL, 0} 121 }; 122 123 struct aw_mmc_softc { 124 device_t aw_dev; 125 clk_t aw_clk_ahb; 126 clk_t aw_clk_mmc; 127 hwreset_t aw_rst_ahb; 128 int aw_bus_busy; 129 int aw_resid; 130 int aw_timeout; 131 struct callout aw_timeoutc; 132 struct mmc_host aw_host; 133 struct mmc_fdt_helper mmc_helper; 134 #ifdef MMCCAM 135 union ccb * ccb; 136 struct mmc_sim mmc_sim; 137 #else 138 struct mmc_request * aw_req; 139 #endif 140 struct mtx aw_mtx; 141 struct resource * aw_res[AW_MMC_RESSZ]; 142 struct aw_mmc_conf * aw_mmc_conf; 143 uint32_t aw_intr; 144 uint32_t aw_intr_wait; 145 void * aw_intrhand; 146 unsigned int aw_clock; 147 device_t child; 148 149 /* Fields required for DMA access. */ 150 bus_addr_t aw_dma_desc_phys; 151 bus_dmamap_t aw_dma_map; 152 bus_dma_tag_t aw_dma_tag; 153 void * aw_dma_desc; 154 bus_dmamap_t aw_dma_buf_map; 155 bus_dma_tag_t aw_dma_buf_tag; 156 int aw_dma_map_err; 157 }; 158 159 static struct resource_spec aw_mmc_res_spec[] = { 160 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 161 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 162 { -1, 0, 0 } 163 }; 164 165 static int aw_mmc_probe(device_t); 166 static int aw_mmc_attach(device_t); 167 static int aw_mmc_detach(device_t); 168 static int aw_mmc_setup_dma(struct aw_mmc_softc *); 169 static void aw_mmc_teardown_dma(struct aw_mmc_softc *sc); 170 static int aw_mmc_reset(struct aw_mmc_softc *); 171 static int aw_mmc_init(struct aw_mmc_softc *); 172 static void aw_mmc_intr(void *); 173 static int aw_mmc_update_clock(struct aw_mmc_softc *, uint32_t); 174 static void aw_mmc_helper_cd_handler(device_t, bool); 175 176 static void aw_mmc_print_error(uint32_t); 177 static int aw_mmc_update_ios(device_t, device_t); 178 static int aw_mmc_request(device_t, device_t, struct mmc_request *); 179 180 #ifndef MMCCAM 181 static int aw_mmc_get_ro(device_t, device_t); 182 static int aw_mmc_acquire_host(device_t, device_t); 183 static int aw_mmc_release_host(device_t, device_t); 184 #endif 185 186 #define AW_MMC_LOCK(_sc) mtx_lock(&(_sc)->aw_mtx) 187 #define AW_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->aw_mtx) 188 #define AW_MMC_READ_4(_sc, _reg) \ 189 bus_read_4((_sc)->aw_res[AW_MMC_MEMRES], _reg) 190 #define AW_MMC_WRITE_4(_sc, _reg, _value) \ 191 bus_write_4((_sc)->aw_res[AW_MMC_MEMRES], _reg, _value) 192 193 SYSCTL_NODE(_hw, OID_AUTO, aw_mmc, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 194 "aw_mmc driver"); 195 196 static int aw_mmc_debug = 0; 197 SYSCTL_INT(_hw_aw_mmc, OID_AUTO, debug, CTLFLAG_RWTUN, &aw_mmc_debug, 0, 198 "Debug level bit0=card changes bit1=ios changes, bit2=interrupts, bit3=commands"); 199 #define AW_MMC_DEBUG_CARD 0x1 200 #define AW_MMC_DEBUG_IOS 0x2 201 #define AW_MMC_DEBUG_INT 0x4 202 #define AW_MMC_DEBUG_CMD 0x8 203 204 #ifdef MMCCAM 205 static int 206 aw_mmc_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 207 { 208 struct aw_mmc_softc *sc; 209 210 sc = device_get_softc(dev); 211 212 cts->host_ocr = sc->aw_host.host_ocr; 213 cts->host_f_min = sc->aw_host.f_min; 214 cts->host_f_max = sc->aw_host.f_max; 215 cts->host_caps = sc->aw_host.caps; 216 cts->host_max_data = (sc->aw_mmc_conf->dma_xferlen * 217 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 218 memcpy(&cts->ios, &sc->aw_host.ios, sizeof(struct mmc_ios)); 219 220 return (0); 221 } 222 223 static int 224 aw_mmc_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 225 { 226 struct aw_mmc_softc *sc; 227 struct mmc_ios *ios; 228 struct mmc_ios *new_ios; 229 230 sc = device_get_softc(dev); 231 ios = &sc->aw_host.ios; 232 new_ios = &cts->ios; 233 234 /* Update only requested fields */ 235 if (cts->ios_valid & MMC_CLK) { 236 ios->clock = new_ios->clock; 237 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 238 device_printf(sc->aw_dev, "Clock => %d\n", ios->clock); 239 } 240 if (cts->ios_valid & MMC_VDD) { 241 ios->vdd = new_ios->vdd; 242 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 243 device_printf(sc->aw_dev, "VDD => %d\n", ios->vdd); 244 } 245 if (cts->ios_valid & MMC_CS) { 246 ios->chip_select = new_ios->chip_select; 247 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 248 device_printf(sc->aw_dev, "CS => %d\n", ios->chip_select); 249 } 250 if (cts->ios_valid & MMC_BW) { 251 ios->bus_width = new_ios->bus_width; 252 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 253 device_printf(sc->aw_dev, "Bus width => %d\n", ios->bus_width); 254 } 255 if (cts->ios_valid & MMC_PM) { 256 ios->power_mode = new_ios->power_mode; 257 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 258 device_printf(sc->aw_dev, "Power mode => %d\n", ios->power_mode); 259 } 260 if (cts->ios_valid & MMC_BT) { 261 ios->timing = new_ios->timing; 262 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 263 device_printf(sc->aw_dev, "Timing => %d\n", ios->timing); 264 } 265 if (cts->ios_valid & MMC_BM) { 266 ios->bus_mode = new_ios->bus_mode; 267 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_IOS)) 268 device_printf(sc->aw_dev, "Bus mode => %d\n", ios->bus_mode); 269 } 270 271 return (aw_mmc_update_ios(sc->aw_dev, NULL)); 272 } 273 274 static int 275 aw_mmc_cam_request(device_t dev, union ccb *ccb) 276 { 277 struct aw_mmc_softc *sc; 278 struct ccb_mmcio *mmcio; 279 280 sc = device_get_softc(dev); 281 mmcio = &ccb->mmcio; 282 283 AW_MMC_LOCK(sc); 284 285 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) { 286 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 287 mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, 288 mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, 289 mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); 290 } 291 if (mmcio->cmd.data != NULL) { 292 if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) 293 panic("data->len = %d, data->flags = %d -- something is b0rked", 294 (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); 295 } 296 if (sc->ccb != NULL) { 297 device_printf(sc->aw_dev, "Controller still has an active command\n"); 298 return (EBUSY); 299 } 300 sc->ccb = ccb; 301 /* aw_mmc_request locks again */ 302 AW_MMC_UNLOCK(sc); 303 aw_mmc_request(sc->aw_dev, NULL, NULL); 304 305 return (0); 306 } 307 #endif /* MMCCAM */ 308 309 static void 310 aw_mmc_helper_cd_handler(device_t dev, bool present) 311 { 312 struct aw_mmc_softc *sc; 313 314 sc = device_get_softc(dev); 315 #ifdef MMCCAM 316 mmc_cam_sim_discover(&sc->mmc_sim); 317 #else 318 AW_MMC_LOCK(sc); 319 if (present) { 320 if (sc->child == NULL) { 321 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD)) 322 device_printf(sc->aw_dev, "Card inserted\n"); 323 324 sc->child = device_add_child(sc->aw_dev, "mmc", -1); 325 AW_MMC_UNLOCK(sc); 326 if (sc->child) { 327 device_set_ivars(sc->child, sc); 328 (void)device_probe_and_attach(sc->child); 329 } 330 } else 331 AW_MMC_UNLOCK(sc); 332 } else { 333 /* Card isn't present, detach if necessary */ 334 if (sc->child != NULL) { 335 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD)) 336 device_printf(sc->aw_dev, "Card removed\n"); 337 338 AW_MMC_UNLOCK(sc); 339 device_delete_child(sc->aw_dev, sc->child); 340 sc->child = NULL; 341 } else 342 AW_MMC_UNLOCK(sc); 343 } 344 #endif /* MMCCAM */ 345 } 346 347 static int 348 aw_mmc_probe(device_t dev) 349 { 350 351 if (!ofw_bus_status_okay(dev)) 352 return (ENXIO); 353 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 354 return (ENXIO); 355 356 device_set_desc(dev, "Allwinner Integrated MMC/SD controller"); 357 358 return (BUS_PROBE_DEFAULT); 359 } 360 361 static int 362 aw_mmc_attach(device_t dev) 363 { 364 struct aw_mmc_softc *sc; 365 struct sysctl_ctx_list *ctx; 366 struct sysctl_oid_list *tree; 367 int error; 368 369 sc = device_get_softc(dev); 370 sc->aw_dev = dev; 371 372 sc->aw_mmc_conf = (struct aw_mmc_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 373 374 #ifndef MMCCAM 375 sc->aw_req = NULL; 376 #endif 377 if (bus_alloc_resources(dev, aw_mmc_res_spec, sc->aw_res) != 0) { 378 device_printf(dev, "cannot allocate device resources\n"); 379 return (ENXIO); 380 } 381 if (bus_setup_intr(dev, sc->aw_res[AW_MMC_IRQRES], 382 INTR_TYPE_NET | INTR_MPSAFE, NULL, aw_mmc_intr, sc, 383 &sc->aw_intrhand)) { 384 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 385 device_printf(dev, "cannot setup interrupt handler\n"); 386 return (ENXIO); 387 } 388 mtx_init(&sc->aw_mtx, device_get_nameunit(sc->aw_dev), "aw_mmc", 389 MTX_DEF); 390 callout_init_mtx(&sc->aw_timeoutc, &sc->aw_mtx, 0); 391 392 /* De-assert reset */ 393 if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->aw_rst_ahb) == 0) { 394 error = hwreset_deassert(sc->aw_rst_ahb); 395 if (error != 0) { 396 device_printf(dev, "cannot de-assert reset\n"); 397 goto fail; 398 } 399 } 400 401 /* Activate the module clock. */ 402 error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->aw_clk_ahb); 403 if (error != 0) { 404 device_printf(dev, "cannot get ahb clock\n"); 405 goto fail; 406 } 407 error = clk_enable(sc->aw_clk_ahb); 408 if (error != 0) { 409 device_printf(dev, "cannot enable ahb clock\n"); 410 goto fail; 411 } 412 error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->aw_clk_mmc); 413 if (error != 0) { 414 device_printf(dev, "cannot get mmc clock\n"); 415 goto fail; 416 } 417 error = clk_set_freq(sc->aw_clk_mmc, CARD_ID_FREQUENCY, 418 CLK_SET_ROUND_DOWN); 419 if (error != 0) { 420 device_printf(dev, "cannot init mmc clock\n"); 421 goto fail; 422 } 423 error = clk_enable(sc->aw_clk_mmc); 424 if (error != 0) { 425 device_printf(dev, "cannot enable mmc clock\n"); 426 goto fail; 427 } 428 429 sc->aw_timeout = 10; 430 ctx = device_get_sysctl_ctx(dev); 431 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 432 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW, 433 &sc->aw_timeout, 0, "Request timeout in seconds"); 434 435 /* Soft Reset controller. */ 436 if (aw_mmc_reset(sc) != 0) { 437 device_printf(dev, "cannot reset the controller\n"); 438 goto fail; 439 } 440 441 if (aw_mmc_setup_dma(sc) != 0) { 442 device_printf(sc->aw_dev, "Couldn't setup DMA!\n"); 443 goto fail; 444 } 445 446 /* Set some defaults for freq and supported mode */ 447 sc->aw_host.f_min = 400000; 448 sc->aw_host.f_max = 52000000; 449 sc->aw_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; 450 sc->aw_host.caps |= MMC_CAP_HSPEED | MMC_CAP_SIGNALING_330; 451 mmc_fdt_parse(dev, 0, &sc->mmc_helper, &sc->aw_host); 452 mmc_fdt_gpio_setup(dev, 0, &sc->mmc_helper, aw_mmc_helper_cd_handler); 453 454 #ifdef MMCCAM 455 sc->ccb = NULL; 456 457 if (mmc_cam_sim_alloc(dev, "aw_mmc", &sc->mmc_sim) != 0) { 458 device_printf(dev, "cannot alloc cam sim\n"); 459 goto fail; 460 } 461 #endif /* MMCCAM */ 462 463 return (0); 464 465 fail: 466 callout_drain(&sc->aw_timeoutc); 467 mtx_destroy(&sc->aw_mtx); 468 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand); 469 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 470 471 return (ENXIO); 472 } 473 474 static int 475 aw_mmc_detach(device_t dev) 476 { 477 struct aw_mmc_softc *sc; 478 device_t d; 479 480 sc = device_get_softc(dev); 481 482 clk_disable(sc->aw_clk_mmc); 483 clk_disable(sc->aw_clk_ahb); 484 hwreset_assert(sc->aw_rst_ahb); 485 486 mmc_fdt_gpio_teardown(&sc->mmc_helper); 487 488 callout_drain(&sc->aw_timeoutc); 489 490 AW_MMC_LOCK(sc); 491 d = sc->child; 492 sc->child = NULL; 493 AW_MMC_UNLOCK(sc); 494 if (d != NULL) 495 device_delete_child(sc->aw_dev, d); 496 497 aw_mmc_teardown_dma(sc); 498 499 mtx_destroy(&sc->aw_mtx); 500 501 bus_teardown_intr(dev, sc->aw_res[AW_MMC_IRQRES], sc->aw_intrhand); 502 bus_release_resources(dev, aw_mmc_res_spec, sc->aw_res); 503 504 #ifdef MMCCAM 505 mmc_cam_sim_free(&sc->mmc_sim); 506 #endif 507 508 return (0); 509 } 510 511 static void 512 aw_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 513 { 514 struct aw_mmc_softc *sc; 515 516 sc = (struct aw_mmc_softc *)arg; 517 if (err) { 518 sc->aw_dma_map_err = err; 519 return; 520 } 521 sc->aw_dma_desc_phys = segs[0].ds_addr; 522 } 523 524 static int 525 aw_mmc_setup_dma(struct aw_mmc_softc *sc) 526 { 527 int error; 528 529 /* Allocate the DMA descriptor memory. */ 530 error = bus_dma_tag_create( 531 bus_get_dma_tag(sc->aw_dev), /* parent */ 532 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 533 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 534 BUS_SPACE_MAXADDR, /* highaddr */ 535 NULL, NULL, /* filter, filterarg*/ 536 AW_MMC_DMA_DESC_SIZE, 1, /* maxsize, nsegment */ 537 AW_MMC_DMA_DESC_SIZE, /* maxsegsize */ 538 0, /* flags */ 539 NULL, NULL, /* lock, lockarg*/ 540 &sc->aw_dma_tag); 541 if (error) 542 return (error); 543 544 error = bus_dmamem_alloc(sc->aw_dma_tag, &sc->aw_dma_desc, 545 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, 546 &sc->aw_dma_map); 547 if (error) 548 return (error); 549 550 error = bus_dmamap_load(sc->aw_dma_tag, 551 sc->aw_dma_map, 552 sc->aw_dma_desc, AW_MMC_DMA_DESC_SIZE, 553 aw_dma_desc_cb, sc, 0); 554 if (error) 555 return (error); 556 if (sc->aw_dma_map_err) 557 return (sc->aw_dma_map_err); 558 559 /* Create the DMA map for data transfers. */ 560 error = bus_dma_tag_create( 561 bus_get_dma_tag(sc->aw_dev), /* parent */ 562 AW_MMC_DMA_ALIGN, 0, /* align, boundary */ 563 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 564 BUS_SPACE_MAXADDR, /* highaddr */ 565 NULL, NULL, /* filter, filterarg*/ 566 sc->aw_mmc_conf->dma_xferlen * 567 AW_MMC_DMA_SEGS, AW_MMC_DMA_SEGS, /* maxsize, nsegments */ 568 sc->aw_mmc_conf->dma_xferlen, /* maxsegsize */ 569 BUS_DMA_ALLOCNOW, /* flags */ 570 NULL, NULL, /* lock, lockarg*/ 571 &sc->aw_dma_buf_tag); 572 if (error) 573 return (error); 574 error = bus_dmamap_create(sc->aw_dma_buf_tag, 0, 575 &sc->aw_dma_buf_map); 576 if (error) 577 return (error); 578 579 return (0); 580 } 581 582 static void 583 aw_mmc_teardown_dma(struct aw_mmc_softc *sc) 584 { 585 586 bus_dmamap_unload(sc->aw_dma_tag, sc->aw_dma_map); 587 bus_dmamem_free(sc->aw_dma_tag, sc->aw_dma_desc, sc->aw_dma_map); 588 if (bus_dma_tag_destroy(sc->aw_dma_tag) != 0) 589 device_printf(sc->aw_dev, "Cannot destroy the dma tag\n"); 590 591 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 592 bus_dmamap_destroy(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 593 if (bus_dma_tag_destroy(sc->aw_dma_buf_tag) != 0) 594 device_printf(sc->aw_dev, "Cannot destroy the dma buf tag\n"); 595 } 596 597 static void 598 aw_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) 599 { 600 int i; 601 struct aw_mmc_dma_desc *dma_desc; 602 struct aw_mmc_softc *sc; 603 604 sc = (struct aw_mmc_softc *)arg; 605 sc->aw_dma_map_err = err; 606 607 if (err) 608 return; 609 610 dma_desc = sc->aw_dma_desc; 611 for (i = 0; i < nsegs; i++) { 612 if (segs[i].ds_len == sc->aw_mmc_conf->dma_xferlen) 613 dma_desc[i].buf_size = 0; /* Size of 0 indicate max len */ 614 else 615 dma_desc[i].buf_size = segs[i].ds_len; 616 dma_desc[i].buf_addr = segs[i].ds_addr; 617 dma_desc[i].config = AW_MMC_DMA_CONFIG_CH | 618 AW_MMC_DMA_CONFIG_OWN | AW_MMC_DMA_CONFIG_DIC; 619 620 dma_desc[i].next = sc->aw_dma_desc_phys + 621 ((i + 1) * sizeof(struct aw_mmc_dma_desc)); 622 } 623 624 dma_desc[0].config |= AW_MMC_DMA_CONFIG_FD; 625 dma_desc[nsegs - 1].config |= AW_MMC_DMA_CONFIG_LD | 626 AW_MMC_DMA_CONFIG_ER; 627 dma_desc[nsegs - 1].config &= ~AW_MMC_DMA_CONFIG_DIC; 628 dma_desc[nsegs - 1].next = 0; 629 } 630 631 static int 632 aw_mmc_prepare_dma(struct aw_mmc_softc *sc) 633 { 634 bus_dmasync_op_t sync_op; 635 int error; 636 struct mmc_command *cmd; 637 uint32_t val; 638 639 #ifdef MMCCAM 640 cmd = &sc->ccb->mmcio.cmd; 641 #else 642 cmd = sc->aw_req->cmd; 643 #endif 644 if (cmd->data->len > (sc->aw_mmc_conf->dma_xferlen * AW_MMC_DMA_SEGS)) 645 return (EFBIG); 646 error = bus_dmamap_load(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 647 cmd->data->data, cmd->data->len, aw_dma_cb, sc, 0); 648 if (error) 649 return (error); 650 if (sc->aw_dma_map_err) 651 return (sc->aw_dma_map_err); 652 653 if (cmd->data->flags & MMC_DATA_WRITE) 654 sync_op = BUS_DMASYNC_PREWRITE; 655 else 656 sync_op = BUS_DMASYNC_PREREAD; 657 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, sync_op); 658 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, BUS_DMASYNC_PREWRITE); 659 660 /* Enable DMA */ 661 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 662 val &= ~AW_MMC_GCTL_FIFO_AC_MOD; 663 val |= AW_MMC_GCTL_DMA_ENB; 664 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 665 666 /* Reset DMA */ 667 val |= AW_MMC_GCTL_DMA_RST; 668 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val); 669 670 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, AW_MMC_DMAC_IDMAC_SOFT_RST); 671 AW_MMC_WRITE_4(sc, AW_MMC_DMAC, 672 AW_MMC_DMAC_IDMAC_IDMA_ON | AW_MMC_DMAC_IDMAC_FIX_BURST); 673 674 /* Enable RX or TX DMA interrupt */ 675 val = AW_MMC_READ_4(sc, AW_MMC_IDIE); 676 if (cmd->data->flags & MMC_DATA_WRITE) 677 val |= AW_MMC_IDST_TX_INT; 678 else 679 val |= AW_MMC_IDST_RX_INT; 680 AW_MMC_WRITE_4(sc, AW_MMC_IDIE, val); 681 682 /* Set DMA descritptor list address */ 683 AW_MMC_WRITE_4(sc, AW_MMC_DLBA, sc->aw_dma_desc_phys); 684 685 /* FIFO trigger level */ 686 AW_MMC_WRITE_4(sc, AW_MMC_FWLR, AW_MMC_DMA_FTRGLEVEL); 687 688 return (0); 689 } 690 691 static int 692 aw_mmc_reset(struct aw_mmc_softc *sc) 693 { 694 uint32_t reg; 695 int timeout; 696 697 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 698 reg |= AW_MMC_GCTL_RESET; 699 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 700 timeout = AW_MMC_RESET_RETRY; 701 while (--timeout > 0) { 702 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & AW_MMC_GCTL_RESET) == 0) 703 break; 704 DELAY(100); 705 } 706 if (timeout == 0) 707 return (ETIMEDOUT); 708 709 return (0); 710 } 711 712 static int 713 aw_mmc_init(struct aw_mmc_softc *sc) 714 { 715 uint32_t reg; 716 int ret; 717 718 ret = aw_mmc_reset(sc); 719 if (ret != 0) 720 return (ret); 721 722 /* Set the timeout. */ 723 AW_MMC_WRITE_4(sc, AW_MMC_TMOR, 724 AW_MMC_TMOR_DTO_LMT_SHIFT(AW_MMC_TMOR_DTO_LMT_MASK) | 725 AW_MMC_TMOR_RTO_LMT_SHIFT(AW_MMC_TMOR_RTO_LMT_MASK)); 726 727 /* Unmask interrupts. */ 728 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, 0); 729 730 /* Clear pending interrupts. */ 731 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 732 733 /* Debug register, undocumented */ 734 AW_MMC_WRITE_4(sc, AW_MMC_DBGC, 0xdeb); 735 736 /* Function select register */ 737 AW_MMC_WRITE_4(sc, AW_MMC_FUNS, 0xceaa0000); 738 739 AW_MMC_WRITE_4(sc, AW_MMC_IDST, 0xffffffff); 740 741 /* Enable interrupts and disable AHB access. */ 742 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 743 reg |= AW_MMC_GCTL_INT_ENB; 744 reg &= ~AW_MMC_GCTL_FIFO_AC_MOD; 745 reg &= ~AW_MMC_GCTL_WAIT_MEM_ACCESS; 746 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 747 748 return (0); 749 } 750 751 static void 752 aw_mmc_req_done(struct aw_mmc_softc *sc) 753 { 754 struct mmc_command *cmd; 755 #ifdef MMCCAM 756 union ccb *ccb; 757 #else 758 struct mmc_request *req; 759 #endif 760 uint32_t val, mask; 761 int retry; 762 763 #ifdef MMCCAM 764 ccb = sc->ccb; 765 cmd = &ccb->mmcio.cmd; 766 #else 767 cmd = sc->aw_req->cmd; 768 #endif 769 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) { 770 device_printf(sc->aw_dev, "%s: cmd %d err %d\n", __func__, cmd->opcode, cmd->error); 771 } 772 if (cmd->error != MMC_ERR_NONE) { 773 /* Reset the FIFO and DMA engines. */ 774 mask = AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST; 775 val = AW_MMC_READ_4(sc, AW_MMC_GCTL); 776 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, val | mask); 777 778 retry = AW_MMC_RESET_RETRY; 779 while (--retry > 0) { 780 if ((AW_MMC_READ_4(sc, AW_MMC_GCTL) & 781 AW_MMC_GCTL_RESET) == 0) 782 break; 783 DELAY(100); 784 } 785 if (retry == 0) 786 device_printf(sc->aw_dev, 787 "timeout resetting DMA/FIFO\n"); 788 aw_mmc_update_clock(sc, 1); 789 } 790 791 callout_stop(&sc->aw_timeoutc); 792 sc->aw_intr = 0; 793 sc->aw_resid = 0; 794 sc->aw_dma_map_err = 0; 795 sc->aw_intr_wait = 0; 796 #ifdef MMCCAM 797 sc->ccb = NULL; 798 ccb->ccb_h.status = 799 (ccb->mmcio.cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 800 xpt_done(ccb); 801 #else 802 req = sc->aw_req; 803 sc->aw_req = NULL; 804 req->done(req); 805 #endif 806 } 807 808 static void 809 aw_mmc_req_ok(struct aw_mmc_softc *sc) 810 { 811 int timeout; 812 struct mmc_command *cmd; 813 uint32_t status; 814 815 timeout = 1000; 816 while (--timeout > 0) { 817 status = AW_MMC_READ_4(sc, AW_MMC_STAR); 818 if ((status & AW_MMC_STAR_CARD_BUSY) == 0) 819 break; 820 DELAY(1000); 821 } 822 #ifdef MMCCAM 823 cmd = &sc->ccb->mmcio.cmd; 824 #else 825 cmd = sc->aw_req->cmd; 826 #endif 827 if (timeout == 0) { 828 cmd->error = MMC_ERR_FAILED; 829 aw_mmc_req_done(sc); 830 return; 831 } 832 if (cmd->flags & MMC_RSP_PRESENT) { 833 if (cmd->flags & MMC_RSP_136) { 834 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP3); 835 cmd->resp[1] = AW_MMC_READ_4(sc, AW_MMC_RESP2); 836 cmd->resp[2] = AW_MMC_READ_4(sc, AW_MMC_RESP1); 837 cmd->resp[3] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 838 } else 839 cmd->resp[0] = AW_MMC_READ_4(sc, AW_MMC_RESP0); 840 } 841 /* All data has been transferred ? */ 842 if (cmd->data != NULL && (sc->aw_resid << 2) < cmd->data->len) 843 cmd->error = MMC_ERR_FAILED; 844 aw_mmc_req_done(sc); 845 } 846 847 static inline void 848 set_mmc_error(struct aw_mmc_softc *sc, int error_code) 849 { 850 #ifdef MMCCAM 851 sc->ccb->mmcio.cmd.error = error_code; 852 #else 853 sc->aw_req->cmd->error = error_code; 854 #endif 855 } 856 857 static void 858 aw_mmc_timeout(void *arg) 859 { 860 struct aw_mmc_softc *sc; 861 862 sc = (struct aw_mmc_softc *)arg; 863 #ifdef MMCCAM 864 if (sc->ccb != NULL) { 865 #else 866 if (sc->aw_req != NULL) { 867 #endif 868 device_printf(sc->aw_dev, "controller timeout\n"); 869 set_mmc_error(sc, MMC_ERR_TIMEOUT); 870 aw_mmc_req_done(sc); 871 } else 872 device_printf(sc->aw_dev, 873 "Spurious timeout - no active request\n"); 874 } 875 876 static void 877 aw_mmc_print_error(uint32_t err) 878 { 879 if(err & AW_MMC_INT_RESP_ERR) 880 printf("AW_MMC_INT_RESP_ERR "); 881 if (err & AW_MMC_INT_RESP_CRC_ERR) 882 printf("AW_MMC_INT_RESP_CRC_ERR "); 883 if (err & AW_MMC_INT_DATA_CRC_ERR) 884 printf("AW_MMC_INT_DATA_CRC_ERR "); 885 if (err & AW_MMC_INT_RESP_TIMEOUT) 886 printf("AW_MMC_INT_RESP_TIMEOUT "); 887 if (err & AW_MMC_INT_FIFO_RUN_ERR) 888 printf("AW_MMC_INT_FIFO_RUN_ERR "); 889 if (err & AW_MMC_INT_CMD_BUSY) 890 printf("AW_MMC_INT_CMD_BUSY "); 891 if (err & AW_MMC_INT_DATA_START_ERR) 892 printf("AW_MMC_INT_DATA_START_ERR "); 893 if (err & AW_MMC_INT_DATA_END_BIT_ERR) 894 printf("AW_MMC_INT_DATA_END_BIT_ERR"); 895 printf("\n"); 896 } 897 898 static void 899 aw_mmc_intr(void *arg) 900 { 901 bus_dmasync_op_t sync_op; 902 struct aw_mmc_softc *sc; 903 struct mmc_data *data; 904 uint32_t idst, imask, rint; 905 906 sc = (struct aw_mmc_softc *)arg; 907 AW_MMC_LOCK(sc); 908 rint = AW_MMC_READ_4(sc, AW_MMC_RISR); 909 idst = AW_MMC_READ_4(sc, AW_MMC_IDST); 910 imask = AW_MMC_READ_4(sc, AW_MMC_IMKR); 911 if (idst == 0 && imask == 0 && rint == 0) { 912 AW_MMC_UNLOCK(sc); 913 return; 914 } 915 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT)) { 916 device_printf(sc->aw_dev, "idst: %#x, imask: %#x, rint: %#x\n", 917 idst, imask, rint); 918 } 919 #ifdef MMCCAM 920 if (sc->ccb == NULL) { 921 #else 922 if (sc->aw_req == NULL) { 923 #endif 924 device_printf(sc->aw_dev, 925 "Spurious interrupt - no active request, rint: 0x%08X\n", 926 rint); 927 aw_mmc_print_error(rint); 928 goto end; 929 } 930 if (rint & AW_MMC_INT_ERR_BIT) { 931 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT)) { 932 device_printf(sc->aw_dev, "error rint: 0x%08X\n", rint); 933 aw_mmc_print_error(rint); 934 } 935 if (rint & AW_MMC_INT_RESP_TIMEOUT) 936 set_mmc_error(sc, MMC_ERR_TIMEOUT); 937 else 938 set_mmc_error(sc, MMC_ERR_FAILED); 939 aw_mmc_req_done(sc); 940 goto end; 941 } 942 if (idst & AW_MMC_IDST_ERROR) { 943 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_INT)) 944 device_printf(sc->aw_dev, "error idst: 0x%08x\n", idst); 945 set_mmc_error(sc, MMC_ERR_FAILED); 946 aw_mmc_req_done(sc); 947 goto end; 948 } 949 950 sc->aw_intr |= rint; 951 #ifdef MMCCAM 952 data = sc->ccb->mmcio.cmd.data; 953 #else 954 data = sc->aw_req->cmd->data; 955 #endif 956 if (data != NULL && (idst & AW_MMC_IDST_COMPLETE) != 0) { 957 if (data->flags & MMC_DATA_WRITE) 958 sync_op = BUS_DMASYNC_POSTWRITE; 959 else 960 sync_op = BUS_DMASYNC_POSTREAD; 961 bus_dmamap_sync(sc->aw_dma_buf_tag, sc->aw_dma_buf_map, 962 sync_op); 963 bus_dmamap_sync(sc->aw_dma_tag, sc->aw_dma_map, 964 BUS_DMASYNC_POSTWRITE); 965 bus_dmamap_unload(sc->aw_dma_buf_tag, sc->aw_dma_buf_map); 966 sc->aw_resid = data->len >> 2; 967 } 968 if ((sc->aw_intr & sc->aw_intr_wait) == sc->aw_intr_wait) 969 aw_mmc_req_ok(sc); 970 971 end: 972 AW_MMC_WRITE_4(sc, AW_MMC_IDST, idst); 973 AW_MMC_WRITE_4(sc, AW_MMC_RISR, rint); 974 AW_MMC_UNLOCK(sc); 975 } 976 977 static int 978 aw_mmc_request(device_t bus, device_t child, struct mmc_request *req) 979 { 980 int blksz; 981 struct aw_mmc_softc *sc; 982 struct mmc_command *cmd; 983 uint32_t cmdreg, imask; 984 int err; 985 986 sc = device_get_softc(bus); 987 988 AW_MMC_LOCK(sc); 989 #ifdef MMCCAM 990 KASSERT(req == NULL, ("req should be NULL in MMCCAM case!")); 991 /* 992 * For MMCCAM, sc->ccb has been NULL-checked and populated 993 * by aw_mmc_cam_request() already. 994 */ 995 cmd = &sc->ccb->mmcio.cmd; 996 #else 997 if (sc->aw_req) { 998 AW_MMC_UNLOCK(sc); 999 return (EBUSY); 1000 } 1001 sc->aw_req = req; 1002 cmd = req->cmd; 1003 1004 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CMD)) { 1005 device_printf(sc->aw_dev, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", 1006 cmd->opcode, cmd->arg, cmd->flags, 1007 cmd->data != NULL ? (unsigned int)cmd->data->len : 0, 1008 cmd->data != NULL ? cmd->data->flags: 0); 1009 } 1010 #endif 1011 cmdreg = AW_MMC_CMDR_LOAD; 1012 imask = AW_MMC_INT_ERR_BIT; 1013 sc->aw_intr_wait = 0; 1014 sc->aw_intr = 0; 1015 sc->aw_resid = 0; 1016 cmd->error = MMC_ERR_NONE; 1017 1018 if (cmd->opcode == MMC_GO_IDLE_STATE) 1019 cmdreg |= AW_MMC_CMDR_SEND_INIT_SEQ; 1020 1021 if (cmd->flags & MMC_RSP_PRESENT) 1022 cmdreg |= AW_MMC_CMDR_RESP_RCV; 1023 if (cmd->flags & MMC_RSP_136) 1024 cmdreg |= AW_MMC_CMDR_LONG_RESP; 1025 if (cmd->flags & MMC_RSP_CRC) 1026 cmdreg |= AW_MMC_CMDR_CHK_RESP_CRC; 1027 1028 if (cmd->data) { 1029 cmdreg |= AW_MMC_CMDR_DATA_TRANS | AW_MMC_CMDR_WAIT_PRE_OVER; 1030 1031 if (cmd->data->flags & MMC_DATA_MULTI) { 1032 cmdreg |= AW_MMC_CMDR_STOP_CMD_FLAG; 1033 imask |= AW_MMC_INT_AUTO_STOP_DONE; 1034 sc->aw_intr_wait |= AW_MMC_INT_AUTO_STOP_DONE; 1035 } else { 1036 sc->aw_intr_wait |= AW_MMC_INT_DATA_OVER; 1037 imask |= AW_MMC_INT_DATA_OVER; 1038 } 1039 if (cmd->data->flags & MMC_DATA_WRITE) 1040 cmdreg |= AW_MMC_CMDR_DIR_WRITE; 1041 #ifdef MMCCAM 1042 if (cmd->data->flags & MMC_DATA_BLOCK_SIZE) { 1043 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, cmd->data->block_size); 1044 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 1045 } else 1046 #endif 1047 { 1048 blksz = min(cmd->data->len, MMC_SECTOR_SIZE); 1049 AW_MMC_WRITE_4(sc, AW_MMC_BKSR, blksz); 1050 AW_MMC_WRITE_4(sc, AW_MMC_BYCR, cmd->data->len); 1051 } 1052 } else { 1053 imask |= AW_MMC_INT_CMD_DONE; 1054 } 1055 1056 /* Enable the interrupts we are interested in */ 1057 AW_MMC_WRITE_4(sc, AW_MMC_IMKR, imask); 1058 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1059 1060 /* Enable auto stop if needed */ 1061 AW_MMC_WRITE_4(sc, AW_MMC_A12A, 1062 cmdreg & AW_MMC_CMDR_STOP_CMD_FLAG ? 0 : 0xffff); 1063 1064 /* Write the command argument */ 1065 AW_MMC_WRITE_4(sc, AW_MMC_CAGR, cmd->arg); 1066 1067 /* 1068 * If we don't have data start the request 1069 * if we do prepare the dma request and start the request 1070 */ 1071 if (cmd->data == NULL) { 1072 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1073 } else { 1074 err = aw_mmc_prepare_dma(sc); 1075 if (err != 0) 1076 device_printf(sc->aw_dev, "prepare_dma failed: %d\n", err); 1077 1078 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, cmdreg | cmd->opcode); 1079 } 1080 1081 callout_reset(&sc->aw_timeoutc, sc->aw_timeout * hz, 1082 aw_mmc_timeout, sc); 1083 AW_MMC_UNLOCK(sc); 1084 1085 return (0); 1086 } 1087 1088 static int 1089 aw_mmc_read_ivar(device_t bus, device_t child, int which, 1090 uintptr_t *result) 1091 { 1092 struct aw_mmc_softc *sc; 1093 1094 sc = device_get_softc(bus); 1095 switch (which) { 1096 default: 1097 return (EINVAL); 1098 case MMCBR_IVAR_BUS_MODE: 1099 *(int *)result = sc->aw_host.ios.bus_mode; 1100 break; 1101 case MMCBR_IVAR_BUS_WIDTH: 1102 *(int *)result = sc->aw_host.ios.bus_width; 1103 break; 1104 case MMCBR_IVAR_CHIP_SELECT: 1105 *(int *)result = sc->aw_host.ios.chip_select; 1106 break; 1107 case MMCBR_IVAR_CLOCK: 1108 *(int *)result = sc->aw_host.ios.clock; 1109 break; 1110 case MMCBR_IVAR_F_MIN: 1111 *(int *)result = sc->aw_host.f_min; 1112 break; 1113 case MMCBR_IVAR_F_MAX: 1114 *(int *)result = sc->aw_host.f_max; 1115 break; 1116 case MMCBR_IVAR_HOST_OCR: 1117 *(int *)result = sc->aw_host.host_ocr; 1118 break; 1119 case MMCBR_IVAR_MODE: 1120 *(int *)result = sc->aw_host.mode; 1121 break; 1122 case MMCBR_IVAR_OCR: 1123 *(int *)result = sc->aw_host.ocr; 1124 break; 1125 case MMCBR_IVAR_POWER_MODE: 1126 *(int *)result = sc->aw_host.ios.power_mode; 1127 break; 1128 case MMCBR_IVAR_VDD: 1129 *(int *)result = sc->aw_host.ios.vdd; 1130 break; 1131 case MMCBR_IVAR_VCCQ: 1132 *(int *)result = sc->aw_host.ios.vccq; 1133 break; 1134 case MMCBR_IVAR_CAPS: 1135 *(int *)result = sc->aw_host.caps; 1136 break; 1137 case MMCBR_IVAR_TIMING: 1138 *(int *)result = sc->aw_host.ios.timing; 1139 break; 1140 case MMCBR_IVAR_MAX_DATA: 1141 *(int *)result = (sc->aw_mmc_conf->dma_xferlen * 1142 AW_MMC_DMA_SEGS) / MMC_SECTOR_SIZE; 1143 break; 1144 case MMCBR_IVAR_RETUNE_REQ: 1145 *(int *)result = retune_req_none; 1146 break; 1147 } 1148 1149 return (0); 1150 } 1151 1152 static int 1153 aw_mmc_write_ivar(device_t bus, device_t child, int which, 1154 uintptr_t value) 1155 { 1156 struct aw_mmc_softc *sc; 1157 1158 sc = device_get_softc(bus); 1159 switch (which) { 1160 default: 1161 return (EINVAL); 1162 case MMCBR_IVAR_BUS_MODE: 1163 sc->aw_host.ios.bus_mode = value; 1164 break; 1165 case MMCBR_IVAR_BUS_WIDTH: 1166 sc->aw_host.ios.bus_width = value; 1167 break; 1168 case MMCBR_IVAR_CHIP_SELECT: 1169 sc->aw_host.ios.chip_select = value; 1170 break; 1171 case MMCBR_IVAR_CLOCK: 1172 sc->aw_host.ios.clock = value; 1173 break; 1174 case MMCBR_IVAR_MODE: 1175 sc->aw_host.mode = value; 1176 break; 1177 case MMCBR_IVAR_OCR: 1178 sc->aw_host.ocr = value; 1179 break; 1180 case MMCBR_IVAR_POWER_MODE: 1181 sc->aw_host.ios.power_mode = value; 1182 break; 1183 case MMCBR_IVAR_VDD: 1184 sc->aw_host.ios.vdd = value; 1185 break; 1186 case MMCBR_IVAR_VCCQ: 1187 sc->aw_host.ios.vccq = value; 1188 break; 1189 case MMCBR_IVAR_TIMING: 1190 sc->aw_host.ios.timing = value; 1191 break; 1192 /* These are read-only */ 1193 case MMCBR_IVAR_CAPS: 1194 case MMCBR_IVAR_HOST_OCR: 1195 case MMCBR_IVAR_F_MIN: 1196 case MMCBR_IVAR_F_MAX: 1197 case MMCBR_IVAR_MAX_DATA: 1198 return (EINVAL); 1199 } 1200 1201 return (0); 1202 } 1203 1204 static int 1205 aw_mmc_update_clock(struct aw_mmc_softc *sc, uint32_t clkon) 1206 { 1207 uint32_t reg; 1208 int retry; 1209 1210 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1211 reg &= ~(AW_MMC_CKCR_ENB | AW_MMC_CKCR_LOW_POWER | 1212 AW_MMC_CKCR_MASK_DATA0); 1213 1214 if (clkon) 1215 reg |= AW_MMC_CKCR_ENB; 1216 if (sc->aw_mmc_conf->mask_data0) 1217 reg |= AW_MMC_CKCR_MASK_DATA0; 1218 1219 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1220 1221 reg = AW_MMC_CMDR_LOAD | AW_MMC_CMDR_PRG_CLK | 1222 AW_MMC_CMDR_WAIT_PRE_OVER; 1223 AW_MMC_WRITE_4(sc, AW_MMC_CMDR, reg); 1224 retry = 0xfffff; 1225 1226 while (reg & AW_MMC_CMDR_LOAD && --retry > 0) { 1227 reg = AW_MMC_READ_4(sc, AW_MMC_CMDR); 1228 DELAY(10); 1229 } 1230 AW_MMC_WRITE_4(sc, AW_MMC_RISR, 0xffffffff); 1231 1232 if (reg & AW_MMC_CMDR_LOAD) { 1233 device_printf(sc->aw_dev, "timeout updating clock\n"); 1234 return (ETIMEDOUT); 1235 } 1236 1237 if (sc->aw_mmc_conf->mask_data0) { 1238 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1239 reg &= ~AW_MMC_CKCR_MASK_DATA0; 1240 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1241 } 1242 1243 return (0); 1244 } 1245 1246 #ifndef MMCCAM 1247 static int 1248 aw_mmc_switch_vccq(device_t bus, device_t child) 1249 { 1250 struct aw_mmc_softc *sc; 1251 int uvolt, err; 1252 1253 sc = device_get_softc(bus); 1254 1255 if (sc->mmc_helper.vqmmc_supply == NULL) 1256 return EOPNOTSUPP; 1257 1258 switch (sc->aw_host.ios.vccq) { 1259 case vccq_180: 1260 uvolt = 1800000; 1261 break; 1262 case vccq_330: 1263 uvolt = 3300000; 1264 break; 1265 default: 1266 return EINVAL; 1267 } 1268 1269 err = regulator_set_voltage(sc->mmc_helper.vqmmc_supply, uvolt, uvolt); 1270 if (err != 0) { 1271 device_printf(sc->aw_dev, 1272 "Cannot set vqmmc to %d<->%d\n", 1273 uvolt, 1274 uvolt); 1275 return (err); 1276 } 1277 1278 return (0); 1279 } 1280 #endif 1281 1282 static int 1283 aw_mmc_update_ios(device_t bus, device_t child) 1284 { 1285 int error; 1286 struct aw_mmc_softc *sc; 1287 struct mmc_ios *ios; 1288 unsigned int clock; 1289 uint32_t reg, div = 1; 1290 int reg_status; 1291 int rv; 1292 1293 sc = device_get_softc(bus); 1294 1295 ios = &sc->aw_host.ios; 1296 1297 /* Set the bus width. */ 1298 switch (ios->bus_width) { 1299 case bus_width_1: 1300 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR1); 1301 break; 1302 case bus_width_4: 1303 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR4); 1304 break; 1305 case bus_width_8: 1306 AW_MMC_WRITE_4(sc, AW_MMC_BWDR, AW_MMC_BWDR8); 1307 break; 1308 } 1309 1310 switch (ios->power_mode) { 1311 case power_on: 1312 break; 1313 case power_off: 1314 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD)) 1315 device_printf(sc->aw_dev, "Powering down sd/mmc\n"); 1316 1317 if (sc->mmc_helper.vmmc_supply) { 1318 rv = regulator_status(sc->mmc_helper.vmmc_supply, ®_status); 1319 if (rv == 0 && reg_status == REGULATOR_STATUS_ENABLED) 1320 regulator_disable(sc->mmc_helper.vmmc_supply); 1321 } 1322 if (sc->mmc_helper.vqmmc_supply) { 1323 rv = regulator_status(sc->mmc_helper.vqmmc_supply, ®_status); 1324 if (rv == 0 && reg_status == REGULATOR_STATUS_ENABLED) 1325 regulator_disable(sc->mmc_helper.vqmmc_supply); 1326 } 1327 1328 if (sc->mmc_helper.mmc_pwrseq) 1329 MMC_PWRSEQ_SET_POWER(sc->mmc_helper.mmc_pwrseq, false); 1330 1331 aw_mmc_reset(sc); 1332 break; 1333 case power_up: 1334 if (__predict_false(aw_mmc_debug & AW_MMC_DEBUG_CARD)) 1335 device_printf(sc->aw_dev, "Powering up sd/mmc\n"); 1336 1337 if (sc->mmc_helper.vmmc_supply) { 1338 rv = regulator_status(sc->mmc_helper.vmmc_supply, ®_status); 1339 if (rv == 0 && reg_status != REGULATOR_STATUS_ENABLED) 1340 regulator_enable(sc->mmc_helper.vmmc_supply); 1341 } 1342 if (sc->mmc_helper.vqmmc_supply) { 1343 rv = regulator_status(sc->mmc_helper.vqmmc_supply, ®_status); 1344 if (rv == 0 && reg_status != REGULATOR_STATUS_ENABLED) 1345 regulator_enable(sc->mmc_helper.vqmmc_supply); 1346 } 1347 1348 if (sc->mmc_helper.mmc_pwrseq) 1349 MMC_PWRSEQ_SET_POWER(sc->mmc_helper.mmc_pwrseq, true); 1350 aw_mmc_init(sc); 1351 break; 1352 }; 1353 1354 /* Enable ddr mode if needed */ 1355 reg = AW_MMC_READ_4(sc, AW_MMC_GCTL); 1356 if (ios->timing == bus_timing_uhs_ddr50 || 1357 ios->timing == bus_timing_mmc_ddr52) 1358 reg |= AW_MMC_GCTL_DDR_MOD_SEL; 1359 else 1360 reg &= ~AW_MMC_GCTL_DDR_MOD_SEL; 1361 AW_MMC_WRITE_4(sc, AW_MMC_GCTL, reg); 1362 1363 if (ios->clock && ios->clock != sc->aw_clock) { 1364 sc->aw_clock = clock = ios->clock; 1365 1366 /* Disable clock */ 1367 error = aw_mmc_update_clock(sc, 0); 1368 if (error != 0) 1369 return (error); 1370 1371 if (ios->timing == bus_timing_mmc_ddr52 && 1372 (sc->aw_mmc_conf->new_timing || 1373 ios->bus_width == bus_width_8)) { 1374 div = 2; 1375 clock <<= 1; 1376 } 1377 1378 /* Reset the divider. */ 1379 reg = AW_MMC_READ_4(sc, AW_MMC_CKCR); 1380 reg &= ~AW_MMC_CKCR_DIV; 1381 reg |= div - 1; 1382 AW_MMC_WRITE_4(sc, AW_MMC_CKCR, reg); 1383 1384 /* New timing mode if needed */ 1385 if (sc->aw_mmc_conf->new_timing) { 1386 reg = AW_MMC_READ_4(sc, AW_MMC_NTSR); 1387 reg |= AW_MMC_NTSR_MODE_SELECT; 1388 AW_MMC_WRITE_4(sc, AW_MMC_NTSR, reg); 1389 } 1390 1391 /* Set the MMC clock. */ 1392 error = clk_disable(sc->aw_clk_mmc); 1393 if (error != 0 && bootverbose) 1394 device_printf(sc->aw_dev, 1395 "failed to disable mmc clock: %d\n", error); 1396 error = clk_set_freq(sc->aw_clk_mmc, clock, 1397 CLK_SET_ROUND_DOWN); 1398 if (error != 0) { 1399 device_printf(sc->aw_dev, 1400 "failed to set frequency to %u Hz: %d\n", 1401 clock, error); 1402 return (error); 1403 } 1404 error = clk_enable(sc->aw_clk_mmc); 1405 if (error != 0 && bootverbose) 1406 device_printf(sc->aw_dev, 1407 "failed to re-enable mmc clock: %d\n", error); 1408 1409 if (sc->aw_mmc_conf->can_calibrate) 1410 AW_MMC_WRITE_4(sc, AW_MMC_SAMP_DL, AW_MMC_SAMP_DL_SW_EN); 1411 1412 /* Enable clock. */ 1413 error = aw_mmc_update_clock(sc, 1); 1414 if (error != 0) 1415 return (error); 1416 } 1417 1418 return (0); 1419 } 1420 1421 #ifndef MMCCAM 1422 static int 1423 aw_mmc_get_ro(device_t bus, device_t child) 1424 { 1425 struct aw_mmc_softc *sc; 1426 1427 sc = device_get_softc(bus); 1428 1429 return (mmc_fdt_gpio_get_readonly(&sc->mmc_helper)); 1430 } 1431 1432 static int 1433 aw_mmc_acquire_host(device_t bus, device_t child) 1434 { 1435 struct aw_mmc_softc *sc; 1436 int error; 1437 1438 sc = device_get_softc(bus); 1439 AW_MMC_LOCK(sc); 1440 while (sc->aw_bus_busy) { 1441 error = msleep(sc, &sc->aw_mtx, PCATCH, "mmchw", 0); 1442 if (error != 0) { 1443 AW_MMC_UNLOCK(sc); 1444 return (error); 1445 } 1446 } 1447 sc->aw_bus_busy++; 1448 AW_MMC_UNLOCK(sc); 1449 1450 return (0); 1451 } 1452 1453 static int 1454 aw_mmc_release_host(device_t bus, device_t child) 1455 { 1456 struct aw_mmc_softc *sc; 1457 1458 sc = device_get_softc(bus); 1459 AW_MMC_LOCK(sc); 1460 sc->aw_bus_busy--; 1461 wakeup(sc); 1462 AW_MMC_UNLOCK(sc); 1463 1464 return (0); 1465 } 1466 #endif 1467 1468 static device_method_t aw_mmc_methods[] = { 1469 /* Device interface */ 1470 DEVMETHOD(device_probe, aw_mmc_probe), 1471 DEVMETHOD(device_attach, aw_mmc_attach), 1472 DEVMETHOD(device_detach, aw_mmc_detach), 1473 1474 /* Bus interface */ 1475 DEVMETHOD(bus_read_ivar, aw_mmc_read_ivar), 1476 DEVMETHOD(bus_write_ivar, aw_mmc_write_ivar), 1477 DEVMETHOD(bus_add_child, bus_generic_add_child), 1478 1479 #ifndef MMCCAM 1480 /* MMC bridge interface */ 1481 DEVMETHOD(mmcbr_update_ios, aw_mmc_update_ios), 1482 DEVMETHOD(mmcbr_request, aw_mmc_request), 1483 DEVMETHOD(mmcbr_get_ro, aw_mmc_get_ro), 1484 DEVMETHOD(mmcbr_switch_vccq, aw_mmc_switch_vccq), 1485 DEVMETHOD(mmcbr_acquire_host, aw_mmc_acquire_host), 1486 DEVMETHOD(mmcbr_release_host, aw_mmc_release_host), 1487 #endif 1488 1489 #ifdef MMCCAM 1490 /* MMCCAM interface */ 1491 DEVMETHOD(mmc_sim_get_tran_settings, aw_mmc_get_tran_settings), 1492 DEVMETHOD(mmc_sim_set_tran_settings, aw_mmc_set_tran_settings), 1493 DEVMETHOD(mmc_sim_cam_request, aw_mmc_cam_request), 1494 #endif 1495 1496 DEVMETHOD_END 1497 }; 1498 1499 static devclass_t aw_mmc_devclass; 1500 1501 static driver_t aw_mmc_driver = { 1502 "aw_mmc", 1503 aw_mmc_methods, 1504 sizeof(struct aw_mmc_softc), 1505 }; 1506 1507 DRIVER_MODULE(aw_mmc, simplebus, aw_mmc_driver, aw_mmc_devclass, NULL, 1508 NULL); 1509 #ifndef MMCCAM 1510 MMC_DECLARE_BRIDGE(aw_mmc); 1511 #endif 1512 SIMPLEBUS_PNP_INFO(compat_data);
Cache object: 093fa17ad823fb8bb93361f70be21b90
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