The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/allwinner/aw_mmc.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
    5  * Copyright (c) 2013 Alexander Fedorov <alexander.fedorov@rtlservice.com>
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  * $FreeBSD$
   30  */
   31 
   32 #ifndef _AW_MMC_H_
   33 #define _AW_MMC_H_
   34 
   35 #define AW_MMC_GCTL             0x00    /* Control Register */
   36 #define AW_MMC_CKCR             0x04    /* Clock Control Register */
   37 #define AW_MMC_TMOR             0x08    /* Timeout Register */
   38 #define AW_MMC_BWDR             0x0C    /* Bus Width Register */
   39 #define AW_MMC_BKSR             0x10    /* Block Size Register */
   40 #define AW_MMC_BYCR             0x14    /* Byte Count Register */
   41 #define AW_MMC_CMDR             0x18    /* Command Register */
   42 #define AW_MMC_CAGR             0x1C    /* Argument Register */
   43 #define AW_MMC_RESP0            0x20    /* Response Register 0 */
   44 #define AW_MMC_RESP1            0x24    /* Response Register 1 */
   45 #define AW_MMC_RESP2            0x28    /* Response Register 2 */
   46 #define AW_MMC_RESP3            0x2C    /* Response Register 3 */
   47 #define AW_MMC_IMKR             0x30    /* Interrupt Mask Register */
   48 #define AW_MMC_MISR             0x34    /* Masked Interrupt Status Register */
   49 #define AW_MMC_RISR             0x38    /* Raw Interrupt Status Register */
   50 #define AW_MMC_STAR             0x3C    /* Status Register */
   51 #define AW_MMC_FWLR             0x40    /* FIFO Threshold Watermark Register */
   52 #define AW_MMC_FUNS             0x44    /* Function Select Register */
   53 #define AW_MMC_DBGC             0x50    /* Debug register */
   54 #define AW_MMC_CSDC             0x54    /* CRC status detect controler register (A64 smhc2 only) */
   55 #define AW_MMC_A12A             0x58    /* Auto command 12 argument register */
   56 #define AW_MMC_NTSR             0x5C    /* SD new timing register (H3, A64 smhc0/1 only) */
   57 #define AW_MMC_HWRST            0x78    /* Hardware reset */
   58 #define AW_MMC_DMAC             0x80    /* IDMAC Control Register */
   59 #define AW_MMC_DLBA             0x84    /* IDMAC Desc List Base Address Reg */
   60 #define AW_MMC_IDST             0x88    /* IDMAC Status Register */
   61 #define AW_MMC_IDIE             0x8C    /* IDMAC Interrupt Enable Register */
   62 
   63 #define AW_MMC_DDR_SBIT_DET     0x10C   /* eMMC4.5 DDR Start Bit Detection control register */
   64 #define AW_MMC_DRV_DL           0x140   /* Drive Delay control register */
   65 #define AW_MMC_SAMP_DL          0x144   /* Sample Delay controle register */
   66 #define AW_MMC_DS_DL            0x148   /* Data strobe delay control register */
   67 
   68 #define AW_MMC_FIFO             0x100   /* FIFO Access Address (A10/A20) */
   69 #define A31_MMC_FIFO            0x200   /* FIFO Access Address (A31) */
   70 
   71 /* AW_MMC_GCTL */
   72 #define AW_MMC_GCTL_SOFT_RST            (1U << 0)
   73 #define AW_MMC_GCTL_FIFO_RST            (1U << 1)
   74 #define AW_MMC_GCTL_DMA_RST             (1U << 2)
   75 #define AW_MMC_GCTL_INT_ENB             (1U << 4)
   76 #define AW_MMC_GCTL_DMA_ENB             (1U << 5)
   77 #define AW_MMC_GCTL_CD_DBC_ENB          (1U << 8)
   78 #define AW_MMC_GCTL_DDR_MOD_SEL         (1U << 10)
   79 #define AW_MMC_GCTL_WAIT_MEM_ACCESS     (1U << 30)
   80 #define AW_MMC_GCTL_FIFO_AC_MOD         (1U << 31)
   81 #define AW_MMC_GCTL_RESET                       \
   82         (AW_MMC_GCTL_SOFT_RST | AW_MMC_GCTL_FIFO_RST | AW_MMC_GCTL_DMA_RST)
   83 
   84 /* AW_MMC_CKCR */
   85 #define AW_MMC_CKCR_DIV         0xff
   86 #define AW_MMC_CKCR_ENB         (1U << 16)
   87 #define AW_MMC_CKCR_LOW_POWER   (1U << 17)
   88 #define AW_MMC_CKCR_MASK_DATA0  (1U << 31)
   89 
   90 /* AW_MMC_TMOR */
   91 #define AW_MMC_TMOR_RTO_LMT_SHIFT(x)    x               /* Response timeout limit */
   92 #define AW_MMC_TMOR_RTO_LMT_MASK        0xff
   93 #define AW_MMC_TMOR_DTO_LMT_SHIFT(x)    (x << 8)        /* Data timeout limit */
   94 #define AW_MMC_TMOR_DTO_LMT_MASK        0xffffff
   95 
   96 /* AW_MMC_BWDR */
   97 #define AW_MMC_BWDR1                    0
   98 #define AW_MMC_BWDR4                    1
   99 #define AW_MMC_BWDR8                    2
  100 
  101 /* AW_MMC_CMDR */
  102 #define AW_MMC_CMDR_RESP_RCV            (1U << 6)
  103 #define AW_MMC_CMDR_LONG_RESP           (1U << 7)
  104 #define AW_MMC_CMDR_CHK_RESP_CRC        (1U << 8)
  105 #define AW_MMC_CMDR_DATA_TRANS          (1U << 9)
  106 #define AW_MMC_CMDR_DIR_WRITE           (1U << 10)
  107 #define AW_MMC_CMDR_TRANS_MODE_STREAM   (1U << 11)
  108 #define AW_MMC_CMDR_STOP_CMD_FLAG       (1U << 12)
  109 #define AW_MMC_CMDR_WAIT_PRE_OVER       (1U << 13)
  110 #define AW_MMC_CMDR_STOP_ABT_CMD        (1U << 14)
  111 #define AW_MMC_CMDR_SEND_INIT_SEQ       (1U << 15)
  112 #define AW_MMC_CMDR_PRG_CLK             (1U << 21)
  113 #define AW_MMC_CMDR_RD_CEDATA_DEV       (1U << 22)
  114 #define AW_MMC_CMDR_CCS_EXP             (1U << 23)
  115 #define AW_MMC_CMDR_BOOT_MOD_SHIFT      24
  116 #define AW_MMC_CMDR_BOOT_MOD_NORMAL     0
  117 #define AW_MMC_CMDR_BOOT_MOD_MANDATORY  1
  118 #define AW_MMC_CMDR_BOOT_MOD_ALT        2
  119 #define AW_MMC_CMDR_EXP_BOOT_ACK        (1U << 26)
  120 #define AW_MMC_CMDR_BOOT_ABT            (1U << 27)
  121 #define AW_MMC_CMDR_VOL_SW              (1U << 28)
  122 #define AW_MMC_CMDR_LOAD                (1U << 31)
  123 
  124 /* AW_MMC_IMKR and AW_MMC_RISR */
  125 #define AW_MMC_INT_RESP_ERR     (1U << 1)
  126 #define AW_MMC_INT_CMD_DONE             (1U << 2)
  127 #define AW_MMC_INT_DATA_OVER            (1U << 3)
  128 #define AW_MMC_INT_TX_DATA_REQ          (1U << 4)
  129 #define AW_MMC_INT_RX_DATA_REQ          (1U << 5)
  130 #define AW_MMC_INT_RESP_CRC_ERR         (1U << 6)
  131 #define AW_MMC_INT_DATA_CRC_ERR         (1U << 7)
  132 #define AW_MMC_INT_RESP_TIMEOUT         (1U << 8)
  133 #define AW_MMC_INT_BOOT_ACK_RECV        (1U << 8)
  134 #define AW_MMC_INT_DATA_TIMEOUT         (1U << 9)
  135 #define AW_MMC_INT_BOOT_START           (1U << 9)
  136 #define AW_MMC_INT_DATA_STARVE          (1U << 10)
  137 #define AW_MMC_INT_VOL_CHG_DONE         (1U << 10)
  138 #define AW_MMC_INT_FIFO_RUN_ERR         (1U << 11)
  139 #define AW_MMC_INT_CMD_BUSY             (1U << 12)
  140 #define AW_MMC_INT_DATA_START_ERR       (1U << 13)
  141 #define AW_MMC_INT_AUTO_STOP_DONE       (1U << 14)
  142 #define AW_MMC_INT_DATA_END_BIT_ERR     (1U << 15)
  143 #define AW_MMC_INT_SDIO                 (1U << 16)
  144 #define AW_MMC_INT_CARD_INSERT          (1U << 30)
  145 #define AW_MMC_INT_CARD_REMOVE          (1U << 31)
  146 #define AW_MMC_INT_ERR_BIT                              \
  147         (AW_MMC_INT_RESP_ERR | AW_MMC_INT_RESP_CRC_ERR |        \
  148          AW_MMC_INT_DATA_CRC_ERR | AW_MMC_INT_RESP_TIMEOUT |    \
  149          AW_MMC_INT_FIFO_RUN_ERR |      AW_MMC_INT_CMD_BUSY |   \
  150          AW_MMC_INT_DATA_START_ERR | AW_MMC_INT_DATA_END_BIT_ERR)
  151 
  152 /* AW_MMC_STAR */
  153 #define AW_MMC_STAR_FIFO_RX_LEVEL       (1U << 0)
  154 #define AW_MMC_STAR_FIFO_TX_LEVEL       (1U << 1)
  155 #define AW_MMC_STAR_FIFO_EMPTY          (1U << 2)
  156 #define AW_MMC_STAR_FIFO_FULL           (1U << 3)
  157 #define AW_MMC_STAR_CARD_PRESENT        (1U << 8)
  158 #define AW_MMC_STAR_CARD_BUSY           (1U << 9)
  159 #define AW_MMC_STAR_FSM_BUSY            (1U << 10)
  160 #define AW_MMC_STAR_DMA_REQ                     (1U << 31)
  161 
  162 /* AW_MMC_FUNS */
  163 #define AW_MMC_CE_ATA_ON                (0xceaaU << 16)
  164 #define AW_MMC_SEND_IRQ_RESP            (1U << 0)
  165 #define AW_MMC_SDIO_RD_WAIT             (1U << 1)
  166 #define AW_MMC_ABT_RD_DATA              (1U << 2)
  167 #define AW_MMC_SEND_CC_SD               (1U << 8)
  168 #define AW_MMC_SEND_AUTOSTOP_CC_SD      (1U << 9)
  169 #define AW_MMC_CE_ATA_DEV_INT_ENB       (1U << 10)
  170 
  171 /* AW_MMC_NTSR */
  172 #define AW_MMC_NTSR_MODE_SELECT         (1U << 31)
  173 
  174 /* IDMA CONTROLLER BUS MOD BIT FIELD */
  175 #define AW_MMC_DMAC_IDMAC_SOFT_RST      (1U << 0)
  176 #define AW_MMC_DMAC_IDMAC_FIX_BURST     (1U << 1)
  177 #define AW_MMC_DMAC_IDMAC_IDMA_ON       (1U << 7)
  178 #define AW_MMC_DMAC_IDMAC_REFETCH_DES   (1U << 31)
  179 
  180 /* AW_MMC_IDST */
  181 #define AW_MMC_IDST_TX_INT              (1U << 0)
  182 #define AW_MMC_IDST_RX_INT              (1U << 1)
  183 #define AW_MMC_IDST_FATAL_BERR_INT      (1U << 2)
  184 #define AW_MMC_IDST_DES_UNAVL_INT       (1U << 4)
  185 #define AW_MMC_IDST_ERR_FLAG_SUM        (1U << 5)
  186 #define AW_MMC_IDST_NOR_INT_SUM         (1U << 8)
  187 #define AW_MMC_IDST_ABN_INT_SUM         (1U << 9)
  188 #define AW_MMC_IDST_HOST_ABT_INTX       (1U << 10)
  189 #define AW_MMC_IDST_HOST_ABT_INRX       (1U << 10)
  190 #define AW_MMC_IDST_IDLE                (0U << 13)
  191 #define AW_MMC_IDST_SUSPEND             (1U << 13)
  192 #define AW_MMC_IDST_DESC_RD             (2U << 13)
  193 #define AW_MMC_IDST_DESC_CHECK          (3U << 13)
  194 #define AW_MMC_IDST_RD_REQ_WAIT         (4U << 13)
  195 #define AW_MMC_IDST_WR_REQ_WAIT         (5U << 13)
  196 #define AW_MMC_IDST_RD                  (6U << 13)
  197 #define AW_MMC_IDST_WR                  (7U << 13)
  198 #define AW_MMC_IDST_DESC_CLOSE          (8U << 13)
  199 #define AW_MMC_IDST_ERROR                               \
  200         (AW_MMC_IDST_FATAL_BERR_INT | AW_MMC_IDST_ERR_FLAG_SUM |        \
  201          AW_MMC_IDST_DES_UNAVL_INT | AW_MMC_IDST_ABN_INT_SUM)
  202 #define AW_MMC_IDST_COMPLETE                            \
  203         (AW_MMC_IDST_TX_INT | AW_MMC_IDST_RX_INT)
  204 
  205 /* AW_MMC_DDR_SBIT_DET */
  206 #define AW_MMC_DDR_SBIT_HS_MD_EN        (1U << 31)
  207 
  208 /* AW_MMC_SAMP */
  209 #define AW_MMC_SAMP_DL_SW_EN            (1U << 7)
  210 
  211 /* The DMA descriptor table. */
  212 struct aw_mmc_dma_desc {
  213         uint32_t config;
  214 #define AW_MMC_DMA_CONFIG_DIC           (1U << 1)       /* Disable Interrupt Completion */
  215 #define AW_MMC_DMA_CONFIG_LD            (1U << 2)       /* Last DES */
  216 #define AW_MMC_DMA_CONFIG_FD            (1U << 3)       /* First DES */
  217 #define AW_MMC_DMA_CONFIG_CH            (1U << 4)       /* CHAIN MOD */
  218 #define AW_MMC_DMA_CONFIG_ER            (1U << 5)       /* End of Ring (undocumented register) */
  219 #define AW_MMC_DMA_CONFIG_CES           (1U << 30)      /* Card Error Summary */
  220 #define AW_MMC_DMA_CONFIG_OWN           (1U << 31)      /* DES Own Flag */
  221         uint32_t buf_size;
  222         uint32_t buf_addr;
  223         uint32_t next;
  224 };
  225 
  226 #define AW_MMC_DMA_ALIGN        4
  227 
  228 #endif /* _AW_MMC_H_ */

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