Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/allwinner/aw_rsb.c
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1 /*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 /* 29 * Allwinner RSB (Reduced Serial Bus) and P2WI (Push-Pull Two Wire Interface) 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/rman.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/module.h> 42 #include <sys/mutex.h> 43 #include <machine/bus.h> 44 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include <dev/iicbus/iiconf.h> 49 #include <dev/iicbus/iicbus.h> 50 51 #include <dev/extres/clk/clk.h> 52 #include <dev/extres/hwreset/hwreset.h> 53 54 #include "iicbus_if.h" 55 56 #define RSB_CTRL 0x00 57 #define START_TRANS (1 << 7) 58 #define GLOBAL_INT_ENB (1 << 1) 59 #define SOFT_RESET (1 << 0) 60 #define RSB_CCR 0x04 61 #define RSB_INTE 0x08 62 #define RSB_INTS 0x0c 63 #define INT_TRANS_ERR_ID(x) (((x) >> 8) & 0xf) 64 #define INT_LOAD_BSY (1 << 2) 65 #define INT_TRANS_ERR (1 << 1) 66 #define INT_TRANS_OVER (1 << 0) 67 #define INT_MASK (INT_LOAD_BSY|INT_TRANS_ERR|INT_TRANS_OVER) 68 #define RSB_DADDR0 0x10 69 #define RSB_DADDR1 0x14 70 #define RSB_DLEN 0x18 71 #define DLEN_READ (1 << 4) 72 #define RSB_DATA0 0x1c 73 #define RSB_DATA1 0x20 74 #define RSB_PMCR 0x28 75 #define RSB_PMCR_START (1 << 31) 76 #define RSB_PMCR_DATA(x) (x << 16) 77 #define RSB_PMCR_REG(x) (x << 8) 78 #define RSB_CMD 0x2c 79 #define CMD_SRTA 0xe8 80 #define CMD_RD8 0x8b 81 #define CMD_RD16 0x9c 82 #define CMD_RD32 0xa6 83 #define CMD_WR8 0x4e 84 #define CMD_WR16 0x59 85 #define CMD_WR32 0x63 86 #define RSB_DAR 0x30 87 #define DAR_RTA (0xff << 16) 88 #define DAR_RTA_SHIFT 16 89 #define DAR_DA (0xffff << 0) 90 #define DAR_DA_SHIFT 0 91 92 #define RSB_MAXLEN 8 93 #define RSB_RESET_RETRY 100 94 #define RSB_I2C_TIMEOUT hz 95 96 #define RSB_ADDR_PMIC_PRIMARY 0x3a3 97 #define RSB_ADDR_PMIC_SECONDARY 0x745 98 #define RSB_ADDR_PERIPH_IC 0xe89 99 100 #define PMIC_MODE_REG 0x3e 101 #define PMIC_MODE_I2C 0x00 102 #define PMIC_MODE_RSB 0x7c 103 104 #define A31_P2WI 1 105 #define A23_RSB 2 106 107 static struct ofw_compat_data compat_data[] = { 108 { "allwinner,sun6i-a31-p2wi", A31_P2WI }, 109 { "allwinner,sun8i-a23-rsb", A23_RSB }, 110 { NULL, 0 } 111 }; 112 113 static struct resource_spec rsb_spec[] = { 114 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 115 { -1, 0 } 116 }; 117 118 /* 119 * Device address to Run-time address mappings. 120 * 121 * Run-time address (RTA) is an 8-bit value used to address the device during 122 * a read or write transaction. The following are valid RTAs: 123 * 0x17 0x2d 0x3a 0x4e 0x59 0x63 0x74 0x8b 0x9c 0xa6 0xb1 0xc5 0xd2 0xe8 0xff 124 * 125 * Allwinner uses RTA 0x2d for the primary PMIC, 0x3a for the secondary PMIC, 126 * and 0x4e for the peripheral IC (where applicable). 127 */ 128 static const struct { 129 uint16_t addr; 130 uint8_t rta; 131 } rsb_rtamap[] = { 132 { .addr = RSB_ADDR_PMIC_PRIMARY, .rta = 0x2d }, 133 { .addr = RSB_ADDR_PMIC_SECONDARY, .rta = 0x3a }, 134 { .addr = RSB_ADDR_PERIPH_IC, .rta = 0x4e }, 135 { .addr = 0, .rta = 0 } 136 }; 137 138 struct rsb_softc { 139 struct resource *res; 140 struct mtx mtx; 141 clk_t clk; 142 hwreset_t rst; 143 device_t iicbus; 144 int busy; 145 uint32_t status; 146 uint16_t cur_addr; 147 int type; 148 149 struct iic_msg *msg; 150 }; 151 152 #define RSB_LOCK(sc) mtx_lock(&(sc)->mtx) 153 #define RSB_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 154 #define RSB_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) 155 #define RSB_READ(sc, reg) bus_read_4((sc)->res, (reg)) 156 #define RSB_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) 157 158 static phandle_t 159 rsb_get_node(device_t bus, device_t dev) 160 { 161 return (ofw_bus_get_node(bus)); 162 } 163 164 static int 165 rsb_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 166 { 167 struct rsb_softc *sc; 168 int retry; 169 170 sc = device_get_softc(dev); 171 172 RSB_LOCK(sc); 173 174 /* Write soft-reset bit and wait for it to self-clear. */ 175 RSB_WRITE(sc, RSB_CTRL, SOFT_RESET); 176 for (retry = RSB_RESET_RETRY; retry > 0; retry--) 177 if ((RSB_READ(sc, RSB_CTRL) & SOFT_RESET) == 0) 178 break; 179 180 RSB_UNLOCK(sc); 181 182 if (retry == 0) { 183 device_printf(dev, "soft reset timeout\n"); 184 return (ETIMEDOUT); 185 } 186 187 return (IIC_ENOADDR); 188 } 189 190 static uint32_t 191 rsb_encode(const uint8_t *buf, u_int len, u_int off) 192 { 193 uint32_t val; 194 u_int n; 195 196 val = 0; 197 for (n = off; n < MIN(len, 4 + off); n++) 198 val |= ((uint32_t)buf[n] << ((n - off) * NBBY)); 199 200 return val; 201 } 202 203 static void 204 rsb_decode(const uint32_t val, uint8_t *buf, u_int len, u_int off) 205 { 206 u_int n; 207 208 for (n = off; n < MIN(len, 4 + off); n++) 209 buf[n] = (val >> ((n - off) * NBBY)) & 0xff; 210 } 211 212 static int 213 rsb_start(device_t dev) 214 { 215 struct rsb_softc *sc; 216 int error, retry; 217 218 sc = device_get_softc(dev); 219 220 RSB_ASSERT_LOCKED(sc); 221 222 /* Start the transfer */ 223 RSB_WRITE(sc, RSB_CTRL, GLOBAL_INT_ENB | START_TRANS); 224 225 /* Wait for transfer to complete */ 226 error = ETIMEDOUT; 227 for (retry = RSB_I2C_TIMEOUT; retry > 0; retry--) { 228 sc->status |= RSB_READ(sc, RSB_INTS); 229 if ((sc->status & INT_TRANS_OVER) != 0) { 230 error = 0; 231 break; 232 } 233 DELAY((1000 * hz) / RSB_I2C_TIMEOUT); 234 } 235 if (error == 0 && (sc->status & INT_TRANS_OVER) == 0) { 236 device_printf(dev, "transfer error, status 0x%08x\n", 237 sc->status); 238 error = EIO; 239 } 240 241 return (error); 242 243 } 244 245 static int 246 rsb_set_rta(device_t dev, uint16_t addr) 247 { 248 struct rsb_softc *sc; 249 uint8_t rta; 250 int i; 251 252 sc = device_get_softc(dev); 253 254 RSB_ASSERT_LOCKED(sc); 255 256 /* Lookup run-time address for given device address */ 257 for (rta = 0, i = 0; rsb_rtamap[i].rta != 0; i++) 258 if (rsb_rtamap[i].addr == addr) { 259 rta = rsb_rtamap[i].rta; 260 break; 261 } 262 if (rta == 0) { 263 device_printf(dev, "RTA not known for address %#x\n", addr); 264 return (ENXIO); 265 } 266 267 /* Set run-time address */ 268 RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS)); 269 RSB_WRITE(sc, RSB_DAR, (addr << DAR_DA_SHIFT) | (rta << DAR_RTA_SHIFT)); 270 RSB_WRITE(sc, RSB_CMD, CMD_SRTA); 271 272 return (rsb_start(dev)); 273 } 274 275 static int 276 rsb_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 277 { 278 struct rsb_softc *sc; 279 uint32_t daddr[2], data[2], dlen; 280 uint16_t device_addr; 281 uint8_t cmd; 282 int error; 283 284 sc = device_get_softc(dev); 285 286 /* 287 * P2WI and RSB are not really I2C or SMBus controllers, so there are 288 * some restrictions imposed by the driver. 289 * 290 * Transfers must contain exactly two messages. The first is always 291 * a write, containing a single data byte offset. Data will either 292 * be read from or written to the corresponding data byte in the 293 * second message. The slave address in both messages must be the 294 * same. 295 */ 296 if (nmsgs != 2 || (msgs[0].flags & IIC_M_RD) == IIC_M_RD || 297 (msgs[0].slave >> 1) != (msgs[1].slave >> 1) || 298 msgs[0].len != 1 || msgs[1].len > RSB_MAXLEN) 299 return (EINVAL); 300 301 /* The RSB controller can read or write 1, 2, or 4 bytes at a time. */ 302 if (sc->type == A23_RSB) { 303 if ((msgs[1].flags & IIC_M_RD) != 0) { 304 switch (msgs[1].len) { 305 case 1: 306 cmd = CMD_RD8; 307 break; 308 case 2: 309 cmd = CMD_RD16; 310 break; 311 case 4: 312 cmd = CMD_RD32; 313 break; 314 default: 315 return (EINVAL); 316 } 317 } else { 318 switch (msgs[1].len) { 319 case 1: 320 cmd = CMD_WR8; 321 break; 322 case 2: 323 cmd = CMD_WR16; 324 break; 325 case 4: 326 cmd = CMD_WR32; 327 break; 328 default: 329 return (EINVAL); 330 } 331 } 332 } 333 334 RSB_LOCK(sc); 335 while (sc->busy) 336 mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0); 337 sc->busy = 1; 338 sc->status = 0; 339 340 /* Select current run-time address if necessary */ 341 if (sc->type == A23_RSB) { 342 device_addr = msgs[0].slave >> 1; 343 if (sc->cur_addr != device_addr) { 344 error = rsb_set_rta(dev, device_addr); 345 if (error != 0) 346 goto done; 347 sc->cur_addr = device_addr; 348 sc->status = 0; 349 } 350 } 351 352 /* Clear interrupt status */ 353 RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS)); 354 355 /* Program data access address registers */ 356 daddr[0] = rsb_encode(msgs[0].buf, msgs[0].len, 0); 357 RSB_WRITE(sc, RSB_DADDR0, daddr[0]); 358 359 /* Write data */ 360 if ((msgs[1].flags & IIC_M_RD) == 0) { 361 data[0] = rsb_encode(msgs[1].buf, msgs[1].len, 0); 362 RSB_WRITE(sc, RSB_DATA0, data[0]); 363 } 364 365 /* Set command type for RSB */ 366 if (sc->type == A23_RSB) 367 RSB_WRITE(sc, RSB_CMD, cmd); 368 369 /* Program data length register and transfer direction */ 370 dlen = msgs[0].len - 1; 371 if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD) 372 dlen |= DLEN_READ; 373 RSB_WRITE(sc, RSB_DLEN, dlen); 374 375 /* Start transfer */ 376 error = rsb_start(dev); 377 if (error != 0) 378 goto done; 379 380 /* Read data */ 381 if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD) { 382 data[0] = RSB_READ(sc, RSB_DATA0); 383 rsb_decode(data[0], msgs[1].buf, msgs[1].len, 0); 384 } 385 386 done: 387 sc->msg = NULL; 388 sc->busy = 0; 389 wakeup(sc); 390 RSB_UNLOCK(sc); 391 392 return (error); 393 } 394 395 static int 396 rsb_probe(device_t dev) 397 { 398 if (!ofw_bus_status_okay(dev)) 399 return (ENXIO); 400 401 switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { 402 case A23_RSB: 403 device_set_desc(dev, "Allwinner RSB"); 404 break; 405 case A31_P2WI: 406 device_set_desc(dev, "Allwinner P2WI"); 407 break; 408 default: 409 return (ENXIO); 410 } 411 412 return (BUS_PROBE_DEFAULT); 413 } 414 415 static int 416 rsb_attach(device_t dev) 417 { 418 struct rsb_softc *sc; 419 int error; 420 421 sc = device_get_softc(dev); 422 mtx_init(&sc->mtx, device_get_nameunit(dev), "rsb", MTX_DEF); 423 424 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 425 426 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) == 0) { 427 error = clk_enable(sc->clk); 428 if (error != 0) { 429 device_printf(dev, "cannot enable clock\n"); 430 goto fail; 431 } 432 } 433 if (hwreset_get_by_ofw_idx(dev, 0, 0, &sc->rst) == 0) { 434 error = hwreset_deassert(sc->rst); 435 if (error != 0) { 436 device_printf(dev, "cannot de-assert reset\n"); 437 goto fail; 438 } 439 } 440 441 if (bus_alloc_resources(dev, rsb_spec, &sc->res) != 0) { 442 device_printf(dev, "cannot allocate resources for device\n"); 443 error = ENXIO; 444 goto fail; 445 } 446 447 /* Set the PMIC into RSB mode as ATF might have leave it in I2C mode */ 448 RSB_WRITE(sc, RSB_PMCR, RSB_PMCR_REG(PMIC_MODE_REG) | RSB_PMCR_DATA(PMIC_MODE_RSB) | RSB_PMCR_START); 449 450 sc->iicbus = device_add_child(dev, "iicbus", -1); 451 if (sc->iicbus == NULL) { 452 device_printf(dev, "cannot add iicbus child device\n"); 453 error = ENXIO; 454 goto fail; 455 } 456 457 bus_generic_attach(dev); 458 459 return (0); 460 461 fail: 462 bus_release_resources(dev, rsb_spec, &sc->res); 463 if (sc->rst != NULL) 464 hwreset_release(sc->rst); 465 if (sc->clk != NULL) 466 clk_release(sc->clk); 467 mtx_destroy(&sc->mtx); 468 return (error); 469 } 470 471 static device_method_t rsb_methods[] = { 472 /* Device interface */ 473 DEVMETHOD(device_probe, rsb_probe), 474 DEVMETHOD(device_attach, rsb_attach), 475 476 /* Bus interface */ 477 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 478 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 479 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 480 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 481 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 482 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 483 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 484 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 485 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 486 487 /* OFW methods */ 488 DEVMETHOD(ofw_bus_get_node, rsb_get_node), 489 490 /* iicbus interface */ 491 DEVMETHOD(iicbus_callback, iicbus_null_callback), 492 DEVMETHOD(iicbus_reset, rsb_reset), 493 DEVMETHOD(iicbus_transfer, rsb_transfer), 494 495 DEVMETHOD_END 496 }; 497 498 static driver_t rsb_driver = { 499 "iichb", 500 rsb_methods, 501 sizeof(struct rsb_softc), 502 }; 503 504 EARLY_DRIVER_MODULE(iicbus, rsb, iicbus_driver, 0, 0, 505 BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE); 506 EARLY_DRIVER_MODULE(rsb, simplebus, rsb_driver, 0, 0, 507 BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE); 508 MODULE_VERSION(rsb, 1); 509 MODULE_DEPEND(rsb, iicbus, 1, 1, 1); 510 SIMPLEBUS_PNP_INFO(compat_data);
Cache object: c33fe96ac425a219e2d773e34b8fb95e
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