1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2019 Emmanuel Vadot <manu@freebsd.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD$
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36
37 #include <dev/extres/clk/clk.h>
38
39 #include <arm/allwinner/clkng/aw_clk.h>
40 #include <arm/allwinner/clkng/aw_clk_nmm.h>
41
42 #include "clkdev_if.h"
43
44 /*
45 * clknode for clocks matching the formula :
46 *
47 * clk = clkin * n / m0 / m1
48 *
49 */
50
51 struct aw_clk_nmm_sc {
52 uint32_t offset;
53
54 struct aw_clk_factor n;
55 struct aw_clk_factor m0;
56 struct aw_clk_factor m1;
57
58 uint32_t gate_shift;
59 uint32_t lock_shift;
60 uint32_t lock_retries;
61
62 uint32_t flags;
63 };
64
65 #define WRITE4(_clk, off, val) \
66 CLKDEV_WRITE_4(clknode_get_device(_clk), off, val)
67 #define READ4(_clk, off, val) \
68 CLKDEV_READ_4(clknode_get_device(_clk), off, val)
69 #define DEVICE_LOCK(_clk) \
70 CLKDEV_DEVICE_LOCK(clknode_get_device(_clk))
71 #define DEVICE_UNLOCK(_clk) \
72 CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk))
73
74 static int
75 aw_clk_nmm_init(struct clknode *clk, device_t dev)
76 {
77
78 clknode_init_parent_idx(clk, 0);
79 return (0);
80 }
81
82 static int
83 aw_clk_nmm_set_gate(struct clknode *clk, bool enable)
84 {
85 struct aw_clk_nmm_sc *sc;
86 uint32_t val;
87
88 sc = clknode_get_softc(clk);
89
90 if ((sc->flags & AW_CLK_HAS_GATE) == 0)
91 return (0);
92
93 DEVICE_LOCK(clk);
94 READ4(clk, sc->offset, &val);
95 if (enable)
96 val |= (1 << sc->gate_shift);
97 else
98 val &= ~(1 << sc->gate_shift);
99 WRITE4(clk, sc->offset, val);
100 DEVICE_UNLOCK(clk);
101
102 return (0);
103 }
104
105 static uint64_t
106 aw_clk_nmm_find_best(struct aw_clk_nmm_sc *sc, uint64_t fparent, uint64_t *fout,
107 uint32_t *factor_n, uint32_t *factor_m0, uint32_t *factor_m1)
108 {
109 uint64_t cur, best;
110 uint32_t n, m0, m1;
111 uint32_t max_n, max_m0, max_m1;
112 uint32_t min_n, min_m0, min_m1;
113
114 *factor_n = *factor_m0 = *factor_m1 = 0;
115
116 max_n = aw_clk_factor_get_max(&sc->n);
117 min_n = aw_clk_factor_get_min(&sc->n);
118 max_m0 = aw_clk_factor_get_max(&sc->m0);
119 min_m0 = aw_clk_factor_get_min(&sc->m0);
120 max_m1 = aw_clk_factor_get_max(&sc->m1);
121 min_m1 = aw_clk_factor_get_min(&sc->m1);
122
123 for (m0 = min_m0; m0 <= max_m0; ) {
124 for (m1 = min_m1; m1 <= max_m1; ) {
125 for (n = min_n; n <= max_n; ) {
126 cur = fparent * n / m0 / m1;
127 if (abs(*fout - cur) < abs(*fout - best)) {
128 best = cur;
129 *factor_n = n;
130 *factor_m0 = m0;
131 *factor_m1 = m1;
132 }
133 n++;
134 }
135 m1++;
136 }
137 m0++;
138 }
139
140 return (best);
141 }
142
143 static int
144 aw_clk_nmm_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
145 int flags, int *stop)
146 {
147 struct aw_clk_nmm_sc *sc;
148 uint64_t cur, best;
149 uint32_t val, n, m0, m1, best_n, best_m0, best_m1;
150 int retry;
151
152 sc = clknode_get_softc(clk);
153
154 best = cur = 0;
155
156 best = aw_clk_nmm_find_best(sc, fparent, fout,
157 &best_n, &best_m0, &best_m1);
158
159 if ((flags & CLK_SET_DRYRUN) != 0) {
160 *fout = best;
161 *stop = 1;
162 return (0);
163 }
164
165 if ((best < *fout) &&
166 ((flags & CLK_SET_ROUND_DOWN) == 0)) {
167 *stop = 1;
168 return (ERANGE);
169 }
170 if ((best > *fout) &&
171 ((flags & CLK_SET_ROUND_UP) == 0)) {
172 *stop = 1;
173 return (ERANGE);
174 }
175
176 DEVICE_LOCK(clk);
177 READ4(clk, sc->offset, &val);
178
179 n = aw_clk_factor_get_value(&sc->n, best_n);
180 m0 = aw_clk_factor_get_value(&sc->m0, best_m0);
181 m1 = aw_clk_factor_get_value(&sc->m1, best_m1);
182 val &= ~sc->n.mask;
183 val &= ~sc->m0.mask;
184 val &= ~sc->m1.mask;
185 val |= n << sc->n.shift;
186 val |= m0 << sc->m0.shift;
187 val |= m1 << sc->m1.shift;
188
189 WRITE4(clk, sc->offset, val);
190 DEVICE_UNLOCK(clk);
191
192 if ((sc->flags & AW_CLK_HAS_LOCK) != 0) {
193 for (retry = 0; retry < sc->lock_retries; retry++) {
194 READ4(clk, sc->offset, &val);
195 if ((val & (1 << sc->lock_shift)) != 0)
196 break;
197 DELAY(1000);
198 }
199 }
200
201 *fout = best;
202 *stop = 1;
203
204 return (0);
205 }
206
207 static int
208 aw_clk_nmm_recalc(struct clknode *clk, uint64_t *freq)
209 {
210 struct aw_clk_nmm_sc *sc;
211 uint32_t val, n, m0, m1;
212
213 sc = clknode_get_softc(clk);
214
215 DEVICE_LOCK(clk);
216 READ4(clk, sc->offset, &val);
217 DEVICE_UNLOCK(clk);
218
219 n = aw_clk_get_factor(val, &sc->n);
220 m0 = aw_clk_get_factor(val, &sc->m0);
221 m1 = aw_clk_get_factor(val, &sc->m1);
222
223 *freq = *freq * n / m0 / m1;
224
225 return (0);
226 }
227
228 static clknode_method_t aw_nmm_clknode_methods[] = {
229 /* Device interface */
230 CLKNODEMETHOD(clknode_init, aw_clk_nmm_init),
231 CLKNODEMETHOD(clknode_set_gate, aw_clk_nmm_set_gate),
232 CLKNODEMETHOD(clknode_recalc_freq, aw_clk_nmm_recalc),
233 CLKNODEMETHOD(clknode_set_freq, aw_clk_nmm_set_freq),
234 CLKNODEMETHOD_END
235 };
236
237 DEFINE_CLASS_1(aw_nmm_clknode, aw_nmm_clknode_class, aw_nmm_clknode_methods,
238 sizeof(struct aw_clk_nmm_sc), clknode_class);
239
240 int
241 aw_clk_nmm_register(struct clkdom *clkdom, struct aw_clk_nmm_def *clkdef)
242 {
243 struct clknode *clk;
244 struct aw_clk_nmm_sc *sc;
245
246 clk = clknode_create(clkdom, &aw_nmm_clknode_class, &clkdef->clkdef);
247 if (clk == NULL)
248 return (1);
249
250 sc = clknode_get_softc(clk);
251
252 sc->offset = clkdef->offset;
253
254 sc->n.shift = clkdef->n.shift;
255 sc->n.width = clkdef->n.width;
256 sc->n.mask = ((1 << sc->n.width) - 1) << sc->n.shift;
257 sc->n.value = clkdef->n.value;
258 sc->n.flags = clkdef->n.flags;
259
260 sc->m0.shift = clkdef->m0.shift;
261 sc->m0.width = clkdef->m0.width;
262 sc->m0.mask = ((1 << sc->m0.width) - 1) << sc->m0.shift;
263 sc->m0.value = clkdef->m0.value;
264 sc->m0.flags = clkdef->m0.flags;
265
266 sc->m1.shift = clkdef->m1.shift;
267 sc->m1.width = clkdef->m1.width;
268 sc->m1.mask = ((1 << sc->m1.width) - 1) << sc->m1.shift;
269 sc->m1.value = clkdef->m1.value;
270 sc->m1.flags = clkdef->m1.flags;
271
272 sc->gate_shift = clkdef->gate_shift;
273
274 sc->lock_shift = clkdef->lock_shift;
275 sc->lock_retries = clkdef->lock_retries;
276
277 sc->flags = clkdef->flags;
278
279 clknode_register(clkdom, clk);
280
281 return (0);
282 }
Cache object: 8b5ae18ae661d1f77e398ef97d77f7f3
|