1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2019 Emmanuel Vadot <manu@freebsd.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD$
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/bus.h>
36
37 #include <dev/extres/clk/clk.h>
38
39 #include <arm/allwinner/clkng/aw_clk.h>
40 #include <arm/allwinner/clkng/aw_clk_np.h>
41
42 #include "clkdev_if.h"
43
44 /*
45 * clknode for clocks matching the formula :
46 *
47 * clk = clkin * n / p
48 *
49 */
50
51 struct aw_clk_np_sc {
52 uint32_t offset;
53
54 struct aw_clk_factor n;
55 struct aw_clk_factor p;
56
57 uint32_t gate_shift;
58 uint32_t lock_shift;
59 uint32_t lock_retries;
60
61 uint32_t flags;
62 };
63
64 #define WRITE4(_clk, off, val) \
65 CLKDEV_WRITE_4(clknode_get_device(_clk), off, val)
66 #define READ4(_clk, off, val) \
67 CLKDEV_READ_4(clknode_get_device(_clk), off, val)
68 #define DEVICE_LOCK(_clk) \
69 CLKDEV_DEVICE_LOCK(clknode_get_device(_clk))
70 #define DEVICE_UNLOCK(_clk) \
71 CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk))
72
73 static int
74 aw_clk_np_init(struct clknode *clk, device_t dev)
75 {
76
77 clknode_init_parent_idx(clk, 0);
78 return (0);
79 }
80
81 static int
82 aw_clk_np_set_gate(struct clknode *clk, bool enable)
83 {
84 struct aw_clk_np_sc *sc;
85 uint32_t val;
86
87 sc = clknode_get_softc(clk);
88
89 if ((sc->flags & AW_CLK_HAS_GATE) == 0)
90 return (0);
91
92 DEVICE_LOCK(clk);
93 READ4(clk, sc->offset, &val);
94 if (enable)
95 val |= (1 << sc->gate_shift);
96 else
97 val &= ~(1 << sc->gate_shift);
98 WRITE4(clk, sc->offset, val);
99 DEVICE_UNLOCK(clk);
100
101 return (0);
102 }
103
104 static uint64_t
105 aw_clk_np_find_best(struct aw_clk_np_sc *sc, uint64_t fparent, uint64_t *fout,
106 uint32_t *factor_n, uint32_t *factor_p)
107 {
108 uint64_t cur, best;
109 uint32_t n, p, max_n, max_p, min_n, min_p;
110
111 *factor_n = *factor_p = 0;
112
113 max_n = aw_clk_factor_get_max(&sc->n);
114 max_p = aw_clk_factor_get_max(&sc->p);
115 min_n = aw_clk_factor_get_min(&sc->n);
116 min_p = aw_clk_factor_get_min(&sc->p);
117
118 for (p = min_p; p <= max_p; ) {
119 for (n = min_n; n <= max_n; ) {
120 cur = fparent * n / p;
121 if (abs(*fout - cur) < abs(*fout - best)) {
122 best = cur;
123 *factor_n = n;
124 *factor_p = p;
125 }
126
127 n++;
128 }
129 p++;
130 }
131
132 return (best);
133 }
134
135 static int
136 aw_clk_np_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
137 int flags, int *stop)
138 {
139 struct aw_clk_np_sc *sc;
140 uint64_t cur, best;
141 uint32_t val, n, p, best_n, best_p;
142 int retry;
143
144 sc = clknode_get_softc(clk);
145
146 best = cur = 0;
147
148 best = aw_clk_np_find_best(sc, fparent, fout,
149 &best_n, &best_p);
150
151 if ((flags & CLK_SET_DRYRUN) != 0) {
152 *fout = best;
153 *stop = 1;
154 return (0);
155 }
156
157 if ((best < *fout) &&
158 ((flags & CLK_SET_ROUND_DOWN) == 0)) {
159 *stop = 1;
160 return (ERANGE);
161 }
162 if ((best > *fout) &&
163 ((flags & CLK_SET_ROUND_UP) == 0)) {
164 *stop = 1;
165 return (ERANGE);
166 }
167
168 DEVICE_LOCK(clk);
169 READ4(clk, sc->offset, &val);
170
171 n = aw_clk_factor_get_value(&sc->n, best_n);
172 p = aw_clk_factor_get_value(&sc->p, best_p);
173 val &= ~sc->n.mask;
174 val &= ~sc->p.mask;
175 val |= n << sc->n.shift;
176 val |= p << sc->p.shift;
177
178 WRITE4(clk, sc->offset, val);
179 DEVICE_UNLOCK(clk);
180
181 if ((sc->flags & AW_CLK_HAS_LOCK) != 0) {
182 for (retry = 0; retry < sc->lock_retries; retry++) {
183 READ4(clk, sc->offset, &val);
184 if ((val & (1 << sc->lock_shift)) != 0)
185 break;
186 DELAY(1000);
187 }
188 }
189
190 *fout = best;
191 *stop = 1;
192
193 return (0);
194 }
195
196 static int
197 aw_clk_np_recalc(struct clknode *clk, uint64_t *freq)
198 {
199 struct aw_clk_np_sc *sc;
200 uint32_t val, n, p;
201
202 sc = clknode_get_softc(clk);
203
204 DEVICE_LOCK(clk);
205 READ4(clk, sc->offset, &val);
206 DEVICE_UNLOCK(clk);
207
208 n = aw_clk_get_factor(val, &sc->n);
209 p = aw_clk_get_factor(val, &sc->p);
210
211 *freq = *freq * n / p;
212
213 return (0);
214 }
215
216 static clknode_method_t aw_np_clknode_methods[] = {
217 /* Device interface */
218 CLKNODEMETHOD(clknode_init, aw_clk_np_init),
219 CLKNODEMETHOD(clknode_set_gate, aw_clk_np_set_gate),
220 CLKNODEMETHOD(clknode_recalc_freq, aw_clk_np_recalc),
221 CLKNODEMETHOD(clknode_set_freq, aw_clk_np_set_freq),
222 CLKNODEMETHOD_END
223 };
224
225 DEFINE_CLASS_1(aw_np_clknode, aw_np_clknode_class, aw_np_clknode_methods,
226 sizeof(struct aw_clk_np_sc), clknode_class);
227
228 int
229 aw_clk_np_register(struct clkdom *clkdom, struct aw_clk_np_def *clkdef)
230 {
231 struct clknode *clk;
232 struct aw_clk_np_sc *sc;
233
234 clk = clknode_create(clkdom, &aw_np_clknode_class, &clkdef->clkdef);
235 if (clk == NULL)
236 return (1);
237
238 sc = clknode_get_softc(clk);
239
240 sc->offset = clkdef->offset;
241
242 sc->n.shift = clkdef->n.shift;
243 sc->n.width = clkdef->n.width;
244 sc->n.mask = ((1 << sc->n.width) - 1) << sc->n.shift;
245 sc->n.value = clkdef->n.value;
246 sc->n.flags = clkdef->n.flags;
247
248 sc->p.shift = clkdef->p.shift;
249 sc->p.width = clkdef->p.width;
250 sc->p.mask = ((1 << sc->p.width) - 1) << sc->p.shift;
251 sc->p.value = clkdef->p.value;
252 sc->p.flags = clkdef->p.flags;
253
254 sc->gate_shift = clkdef->gate_shift;
255
256 sc->lock_shift = clkdef->lock_shift;
257 sc->lock_retries = clkdef->lock_retries;
258
259 sc->flags = clkdef->flags;
260
261 clknode_register(clkdom, clk);
262
263 return (0);
264 }
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