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sys/arm/allwinner/clkng/ccu_a10.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Kyle Evans <kevans@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <machine/bus.h> 40 41 #include <dev/fdt/simplebus.h> 42 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 46 #include <dev/extres/clk/clk_div.h> 47 #include <dev/extres/clk/clk_fixed.h> 48 #include <dev/extres/clk/clk_mux.h> 49 50 #include <arm/allwinner/clkng/aw_ccung.h> 51 52 #include <dt-bindings/clock/sun4i-a10-ccu.h> 53 #include <dt-bindings/clock/sun7i-a20-ccu.h> 54 #include <dt-bindings/reset/sun4i-a10-ccu.h> 55 56 /* Non-exported resets */ 57 /* Non-exported clocks */ 58 #define CLK_PLL_CORE 2 59 #define CLK_AXI 3 60 #define CLK_AHB 4 61 #define CLK_APB0 5 62 #define CLK_APB1 6 63 #define CLK_PLL_VIDEO0 8 64 #define CLK_PLL_DDR 12 65 #define CLK_PLL_DDR_OTHER 13 66 #define CLK_PLL6 14 67 #define CLK_PLL_PERIPH 15 68 #define CLK_PLL_SATA 16 69 #define CLK_PLL_VIDEO1 17 70 71 /* Non-exported fixed clocks */ 72 73 static struct aw_ccung_reset a10_ccu_resets[] = { 74 CCU_RESET(RST_USB_PHY0, 0xcc, 0) 75 CCU_RESET(RST_USB_PHY1, 0xcc, 1) 76 CCU_RESET(RST_USB_PHY2, 0xcc, 2) 77 78 CCU_RESET(RST_GPS, 0xd0, 0) 79 80 CCU_RESET(RST_DE_BE0, 0x104, 30) 81 CCU_RESET(RST_DE_BE1, 0x108, 30) 82 CCU_RESET(RST_DE_FE0, 0x10c, 30) 83 CCU_RESET(RST_DE_FE1, 0x110, 30) 84 CCU_RESET(RST_DE_MP, 0x114, 30) 85 86 CCU_RESET(RST_TVE0, 0x118, 29) 87 CCU_RESET(RST_TCON0, 0x118, 30) 88 89 CCU_RESET(RST_TVE1, 0x11c, 29) 90 CCU_RESET(RST_TCON1, 0x11c, 30) 91 92 CCU_RESET(RST_CSI0, 0x134, 30) 93 CCU_RESET(RST_CSI1, 0x138, 30) 94 95 CCU_RESET(RST_VE, 0x13c, 0) 96 97 CCU_RESET(RST_ACE, 0x148, 16) 98 99 CCU_RESET(RST_LVDS, 0x14c, 0) 100 101 CCU_RESET(RST_GPU, 0x154, 30) 102 103 CCU_RESET(RST_HDMI_H, 0x170, 0) 104 CCU_RESET(RST_HDMI_SYS, 0x170, 1) 105 CCU_RESET(RST_HDMI_AUDIO_DMA, 0x170, 2) 106 }; 107 108 static struct aw_ccung_gate a10_ccu_gates[] = { 109 CCU_GATE(CLK_HOSC, "hosc", "osc24M", 0x50, 0) 110 111 CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0) 112 CCU_GATE(CLK_AHB_EHCI0, "ahb-ehci0", "ahb", 0x60, 1) 113 CCU_GATE(CLK_AHB_OHCI0, "ahb-ohci0", "ahb", 0x60, 2) 114 CCU_GATE(CLK_AHB_EHCI1, "ahb-ehci1", "ahb", 0x60, 3) 115 CCU_GATE(CLK_AHB_OHCI1, "ahb-ohci1", "ahb", 0x60, 4) 116 CCU_GATE(CLK_AHB_SS, "ahb-ss", "ahb", 0x60, 5) 117 CCU_GATE(CLK_AHB_DMA, "ahb-dma", "ahb", 0x60, 6) 118 CCU_GATE(CLK_AHB_BIST, "ahb-bist", "ahb", 0x60, 7) 119 CCU_GATE(CLK_AHB_MMC0, "ahb-mmc0", "ahb", 0x60, 8) 120 CCU_GATE(CLK_AHB_MMC1, "ahb-mmc1", "ahb", 0x60, 9) 121 CCU_GATE(CLK_AHB_MMC2, "ahb-mmc2", "ahb", 0x60, 10) 122 CCU_GATE(CLK_AHB_MMC3, "ahb-mmc3", "ahb", 0x60, 11) 123 CCU_GATE(CLK_AHB_MS, "ahb-ms", "ahb", 0x60, 12) 124 CCU_GATE(CLK_AHB_NAND, "ahb-nand", "ahb", 0x60, 13) 125 CCU_GATE(CLK_AHB_SDRAM, "ahb-sdram", "ahb", 0x60, 14) 126 CCU_GATE(CLK_AHB_ACE, "ahb-ace", "ahb", 0x60, 16) 127 CCU_GATE(CLK_AHB_EMAC, "ahb-emac", "ahb", 0x60, 17) 128 CCU_GATE(CLK_AHB_TS, "ahb-ts", "ahb", 0x60, 18) 129 CCU_GATE(CLK_AHB_SPI0, "ahb-spi0", "ahb", 0x60, 20) 130 CCU_GATE(CLK_AHB_SPI1, "ahb-spi1", "ahb", 0x60, 21) 131 CCU_GATE(CLK_AHB_SPI2, "ahb-spi2", "ahb", 0x60, 22) 132 CCU_GATE(CLK_AHB_SPI3, "ahb-spi3", "ahb", 0x60, 23) 133 CCU_GATE(CLK_AHB_SATA, "ahb-sata", "ahb", 0x60, 25) 134 135 CCU_GATE(CLK_AHB_VE, "ahb-ve", "ahb", 0x64, 0) 136 CCU_GATE(CLK_AHB_TVD, "ahb-tvd", "ahb", 0x64, 1) 137 CCU_GATE(CLK_AHB_TVE0, "ahb-tve0", "ahb", 0x64, 2) 138 CCU_GATE(CLK_AHB_TVE1, "ahb-tve1", "ahb", 0x64, 3) 139 CCU_GATE(CLK_AHB_LCD0, "ahb-lcd0", "ahb", 0x64, 4) 140 CCU_GATE(CLK_AHB_LCD1, "ahb-lcd1", "ahb", 0x64, 5) 141 CCU_GATE(CLK_AHB_CSI0, "ahb-csi0", "ahb", 0x64, 8) 142 CCU_GATE(CLK_AHB_CSI1, "ahb-csi1", "ahb", 0x64, 9) 143 CCU_GATE(CLK_AHB_HDMI1, "ahb-hdmi1", "ahb", 0x64, 10) 144 CCU_GATE(CLK_AHB_HDMI0, "ahb-hdmi0", "ahb", 0x64, 11) 145 CCU_GATE(CLK_AHB_DE_BE0, "ahb-de_be0", "ahb", 0x64, 12) 146 CCU_GATE(CLK_AHB_DE_BE1, "ahb-de_be1", "ahb", 0x64, 13) 147 CCU_GATE(CLK_AHB_DE_FE0, "ahb-de_fe0", "ahb", 0x64, 14) 148 CCU_GATE(CLK_AHB_DE_FE1, "ahb-de_fe1", "ahb", 0x64, 15) 149 CCU_GATE(CLK_AHB_GMAC, "ahb-gmac", "ahb", 0x64, 17) 150 CCU_GATE(CLK_AHB_MP, "ahb-mp", "ahb", 0x64, 18) 151 CCU_GATE(CLK_AHB_GPU, "ahb-gpu", "ahb", 0x64, 20) 152 153 CCU_GATE(CLK_APB0_CODEC, "apb0-codec", "apb0", 0x68, 0) 154 CCU_GATE(CLK_APB0_SPDIF, "apb0-spdif", "apb0", 0x68, 1) 155 CCU_GATE(CLK_APB0_AC97, "apb0-ac97", "apb0", 0x68, 2) 156 CCU_GATE(CLK_APB0_I2S0, "apb0-i2s0", "apb0", 0x68, 3) 157 CCU_GATE(CLK_APB0_I2S1, "apb0-i2s1", "apb0", 0x68, 4) 158 CCU_GATE(CLK_APB0_PIO, "apb0-pi0", "apb0", 0x68, 5) 159 CCU_GATE(CLK_APB0_IR0, "apb0-ir0", "apb0", 0x68, 6) 160 CCU_GATE(CLK_APB0_IR1, "apb0-ir1", "apb0", 0x68, 7) 161 CCU_GATE(CLK_APB0_I2S2, "apb0-i2s2", "apb0",0x68, 8) 162 CCU_GATE(CLK_APB0_KEYPAD, "apb0-keypad", "apb0", 0x68, 10) 163 164 CCU_GATE(CLK_APB1_I2C0, "apb1-i2c0", "apb1", 0x6c, 0) 165 CCU_GATE(CLK_APB1_I2C1, "apb1-i2c1", "apb1",0x6c, 1) 166 CCU_GATE(CLK_APB1_I2C2, "apb1-i2c2", "apb1",0x6c, 2) 167 CCU_GATE(CLK_APB1_I2C3, "apb1-i2c3", "apb1",0x6c, 3) 168 CCU_GATE(CLK_APB1_CAN, "apb1-can", "apb1",0x6c, 4) 169 CCU_GATE(CLK_APB1_SCR, "apb1-scr", "apb1",0x6c, 5) 170 CCU_GATE(CLK_APB1_PS20, "apb1-ps20", "apb1",0x6c, 6) 171 CCU_GATE(CLK_APB1_PS21, "apb1-ps21", "apb1",0x6c, 7) 172 CCU_GATE(CLK_APB1_I2C4, "apb1-i2c4", "apb1", 0x6c, 15) 173 CCU_GATE(CLK_APB1_UART0, "apb1-uart0", "apb1",0x6c, 16) 174 CCU_GATE(CLK_APB1_UART1, "apb1-uart1", "apb1",0x6c, 17) 175 CCU_GATE(CLK_APB1_UART2, "apb1-uart2", "apb1",0x6c, 18) 176 CCU_GATE(CLK_APB1_UART3, "apb1-uart3", "apb1",0x6c, 19) 177 CCU_GATE(CLK_APB1_UART4, "apb1-uart4", "apb1",0x6c, 20) 178 CCU_GATE(CLK_APB1_UART5, "apb1-uart5", "apb1",0x6c, 21) 179 CCU_GATE(CLK_APB1_UART6, "apb1-uart6", "apb1",0x6c, 22) 180 CCU_GATE(CLK_APB1_UART7, "apb1-uart7", "apb1",0x6c, 23) 181 182 CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "ahb", 0xcc, 6) 183 CCU_GATE(CLK_USB_OHCI1, "usb-ohci1", "ahb", 0xcc, 7) 184 CCU_GATE(CLK_USB_PHY, "usb-phy", "ahb", 0xcc, 8) 185 186 CCU_GATE(CLK_DRAM_VE, "dram-ve", "pll_ddr", 0x100, 0) 187 CCU_GATE(CLK_DRAM_CSI0, "dram-csi0", "pll_ddr", 0x100, 1) 188 CCU_GATE(CLK_DRAM_CSI1, "dram-csi1", "pll_ddr", 0x100, 2) 189 CCU_GATE(CLK_DRAM_TS, "dram-ts", "pll_ddr", 0x100, 3) 190 CCU_GATE(CLK_DRAM_TVD, "dram-tvd", "pll_ddr", 0x100, 4) 191 CCU_GATE(CLK_DRAM_TVE0, "dram-tve0", "pll_ddr", 0x100, 5) 192 CCU_GATE(CLK_DRAM_TVE1, "dram-tve1", "pll_ddr", 0x100, 6) 193 CCU_GATE(CLK_DRAM_OUT, "dram-out", "pll_ddr", 0x100, 15) 194 CCU_GATE(CLK_DRAM_DE_FE1, "dram-de_fe1", "pll_ddr", 0x100, 24) 195 CCU_GATE(CLK_DRAM_DE_FE0, "dram-de_fe0", "pll_ddr", 0x100, 25) 196 CCU_GATE(CLK_DRAM_DE_BE0, "dram-de_be0", "pll_ddr", 0x100, 26) 197 CCU_GATE(CLK_DRAM_DE_BE1, "dram-de_be1", "pll_ddr", 0x100, 27) 198 CCU_GATE(CLK_DRAM_MP, "dram-de_mp", "pll_ddr", 0x100, 28) 199 CCU_GATE(CLK_DRAM_ACE, "dram-ace", "pll_ddr", 0x100, 29) 200 }; 201 202 static const char *pll_parents[] = {"osc24M"}; 203 NKMP_CLK(pll_core_clk, 204 CLK_PLL_CORE, /* id */ 205 "pll_core", pll_parents, /* name, parents */ 206 0x00, /* offset */ 207 8, 5, 0, AW_CLK_FACTOR_ZERO_IS_ONE, /* n factor */ 208 4, 2, 0, 0, /* k factor */ 209 0, 2, 0, 0, /* m factor */ 210 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ 211 31, /* gate */ 212 0, 0, /* lock */ 213 AW_CLK_HAS_GATE); /* flags */ 214 215 FRAC_CLK(pll_video0_clk, 216 CLK_PLL_VIDEO0, /* id */ 217 "pll_video0", pll_parents, /* name, parents */ 218 0x10, /* offset */ 219 0, 7, 0, 0, /* n factor */ 220 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 221 31, 0, 0, /* gate, lock, lock retries */ 222 AW_CLK_HAS_GATE, /* flags */ 223 270000000, 297000000, /* freq0, freq1 */ 224 15, 14, /* mode sel, freq sel */ 225 27000000, 381000000); /* min freq, max freq */ 226 static const char *pll_video0_2x_parents[] = {"pll_video0"}; 227 FIXED_CLK(pll_video0_2x_clk, 228 CLK_PLL_VIDEO0_2X, /* id */ 229 "pll_video0-2x", pll_video0_2x_parents, /* name, parents */ 230 0, /* freq */ 231 2, /* mult */ 232 1, /* div */ 233 0); /* flags */ 234 235 FRAC_CLK(pll_video1_clk, 236 CLK_PLL_VIDEO1, /* id */ 237 "pll_video1", pll_parents, /* name, parents */ 238 0x30, /* offset */ 239 0, 7, 0, 0, /* n factor */ 240 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 241 31, 0, 0, /* gate, lock, lock retries */ 242 AW_CLK_HAS_GATE, /* flags */ 243 270000000, 297000000, /* freq0, freq1 */ 244 15, 14, /* mode sel, freq sel */ 245 27000000, 381000000); /* min freq, max freq */ 246 static const char *pll_video1_2x_parents[] = {"pll_video1"}; 247 FIXED_CLK(pll_video1_2x_clk, 248 CLK_PLL_VIDEO1_2X, /* id */ 249 "pll_video1-2x", pll_video1_2x_parents, /* name, parents */ 250 0, /* freq */ 251 2, /* mult */ 252 1, /* div */ 253 0); /* flags */ 254 255 static const char *cpu_parents[] = {"osc32k", "osc24M", "pll_core", "pll_periph"}; 256 static const char *axi_parents[] = {"cpu"}; 257 static const char *ahb_parents[] = {"axi", "pll_periph", "pll6"}; 258 static const char *apb0_parents[] = {"ahb"}; 259 static const char *apb1_parents[] = {"osc24M", "pll_periph", "osc32k"}; 260 MUX_CLK(cpu_clk, 261 CLK_CPU, /* id */ 262 "cpu", cpu_parents, /* name, parents */ 263 0x54, 16, 2); /* offset, shift, width */ 264 NM_CLK(axi_clk, 265 CLK_AXI, /* id */ 266 "axi", axi_parents, /* name, parents */ 267 0x54, /* offset */ 268 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 269 0, 2, 0, 0, /* m factor */ 270 0, 0, /* mux */ 271 0, /* gate */ 272 0); /* flags */ 273 NM_CLK(ahb_clk, 274 CLK_AHB, /* id */ 275 "ahb", ahb_parents, /* name, parents */ 276 0x54, /* offset */ 277 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 278 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* m factor */ 279 6, 2, /* mux */ 280 0, /* gate */ 281 AW_CLK_HAS_MUX); /* flags */ 282 NM_CLK(apb0_clk, 283 CLK_APB0, /* id */ 284 "apb0", apb0_parents, /* name, parents */ 285 0x54, /* offset */ 286 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 287 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO | 288 AW_CLK_FACTOR_ZERO_IS_ONE, /* m factor */ 289 0, 0, /* mux */ 290 0, /* gate */ 291 0); /* flags */ 292 293 NM_CLK(apb1_clk, 294 CLK_APB1, /* id */ 295 "apb1", apb1_parents, /* name, parents */ 296 0x58, /* offset */ 297 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 298 0, 5, 0, 0, /* m factor */ 299 24, 2, /* mux */ 300 0, /* gate */ 301 AW_CLK_HAS_MUX); /* flags */ 302 303 NKMP_CLK(pll_ddr_other_clk, 304 CLK_PLL_DDR_OTHER, /* id */ 305 "pll_ddr_other", pll_parents, /* name, parents */ 306 0x20, /* offset */ 307 8, 5, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 308 4, 2, 0, 0, /* k factor */ 309 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 310 2, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ 311 31, /* gate */ 312 0, 0, /* lock */ 313 AW_CLK_HAS_GATE); /* flags */ 314 NKMP_CLK(pll_ddr_clk, 315 CLK_PLL_DDR, /* id */ 316 "pll_ddr", pll_parents, /* name, parents */ 317 0x20, /* offset */ 318 8, 5, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 319 4, 2, 0, 0, /* k factor */ 320 0, 2, 0, 0, /* m factor */ 321 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 322 31, /* gate */ 323 0, 0, /* lock */ 324 AW_CLK_HAS_GATE); /* flags */ 325 326 NKMP_CLK(pll6_clk, 327 CLK_PLL6, /* id */ 328 "pll6", pll_parents, /* name, parents */ 329 0x28, /* offset */ 330 8, 5, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 331 4, 2, 0, 0, /* k factor */ 332 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 333 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 334 31, /* gate */ 335 0, 0, /* lock */ 336 AW_CLK_HAS_GATE); /* flags */ 337 338 static const char *pll6_parents[] = {"pll6"}; 339 FIXED_CLK(pll_periph_clk, 340 CLK_PLL_PERIPH, /* id */ 341 "pll_periph", pll6_parents, /* name, parents */ 342 0, /* freq */ 343 1, /* mult */ 344 2, /* div */ 345 0); /* flags */ 346 NKMP_CLK(pll_periph_sata_clk, 347 CLK_PLL_SATA, /* id */ 348 "pll_periph_sata", pll6_parents, /* name, parents */ 349 0x28, /* offset */ 350 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 351 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 352 0, 2, 0, 0, /* m factor */ 353 0, 0, 6, AW_CLK_FACTOR_FIXED, /* p factor (fake, 6) */ 354 14, /* gate */ 355 0, 0, /* lock */ 356 AW_CLK_HAS_GATE); /* flags */ 357 358 static const char *mod_parents[] = {"osc24M", "pll_periph", "pll_ddr_other"}; 359 NM_CLK(nand_clk, 360 CLK_NAND, /* id */ 361 "nand", mod_parents, /* name, parents */ 362 0x80, /* offset */ 363 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 364 0, 4, 0, 0, /* m factor */ 365 24, 2, /* mux */ 366 31, /* gate */ 367 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 368 369 NM_CLK(ms_clk, 370 CLK_MS, /* id */ 371 "ms", mod_parents, /* name, parents */ 372 0x84, /* offset */ 373 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 374 0, 4, 0, 0, /* m factor */ 375 24, 2, /* mux */ 376 31, /* gate */ 377 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 378 379 NM_CLK(mmc0_clk, 380 CLK_MMC0, /* id */ 381 "mmc0", mod_parents, /* name, parents */ 382 0x88, /* offset */ 383 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 384 0, 4, 0, 0, /* m factor */ 385 24, 2, /* mux */ 386 31, /* gate */ 387 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | 388 AW_CLK_REPARENT); /* flags */ 389 390 NM_CLK(mmc1_clk, 391 CLK_MMC1, /* id */ 392 "mmc1", mod_parents, /* name, parents */ 393 0x8c, /* offset */ 394 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 395 0, 4, 0, 0, /* m factor */ 396 24, 2, /* mux */ 397 31, /* gate */ 398 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | 399 AW_CLK_REPARENT); /* flags */ 400 401 NM_CLK(mmc2_clk, 402 CLK_MMC2, /* id */ 403 "mmc2", mod_parents, /* name, parents */ 404 0x90, /* offset */ 405 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 406 0, 4, 0, 0, /* m factor */ 407 24, 2, /* mux */ 408 31, /* gate */ 409 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | 410 AW_CLK_REPARENT); /* flags */ 411 412 NM_CLK(mmc3_clk, 413 CLK_MMC3, /* id */ 414 "mmc3", mod_parents, /* name, parents */ 415 0x94, /* offset */ 416 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 417 0, 4, 0, 0, /* m factor */ 418 24, 2, /* mux */ 419 31, /* gate */ 420 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | 421 AW_CLK_REPARENT); /* flags */ 422 423 NM_CLK(ts_clk, 424 CLK_TS, /* id */ 425 "ts", mod_parents, /* name, parents */ 426 0x94, /* offset */ 427 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 428 0, 4, 0, 0, /* m factor */ 429 24, 2, /* mux */ 430 31, /* gate */ 431 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 432 433 NM_CLK(ss_clk, 434 CLK_SS, /* id */ 435 "ss", mod_parents, /* name, parents */ 436 0x9c, /* offset */ 437 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 438 0, 4, 0, 0, /* m factor */ 439 24, 2, /* mux */ 440 31, /* gate */ 441 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 442 443 NM_CLK(spi0_clk, 444 CLK_SPI0, /* id */ 445 "spi0", mod_parents, /* name, parents */ 446 0xa0, /* offset */ 447 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 448 0, 4, 0, 0, /* m factor */ 449 24, 2, /* mux */ 450 31, /* gate */ 451 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 452 453 NM_CLK(spi1_clk, 454 CLK_SPI1, /* id */ 455 "spi1", mod_parents, /* name, parents */ 456 0xa4, /* offset */ 457 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 458 0, 4, 0, 0, /* m factor */ 459 24, 2, /* mux */ 460 31, /* gate */ 461 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 462 463 NM_CLK(spi2_clk, 464 CLK_SPI2, /* id */ 465 "spi2", mod_parents, /* name, parents */ 466 0xa8, /* offset */ 467 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 468 0, 4, 0, 0, /* m factor */ 469 24, 2, /* mux */ 470 31, /* gate */ 471 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 472 473 /* MISSING CLK_PATA */ 474 475 NM_CLK(ir0_clk, 476 CLK_IR0, /* id */ 477 "ir0", mod_parents, /* name, parents */ 478 0xb0, /* offset */ 479 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 480 0, 4, 0, 0, /* m factor */ 481 24, 2, /* mux */ 482 31, /* gate */ 483 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 484 485 NM_CLK(ir1_clk, 486 CLK_IR1, /* id */ 487 "ir1", mod_parents, /* name, parents */ 488 0xb4, /* offset */ 489 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 490 0, 4, 0, 0, /* m factor */ 491 24, 2, /* mux */ 492 31, /* gate */ 493 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 494 495 /* MISSING CLK_I2S0, CLK_AC97, CLK_SPDIF */ 496 497 static const char *keypad_parents[] = {"osc24M", "osc24M", "osc32k"}; 498 NM_CLK(keypad_clk, 499 CLK_KEYPAD, /* id */ 500 "keypad", keypad_parents, /* name, parents */ 501 0xc4, /* offset */ 502 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 503 0, 5, 0, 0, /* m factor */ 504 24, 2, /* mux */ 505 31, /* gate */ 506 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 507 508 static const char *sata_parents[] = {"pll_periph_sata", "osc32k"}; 509 NM_CLK(sata_clk, 510 CLK_SATA, /* id */ 511 "sata", sata_parents, /* name, parents */ 512 0xc8, /* offset */ 513 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 514 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 515 24, 1, /* mux */ 516 31, /* gate */ 517 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 518 519 NM_CLK(spi3_clk, 520 CLK_SPI3, /* id */ 521 "spi3", mod_parents, /* name, parents */ 522 0xd4, /* offset */ 523 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 524 0, 4, 0, 0, /* m factor */ 525 24, 2, /* mux */ 526 31, /* gate */ 527 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 528 529 /* MISSING CLK_I2S1, CLK_I2S2, DE Clocks */ 530 531 static struct aw_ccung_clk a10_ccu_clks[] = { 532 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_core_clk}, 533 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_other_clk}, 534 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_clk}, 535 { .type = AW_CLK_NKMP, .clk.nkmp = &pll6_clk}, 536 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph_sata_clk}, 537 { .type = AW_CLK_NM, .clk.nm = &axi_clk}, 538 { .type = AW_CLK_NM, .clk.nm = &ahb_clk}, 539 { .type = AW_CLK_NM, .clk.nm = &apb0_clk}, 540 { .type = AW_CLK_NM, .clk.nm = &apb1_clk}, 541 { .type = AW_CLK_FRAC, .clk.frac = &pll_video0_clk}, 542 { .type = AW_CLK_FRAC, .clk.frac = &pll_video1_clk}, 543 { .type = AW_CLK_NM, .clk.nm = &nand_clk}, 544 { .type = AW_CLK_NM, .clk.nm = &ms_clk}, 545 { .type = AW_CLK_NM, .clk.nm = &mmc0_clk}, 546 { .type = AW_CLK_NM, .clk.nm = &mmc1_clk}, 547 { .type = AW_CLK_NM, .clk.nm = &mmc2_clk}, 548 { .type = AW_CLK_NM, .clk.nm = &mmc3_clk}, 549 { .type = AW_CLK_NM, .clk.nm = &ts_clk}, 550 { .type = AW_CLK_NM, .clk.nm = &ss_clk}, 551 { .type = AW_CLK_NM, .clk.nm = &spi0_clk}, 552 { .type = AW_CLK_NM, .clk.nm = &spi1_clk}, 553 { .type = AW_CLK_NM, .clk.nm = &spi2_clk}, 554 { .type = AW_CLK_NM, .clk.nm = &ir0_clk}, 555 { .type = AW_CLK_NM, .clk.nm = &ir1_clk}, 556 { .type = AW_CLK_NM, .clk.nm = &keypad_clk}, 557 { .type = AW_CLK_NM, .clk.nm = &sata_clk}, 558 { .type = AW_CLK_NM, .clk.nm = &spi3_clk}, 559 { .type = AW_CLK_MUX, .clk.mux = &cpu_clk}, 560 { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph_clk}, 561 { .type = AW_CLK_FIXED, .clk.fixed = &pll_video0_2x_clk}, 562 { .type = AW_CLK_FIXED, .clk.fixed = &pll_video1_2x_clk}, 563 }; 564 565 static struct aw_clk_init a10_init_clks[] = { 566 }; 567 568 static struct ofw_compat_data compat_data[] = { 569 #if defined(SOC_ALLWINNER_A10) 570 { "allwinner,sun4i-a10-ccu", 1 }, 571 #endif 572 #if defined(SOC_ALLWINNER_A20) 573 { "allwinner,sun7i-a20-ccu", 1 }, 574 #endif 575 { NULL, 0}, 576 }; 577 578 static int 579 ccu_a10_probe(device_t dev) 580 { 581 582 if (!ofw_bus_status_okay(dev)) 583 return (ENXIO); 584 585 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 586 return (ENXIO); 587 588 device_set_desc(dev, "Allwinner A10/A20 Clock Control Unit NG"); 589 return (BUS_PROBE_DEFAULT); 590 } 591 592 static int 593 ccu_a10_attach(device_t dev) 594 { 595 struct aw_ccung_softc *sc; 596 597 sc = device_get_softc(dev); 598 599 sc->resets = a10_ccu_resets; 600 sc->nresets = nitems(a10_ccu_resets); 601 sc->gates = a10_ccu_gates; 602 sc->ngates = nitems(a10_ccu_gates); 603 sc->clks = a10_ccu_clks; 604 sc->nclks = nitems(a10_ccu_clks); 605 sc->clk_init = a10_init_clks; 606 sc->n_clk_init = nitems(a10_init_clks); 607 608 return (aw_ccung_attach(dev)); 609 } 610 611 static device_method_t ccu_a10ng_methods[] = { 612 /* Device interface */ 613 DEVMETHOD(device_probe, ccu_a10_probe), 614 DEVMETHOD(device_attach, ccu_a10_attach), 615 616 DEVMETHOD_END 617 }; 618 619 DEFINE_CLASS_1(ccu_a10ng, ccu_a10ng_driver, ccu_a10ng_methods, 620 sizeof(struct aw_ccung_softc), aw_ccung_driver); 621 622 EARLY_DRIVER_MODULE(ccu_a10ng, simplebus, ccu_a10ng_driver, 0, 0, 623 BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
Cache object: 893b2b0c3aa93a300aa63b05bf1429e1
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