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FreeBSD/Linux Kernel Cross Reference
sys/arm/allwinner/clkng/ccu_h3.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2017,2018 Emmanuel Vadot <manu@freebsd.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <machine/bus.h> 40 41 #include <dev/fdt/simplebus.h> 42 43 #include <dev/ofw/ofw_bus.h> 44 #include <dev/ofw/ofw_bus_subr.h> 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/bus.h> 49 50 #include <dev/extres/clk/clk_div.h> 51 #include <dev/extres/clk/clk_fixed.h> 52 #include <dev/extres/clk/clk_mux.h> 53 54 #if defined(__aarch64__) 55 #include "opt_soc.h" 56 #endif 57 58 #include <arm/allwinner/clkng/aw_ccung.h> 59 60 #include <dt-bindings/clock/sun8i-h3-ccu.h> 61 #include <dt-bindings/reset/sun8i-h3-ccu.h> 62 63 /* Non-exported resets */ 64 #define RST_BUS_SCR 53 65 66 /* Non-exported clocks */ 67 #define CLK_PLL_CPUX 0 68 #define CLK_PLL_AUDIO_BASE 1 69 #define CLK_PLL_AUDIO 2 70 #define CLK_PLL_AUDIO_2X 3 71 #define CLK_PLL_AUDIO_4X 4 72 #define CLK_PLL_AUDIO_8X 5 73 #define CLK_PLL_VIDEO 6 74 #define CLK_PLL_VE 7 75 #define CLK_PLL_DDR 8 76 #define CLK_PLL_PERIPH0_2X 10 77 #define CLK_PLL_GPU 11 78 #define CLK_PLL_PERIPH1 12 79 #define CLK_PLL_DE 13 80 81 #define CLK_AXI 15 82 #define CLK_AHB1 16 83 #define CLK_APB1 17 84 #define CLK_APB2 18 85 #define CLK_AHB2 19 86 87 #define CLK_BUS_SCR 66 88 89 #define CLK_USBPHY0 88 90 #define CLK_USBPHY1 89 91 #define CLK_USBPHY2 90 92 #define CLK_USBPHY3 91 93 #define CLK_USBOHCI0 92 94 #define CLK_USBOHCI1 93 95 #define CLK_USBOHCI2 94 96 #define CLK_USBOHCI3 95 97 #define CLK_DRAM 96 98 99 #define CLK_MBUS 113 100 101 static struct aw_ccung_reset h3_ccu_resets[] = { 102 CCU_RESET(RST_USB_PHY0, 0xcc, 0) 103 CCU_RESET(RST_USB_PHY1, 0xcc, 1) 104 CCU_RESET(RST_USB_PHY2, 0xcc, 2) 105 CCU_RESET(RST_USB_PHY3, 0xcc, 3) 106 107 CCU_RESET(RST_MBUS, 0xfc, 31) 108 109 CCU_RESET(RST_BUS_CE, 0x2c0, 5) 110 CCU_RESET(RST_BUS_DMA, 0x2c0, 6) 111 CCU_RESET(RST_BUS_MMC0, 0x2c0, 8) 112 CCU_RESET(RST_BUS_MMC1, 0x2c0, 9) 113 CCU_RESET(RST_BUS_MMC2, 0x2c0, 10) 114 CCU_RESET(RST_BUS_NAND, 0x2c0, 13) 115 CCU_RESET(RST_BUS_DRAM, 0x2c0, 14) 116 CCU_RESET(RST_BUS_EMAC, 0x2c0, 17) 117 CCU_RESET(RST_BUS_TS, 0x2c0, 18) 118 CCU_RESET(RST_BUS_HSTIMER, 0x2c0, 19) 119 CCU_RESET(RST_BUS_SPI0, 0x2c0, 20) 120 CCU_RESET(RST_BUS_SPI1, 0x2c0, 21) 121 CCU_RESET(RST_BUS_OTG, 0x2c0, 23) 122 CCU_RESET(RST_BUS_EHCI0, 0x2c0, 24) 123 CCU_RESET(RST_BUS_EHCI1, 0x2c0, 25) 124 CCU_RESET(RST_BUS_EHCI2, 0x2c0, 26) 125 CCU_RESET(RST_BUS_EHCI3, 0x2c0, 27) 126 CCU_RESET(RST_BUS_OHCI0, 0x2c0, 28) 127 CCU_RESET(RST_BUS_OHCI1, 0x2c0, 29) 128 CCU_RESET(RST_BUS_OHCI2, 0x2c0, 30) 129 CCU_RESET(RST_BUS_OHCI3, 0x2c0, 31) 130 131 CCU_RESET(RST_BUS_VE, 0x2c4, 0) 132 CCU_RESET(RST_BUS_TCON0, 0x2c4, 3) 133 CCU_RESET(RST_BUS_TCON1, 0x2c4, 4) 134 CCU_RESET(RST_BUS_DEINTERLACE, 0x2c4, 5) 135 CCU_RESET(RST_BUS_CSI, 0x2c4, 8) 136 CCU_RESET(RST_BUS_TVE, 0x2c4, 9) 137 CCU_RESET(RST_BUS_HDMI0, 0x2c4, 10) 138 CCU_RESET(RST_BUS_HDMI1, 0x2c4, 11) 139 CCU_RESET(RST_BUS_DE, 0x2c4, 12) 140 CCU_RESET(RST_BUS_GPU, 0x2c4, 20) 141 CCU_RESET(RST_BUS_MSGBOX, 0x2c4, 21) 142 CCU_RESET(RST_BUS_SPINLOCK, 0x2c4, 22) 143 CCU_RESET(RST_BUS_DBG, 0x2c4, 31) 144 145 CCU_RESET(RST_BUS_EPHY, 0x2c8, 2) 146 147 CCU_RESET(RST_BUS_CODEC, 0x2d0, 0) 148 CCU_RESET(RST_BUS_SPDIF, 0x2d0, 1) 149 CCU_RESET(RST_BUS_THS, 0x2d0, 8) 150 CCU_RESET(RST_BUS_I2S0, 0x2d0, 12) 151 CCU_RESET(RST_BUS_I2S1, 0x2d0, 13) 152 CCU_RESET(RST_BUS_I2S2, 0x2d0, 14) 153 154 CCU_RESET(RST_BUS_I2C0, 0x2d8, 0) 155 CCU_RESET(RST_BUS_I2C1, 0x2d8, 1) 156 CCU_RESET(RST_BUS_I2C2, 0x2d8, 2) 157 CCU_RESET(RST_BUS_UART0, 0x2d8, 16) 158 CCU_RESET(RST_BUS_UART1, 0x2d8, 17) 159 CCU_RESET(RST_BUS_UART2, 0x2d8, 18) 160 CCU_RESET(RST_BUS_UART3, 0x2d8, 19) 161 CCU_RESET(RST_BUS_SCR, 0x2d8, 20) 162 }; 163 164 static struct aw_ccung_gate h3_ccu_gates[] = { 165 CCU_GATE(CLK_BUS_CE, "bus-ce", "ahb1", 0x60, 5) 166 CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6) 167 CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8) 168 CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9) 169 CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10) 170 CCU_GATE(CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13) 171 CCU_GATE(CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14) 172 CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb2", 0x60, 17) 173 CCU_GATE(CLK_BUS_TS, "bus-ts", "ahb1", 0x60, 18) 174 CCU_GATE(CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19) 175 CCU_GATE(CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20) 176 CCU_GATE(CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21) 177 CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 23) 178 CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 0x60, 24) 179 CCU_GATE(CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 25) 180 CCU_GATE(CLK_BUS_EHCI2, "bus-ehci2", "ahb2", 0x60, 26) 181 CCU_GATE(CLK_BUS_EHCI3, "bus-ehci3", "ahb2", 0x60, 27) 182 CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 0x60, 28) 183 CCU_GATE(CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 0x60, 29) 184 CCU_GATE(CLK_BUS_OHCI2, "bus-ohci2", "ahb2", 0x60, 30) 185 CCU_GATE(CLK_BUS_OHCI3, "bus-ohci3", "ahb2", 0x60, 31) 186 187 CCU_GATE(CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0) 188 CCU_GATE(CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 3) 189 CCU_GATE(CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 4) 190 CCU_GATE(CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 0x64, 5) 191 CCU_GATE(CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8) 192 CCU_GATE(CLK_BUS_TVE, "bus-tve", "ahb1", 0x64, 9) 193 CCU_GATE(CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11) 194 CCU_GATE(CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12) 195 CCU_GATE(CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20) 196 CCU_GATE(CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21) 197 CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22) 198 199 CCU_GATE(CLK_BUS_CODEC, "bus-codec", "apb1", 0x68, 0) 200 CCU_GATE(CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1) 201 CCU_GATE(CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5) 202 CCU_GATE(CLK_BUS_THS, "bus-ths", "apb1", 0x68, 8) 203 CCU_GATE(CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12) 204 CCU_GATE(CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13) 205 CCU_GATE(CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14) 206 207 CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6c, 0) 208 CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6c, 1) 209 CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6c, 2) 210 CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x6c, 16) 211 CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x6c, 17) 212 CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x6c, 18) 213 CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x6c, 19) 214 CCU_GATE(CLK_BUS_SCR, "bus-scr", "apb2", 0x6c, 20) 215 216 CCU_GATE(CLK_BUS_EPHY, "bus-ephy", "ahb1", 0x70, 0) 217 CCU_GATE(CLK_BUS_DBG, "bus-dbg", "ahb1", 0x70, 7) 218 219 CCU_GATE(CLK_USBPHY0, "usb-phy0", "osc24M", 0xcc, 8) 220 CCU_GATE(CLK_USBPHY1, "usb-phy1", "osc24M", 0xcc, 9) 221 CCU_GATE(CLK_USBPHY2, "usb-phy2", "osc24M", 0xcc, 10) 222 CCU_GATE(CLK_USBPHY3, "usb-phy3", "osc24M", 0xcc, 11) 223 CCU_GATE(CLK_USBOHCI0, "usb-ohci0", "osc24M", 0xcc, 16) 224 CCU_GATE(CLK_USBOHCI1, "usb-ohci1", "osc24M", 0xcc, 17) 225 CCU_GATE(CLK_USBOHCI2, "usb-ohci2", "osc24M", 0xcc, 18) 226 CCU_GATE(CLK_USBOHCI3, "usb-ohci3", "osc24M", 0xcc, 19) 227 228 CCU_GATE(CLK_THS, "ths", "thsdiv", 0x74, 31) 229 CCU_GATE(CLK_I2S0, "i2s0", "i2s0mux", 0xB0, 31) 230 CCU_GATE(CLK_I2S1, "i2s1", "i2s1mux", 0xB4, 31) 231 CCU_GATE(CLK_I2S2, "i2s2", "i2s2mux", 0xB8, 31) 232 233 CCU_GATE(CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0) 234 CCU_GATE(CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1) 235 CCU_GATE(CLK_DRAM_DEINTERLACE, "dram-deinterlace", "dram", 0x100, 2) 236 CCU_GATE(CLK_DRAM_TS, "dram-ts", "dram", 0x100, 3) 237 238 CCU_GATE(CLK_AC_DIG, "ac-dig", "pll_audio", 0x140, 31) 239 240 CCU_GATE(CLK_AVS, "avs", "osc24M", 0x144, 31) 241 242 CCU_GATE(CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 31) 243 244 CCU_GATE(CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x154, 31) 245 }; 246 247 static const char *pll_cpux_parents[] = {"osc24M"}; 248 NKMP_CLK(pll_cpux_clk, 249 CLK_PLL_CPUX, /* id */ 250 "pll_cpux", pll_cpux_parents, /* name, parents */ 251 0x00, /* offset */ 252 8, 5, 0, 0, /* n factor */ 253 4, 2, 0, 0, /* k factor */ 254 0, 2, 0, 0, /* m factor */ 255 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ 256 31, /* gate */ 257 28, 1000, /* lock */ 258 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK | AW_CLK_SCALE_CHANGE); /* flags */ 259 260 static const char *pll_audio_parents[] = {"osc24M"}; 261 NKMP_CLK(pll_audio_clk, 262 CLK_PLL_AUDIO, /* id */ 263 "pll_audio", pll_audio_parents, /* name, parents */ 264 0x08, /* offset */ 265 8, 7, 0, 0, /* n factor */ 266 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 267 0, 5, 0, 0, /* m factor */ 268 16, 4, 0, 0, /* p factor */ 269 31, /* gate */ 270 28, 1000, /* lock */ 271 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ 272 273 static const char *pll_audio_mult_parents[] = {"pll_audio"}; 274 FIXED_CLK(pll_audio_2x_clk, 275 CLK_PLL_AUDIO_2X, /* id */ 276 "pll_audio-2x", /* name */ 277 pll_audio_mult_parents, /* parent */ 278 0, /* freq */ 279 2, /* mult */ 280 1, /* div */ 281 0); /* flags */ 282 FIXED_CLK(pll_audio_4x_clk, 283 CLK_PLL_AUDIO_4X, /* id */ 284 "pll_audio-4x", /* name */ 285 pll_audio_mult_parents, /* parent */ 286 0, /* freq */ 287 4, /* mult */ 288 1, /* div */ 289 0); /* flags */ 290 FIXED_CLK(pll_audio_8x_clk, 291 CLK_PLL_AUDIO_8X, /* id */ 292 "pll_audio-8x", /* name */ 293 pll_audio_mult_parents, /* parent */ 294 0, /* freq */ 295 8, /* mult */ 296 1, /* div */ 297 0); /* flags */ 298 299 static const char *pll_video_parents[] = {"osc24M"}; 300 FRAC_CLK(pll_video_clk, 301 CLK_PLL_VIDEO, /* id */ 302 "pll_video", pll_video_parents, /* name, parents */ 303 0x10, /* offset */ 304 8, 7, 0, 0, /* n factor */ 305 0, 4, 0, 0, /* m factor */ 306 31, 28, 1000, /* gate, lock, lock retries */ 307 AW_CLK_HAS_LOCK, /* flags */ 308 270000000, 297000000, /* freq0, freq1 */ 309 24, 25, /* mode sel, freq sel */ 310 192000000, 600000000); /* min freq, max freq */ 311 312 static const char *pll_ve_parents[] = {"osc24M"}; 313 FRAC_CLK(pll_ve_clk, 314 CLK_PLL_VE, /* id */ 315 "pll_ve", pll_ve_parents, /* name, parents */ 316 0x18, /* offset */ 317 8, 7, 0, 0, /* n factor */ 318 0, 4, 0, 0, /* m factor */ 319 31, 28, 1000, /* gate, lock, lock retries */ 320 AW_CLK_HAS_LOCK, /* flags */ 321 270000000, 297000000, /* freq0, freq1 */ 322 24, 25, /* mode sel, freq sel */ 323 192000000, 600000000); /* min freq, max freq */ 324 325 static const char *pll_ddr_parents[] = {"osc24M"}; 326 NKMP_CLK_WITH_UPDATE(pll_ddr_clk, 327 CLK_PLL_DDR, /* id */ 328 "pll_ddr", pll_ddr_parents, /* name, parents */ 329 0x20, /* offset */ 330 8, 5, 0, 0, /* n factor */ 331 4, 2, 0, 0, /* k factor */ 332 0, 2, 0, 0, /* m factor */ 333 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 334 31, /* gate */ 335 28, 1000, /* lock */ 336 20, /* update */ 337 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ 338 339 static const char *pll_periph0_parents[] = {"osc24M"}; 340 static const char *pll_periph0_2x_parents[] = {"pll_periph0"}; 341 NKMP_CLK(pll_periph0_clk, 342 CLK_PLL_PERIPH0, /* id */ 343 "pll_periph0", pll_periph0_parents, /* name, parents */ 344 0x28, /* offset */ 345 8, 5, 0, 0, /* n factor */ 346 4, 2, 0, 0, /* k factor */ 347 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 348 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 349 31, /* gate */ 350 28, 1000, /* lock */ 351 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ 352 FIXED_CLK(pll_periph0_2x_clk, 353 CLK_PLL_PERIPH0_2X, /* id */ 354 "pll_periph0-2x", /* name */ 355 pll_periph0_2x_parents, /* parent */ 356 0, /* freq */ 357 2, /* mult */ 358 1, /* div */ 359 0); /* flags */ 360 361 static const char *pll_gpu_parents[] = {"osc24M"}; 362 FRAC_CLK(pll_gpu_clk, 363 CLK_PLL_GPU, /* id */ 364 "pll_gpu", pll_gpu_parents, /* name, parents */ 365 0x38, /* offset */ 366 8, 7, 0, 0, /* n factor */ 367 0, 4, 0, 0, /* m factor */ 368 31, 28, 1000, /* gate, lock, lock retries */ 369 AW_CLK_HAS_LOCK, /* flags */ 370 270000000, 297000000, /* freq0, freq1 */ 371 24, 25, /* mode sel, freq sel */ 372 192000000, 600000000); /* min freq, max freq */ 373 374 static const char *pll_periph1_parents[] = {"osc24M"}; 375 NKMP_CLK(pll_periph1_clk, 376 CLK_PLL_PERIPH1, /* id */ 377 "pll_periph1", pll_periph1_parents, /* name, parents */ 378 0x44, /* offset */ 379 8, 5, 0, 0, /* n factor */ 380 4, 2, 0, 0, /* k factor */ 381 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 382 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 383 31, /* gate */ 384 28, 1000, /* lock */ 385 AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ 386 387 static const char *pll_de_parents[] = {"osc24M"}; 388 FRAC_CLK(pll_de_clk, 389 CLK_PLL_DE, /* id */ 390 "pll_de", pll_de_parents, /* name, parents */ 391 0x48, /* offset */ 392 8, 7, 0, 0, /* n factor */ 393 0, 4, 0, 0, /* m factor */ 394 31, 28, 1000, /* gate, lock, lock retries */ 395 AW_CLK_HAS_LOCK, /* flags */ 396 270000000, 297000000, /* freq0, freq1 */ 397 24, 25, /* mode sel, freq sel */ 398 192000000, 600000000); /* min freq, max freq */ 399 400 static const char *cpux_parents[] = {"osc32k", "osc24M", "pll_cpux", "pll_cpux"}; 401 MUX_CLK(cpux_clk, 402 CLK_CPUX, /* id */ 403 "cpux", cpux_parents, /* name, parents */ 404 0x50, 16, 2); /* offset, shift, width */ 405 406 static const char *axi_parents[] = {"cpux"}; 407 DIV_CLK(axi_clk, 408 CLK_AXI, /* id */ 409 "axi", axi_parents, /* name, parents */ 410 0x50, /* offset */ 411 0, 2, /* shift, width */ 412 0, NULL); /* flags, div table */ 413 414 static const char *ahb1_parents[] = {"osc32k", "osc24M", "axi", "pll_periph0"}; 415 PREDIV_CLK(ahb1_clk, CLK_AHB1, /* id */ 416 "ahb1", ahb1_parents, /* name, parents */ 417 0x54, /* offset */ 418 12, 2, /* mux */ 419 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ 420 6, 2, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ 421 12, 2, 3); /* prediv condition */ 422 423 static const char *apb1_parents[] = {"ahb1"}; 424 static struct clk_div_table apb1_div_table[] = { 425 { .value = 0, .divider = 2, }, 426 { .value = 1, .divider = 2, }, 427 { .value = 2, .divider = 4, }, 428 { .value = 3, .divider = 8, }, 429 { }, 430 }; 431 DIV_CLK(apb1_clk, 432 CLK_APB1, /* id */ 433 "apb1", apb1_parents, /* name, parents */ 434 0x54, /* offset */ 435 8, 2, /* shift, width */ 436 CLK_DIV_WITH_TABLE, /* flags */ 437 apb1_div_table); /* div table */ 438 439 static const char *apb2_parents[] = {"osc32k", "osc24M", "pll_periph0", "pll_periph0"}; 440 NM_CLK(apb2_clk, 441 CLK_APB2, /* id */ 442 "apb2", apb2_parents, /* name, parents */ 443 0x58, /* offset */ 444 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 445 0, 5, 0, 0, /* m factor */ 446 24, 2, /* mux */ 447 0, /* gate */ 448 AW_CLK_HAS_MUX); 449 450 static const char *ahb2_parents[] = {"ahb1", "pll_periph0"}; 451 PREDIV_CLK(ahb2_clk, CLK_AHB2, /* id */ 452 "ahb2", ahb2_parents, /* name, parents */ 453 0x5c, /* offset */ 454 0, 2, /* mux */ 455 0, 0, 1, AW_CLK_FACTOR_FIXED, /* div */ 456 0, 0, 2, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */ 457 0, 2, 1); /* prediv condition */ 458 459 static const char *ths_parents[] = {"osc24M"}; 460 static struct clk_div_table ths_div_table[] = { 461 { .value = 0, .divider = 1, }, 462 { .value = 1, .divider = 2, }, 463 { .value = 2, .divider = 4, }, 464 { .value = 3, .divider = 6, }, 465 { }, 466 }; 467 DIV_CLK(thsdiv_clk, 468 0, /* id */ 469 "thsdiv", ths_parents, /* name, parents */ 470 0x74, /* offset */ 471 0, 2, /* shift, width */ 472 CLK_DIV_WITH_TABLE, /* flags */ 473 ths_div_table); /* div table */ 474 475 static const char *mod_parents[] = {"osc24M", "pll_periph0", "pll_periph1"}; 476 NM_CLK(nand_clk, 477 CLK_NAND, "nand", mod_parents, /* id, name, parents */ 478 0x80, /* offset */ 479 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 480 0, 4, 0, 0, /* m factor */ 481 24, 2, /* mux */ 482 31, /* gate */ 483 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ 484 485 NM_CLK(mmc0_clk, 486 CLK_MMC0, "mmc0", mod_parents, /* id, name, parents */ 487 0x88, /* offset */ 488 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 489 0, 4, 0, 0, /* m factor */ 490 24, 2, /* mux */ 491 31, /* gate */ 492 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | 493 AW_CLK_REPARENT); /* flags */ 494 495 NM_CLK(mmc1_clk, 496 CLK_MMC1, "mmc1", mod_parents, /* id, name, parents */ 497 0x8c, /* offset */ 498 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 499 0, 4, 0, 0, /* m factor */ 500 24, 2, /* mux */ 501 31, /* gate */ 502 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | 503 AW_CLK_REPARENT); /* flags */ 504 505 NM_CLK(mmc2_clk, 506 CLK_MMC2, "mmc2", mod_parents, /* id, name, parents */ 507 0x90, /* offset */ 508 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 509 0, 4, 0, 0, /* m factor */ 510 24, 2, /* mux */ 511 31, /* gate */ 512 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | 513 AW_CLK_REPARENT); /* flags */ 514 515 static const char *ts_parents[] = {"osc24M", "pll_periph0"}; 516 NM_CLK(ts_clk, 517 CLK_TS, "ts", ts_parents, /* id, name, parents */ 518 0x98, /* offset */ 519 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 520 0, 4, 0, 0, /* m factor */ 521 24, 2, /* mux */ 522 31, /* gate */ 523 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ 524 525 NM_CLK(ce_clk, 526 CLK_CE, "ce", mod_parents, /* id, name, parents */ 527 0x9C, /* offset */ 528 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 529 0, 4, 0, 0, /* m factor */ 530 24, 2, /* mux */ 531 31, /* gate */ 532 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ 533 534 NM_CLK(spi0_clk, 535 CLK_SPI0, "spi0", mod_parents, /* id, name, parents */ 536 0xA0, /* offset */ 537 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 538 0, 4, 0, 0, /* m factor */ 539 24, 2, /* mux */ 540 31, /* gate */ 541 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | 542 AW_CLK_REPARENT); /* flags */ 543 544 NM_CLK(spi1_clk, 545 CLK_SPI1, "spi1", mod_parents, /* id, name, parents */ 546 0xA4, /* offset */ 547 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 548 0, 4, 0, 0, /* m factor */ 549 24, 2, /* mux */ 550 31, /* gate */ 551 AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | 552 AW_CLK_REPARENT); /* flags */ 553 554 static const char *i2s_parents[] = {"pll_audio-8x", "pll_audio-4x", "pll_audio-2x", "pll_audio"}; 555 MUX_CLK(i2s0mux_clk, 556 0, "i2s0mux", i2s_parents, /* id, name, parents */ 557 0xb0, 16, 2); /* offset, mux shift, mux width */ 558 MUX_CLK(i2s1mux_clk, 559 0, "i2s1mux", i2s_parents, /* id, name, parents */ 560 0xb4, 16, 2); /* offset, mux shift, mux width */ 561 MUX_CLK(i2s2mux_clk, 562 0, "i2s2mux", i2s_parents, /* id, name, parents */ 563 0xb8, 16, 2); /* offset, mux shift, mux width */ 564 565 static const char *spdif_parents[] = {"pll_audio"}; 566 NM_CLK(spdif_clk, 567 CLK_SPDIF, "spdif", spdif_parents, /* id, name, parents */ 568 0xC0, /* offset */ 569 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake); */ 570 0, 4, 0, 0, /* m factor */ 571 0, 0, /* mux */ 572 31, /* gate */ 573 AW_CLK_HAS_GATE); /* flags */ 574 575 static const char *dram_parents[] = {"pll_ddr", "pll_periph0-2x"}; 576 NM_CLK(dram_clk, 577 CLK_DRAM, "dram", dram_parents, /* id, name, parents */ 578 0xF4, /* offset */ 579 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 580 0, 4, 0, 0, /* m factor */ 581 20, 2, /* mux */ 582 0, /* gate */ 583 AW_CLK_HAS_MUX); /* flags */ 584 585 static const char *de_parents[] = {"pll_periph0-2x", "pll_de"}; 586 NM_CLK(de_clk, 587 CLK_DE, "de", de_parents, /* id, name, parents */ 588 0x104, /* offset */ 589 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 590 0, 4, 0, 0, /* m factor */ 591 24, 2, /* mux */ 592 31, /* gate */ 593 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 594 595 static const char *tcon0_parents[] = {"pll_video"}; 596 NM_CLK(tcon0_clk, 597 CLK_TCON0, "tcon0", tcon0_parents, /* id, name, parents */ 598 0x118, /* offset */ 599 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 600 0, 4, 0, 0, /* m factor */ 601 24, 2, /* mux */ 602 31, /* gate */ 603 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 604 605 static const char *tve_parents[] = {"pll_de", "pll_periph1"}; 606 NM_CLK(tve_clk, 607 CLK_TVE, "tve", tve_parents, /* id, name, parents */ 608 0x120, /* offset */ 609 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 610 0, 4, 0, 0, /* m factor */ 611 24, 2, /* mux */ 612 31, /* gate */ 613 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 614 615 static const char *deinterlace_parents[] = {"pll_periph0", "pll_periph1"}; 616 NM_CLK(deinterlace_clk, 617 CLK_DEINTERLACE, "deinterlace", deinterlace_parents, /* id, name, parents */ 618 0x124, /* offset */ 619 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 620 0, 4, 0, 0, /* m factor */ 621 24, 2, /* mux */ 622 31, /* gate */ 623 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 624 625 static const char *csi_sclk_parents[] = {"pll_periph0", "pll_periph1"}; 626 NM_CLK(csi_sclk_clk, 627 CLK_CSI_SCLK, "csi-sclk", csi_sclk_parents, /* id, name, parents */ 628 0x134, /* offset */ 629 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 630 16, 4, 0, 0, /* m factor */ 631 24, 2, /* mux */ 632 31, /* gate */ 633 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 634 635 static const char *csi_mclk_parents[] = {"osc24M", "pll_video", "pll_periph1"}; 636 NM_CLK(csi_mclk_clk, 637 CLK_CSI_MCLK, "csi-mclk", csi_mclk_parents, /* id, name, parents */ 638 0x134, /* offset */ 639 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 640 0, 4, 0, 0, /* m factor */ 641 8, 2, /* mux */ 642 15, /* gate */ 643 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 644 645 static const char *ve_parents[] = {"pll_ve"}; 646 NM_CLK(ve_clk, 647 CLK_VE, "ve", ve_parents, /* id, name, parents */ 648 0x13C, /* offset */ 649 16, 3, 0, 0, /* n factor */ 650 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 651 0, 0, /* mux */ 652 31, /* gate */ 653 AW_CLK_HAS_GATE); /* flags */ 654 655 static const char *hdmi_parents[] = {"pll_video"}; 656 NM_CLK(hdmi_clk, 657 CLK_HDMI, "hdmi", hdmi_parents, /* id, name, parents */ 658 0x150, /* offset */ 659 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 660 0, 4, 0, 0, /* m factor */ 661 24, 2, /* mux */ 662 31, /* gate */ 663 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 664 665 static const char *mbus_parents[] = {"osc24M", "pll_periph0-2x", "pll_ddr"}; 666 NM_CLK(mbus_clk, 667 CLK_MBUS, "mbus", mbus_parents, /* id, name, parents */ 668 0x15C, /* offset */ 669 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 670 0, 3, 0, 0, /* m factor */ 671 24, 2, /* mux */ 672 31, /* gate */ 673 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 674 675 static const char *gpu_parents[] = {"pll_gpu"}; 676 NM_CLK(gpu_clk, 677 CLK_GPU, "gpu", gpu_parents, /* id, name, parents */ 678 0x1A0, /* offset */ 679 0, 2, 0, 0, /* n factor */ 680 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 681 0, 0, /* mux */ 682 31, /* gate */ 683 AW_CLK_HAS_GATE); /* flags */ 684 685 static struct aw_ccung_clk h3_ccu_clks[] = { 686 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_cpux_clk}, 687 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_audio_clk}, 688 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph0_clk}, 689 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph1_clk}, 690 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_clk}, 691 { .type = AW_CLK_FRAC, .clk.frac = &pll_video_clk}, 692 { .type = AW_CLK_FRAC, .clk.frac = &pll_ve_clk}, 693 { .type = AW_CLK_FRAC, .clk.frac = &pll_gpu_clk}, 694 { .type = AW_CLK_FRAC, .clk.frac = &pll_de_clk}, 695 { .type = AW_CLK_NM, .clk.nm = &apb2_clk}, 696 { .type = AW_CLK_NM, .clk.nm = &nand_clk}, 697 { .type = AW_CLK_NM, .clk.nm = &mmc0_clk}, 698 { .type = AW_CLK_NM, .clk.nm = &mmc1_clk}, 699 { .type = AW_CLK_NM, .clk.nm = &mmc2_clk}, 700 { .type = AW_CLK_NM, .clk.nm = &ts_clk}, 701 { .type = AW_CLK_NM, .clk.nm = &ce_clk}, 702 { .type = AW_CLK_NM, .clk.nm = &spi0_clk}, 703 { .type = AW_CLK_NM, .clk.nm = &spi1_clk}, 704 { .type = AW_CLK_NM, .clk.nm = &spdif_clk}, 705 { .type = AW_CLK_NM, .clk.nm = &dram_clk}, 706 { .type = AW_CLK_NM, .clk.nm = &de_clk}, 707 { .type = AW_CLK_NM, .clk.nm = &tcon0_clk}, 708 { .type = AW_CLK_NM, .clk.nm = &tve_clk}, 709 { .type = AW_CLK_NM, .clk.nm = &deinterlace_clk}, 710 { .type = AW_CLK_NM, .clk.nm = &csi_sclk_clk}, 711 { .type = AW_CLK_NM, .clk.nm = &csi_mclk_clk}, 712 { .type = AW_CLK_NM, .clk.nm = &ve_clk}, 713 { .type = AW_CLK_NM, .clk.nm = &hdmi_clk}, 714 { .type = AW_CLK_NM, .clk.nm = &mbus_clk}, 715 { .type = AW_CLK_NM, .clk.nm = &gpu_clk}, 716 { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb1_clk}, 717 { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb2_clk}, 718 { .type = AW_CLK_MUX, .clk.mux = &cpux_clk}, 719 { .type = AW_CLK_MUX, .clk.mux = &i2s0mux_clk}, 720 { .type = AW_CLK_MUX, .clk.mux = &i2s1mux_clk}, 721 { .type = AW_CLK_MUX, .clk.mux = &i2s2mux_clk}, 722 { .type = AW_CLK_DIV, .clk.div = &axi_clk}, 723 { .type = AW_CLK_DIV, .clk.div = &apb1_clk}, 724 { .type = AW_CLK_DIV, .clk.div = &thsdiv_clk}, 725 { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph0_2x_clk}, 726 { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_2x_clk}, 727 { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_4x_clk}, 728 { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_8x_clk}, 729 }; 730 731 static struct aw_clk_init h3_init_clks[] = { 732 {"ahb1", "pll_periph0", 0, false}, 733 {"ahb2", "pll_periph0", 0, false}, 734 {"dram", "pll_ddr", 0, false}, 735 }; 736 737 static struct ofw_compat_data compat_data[] = { 738 #if defined(SOC_ALLWINNER_H3) 739 { "allwinner,sun8i-h3-ccu", 1 }, 740 #endif 741 #if defined(SOC_ALLWINNER_H5) 742 { "allwinner,sun50i-h5-ccu", 1 }, 743 #endif 744 { NULL, 0}, 745 }; 746 747 static int 748 ccu_h3_probe(device_t dev) 749 { 750 751 if (!ofw_bus_status_okay(dev)) 752 return (ENXIO); 753 754 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 755 return (ENXIO); 756 757 device_set_desc(dev, "Allwinner H3/H5 Clock Control Unit NG"); 758 return (BUS_PROBE_DEFAULT); 759 } 760 761 static int 762 ccu_h3_attach(device_t dev) 763 { 764 struct aw_ccung_softc *sc; 765 766 sc = device_get_softc(dev); 767 768 sc->resets = h3_ccu_resets; 769 sc->nresets = nitems(h3_ccu_resets); 770 sc->gates = h3_ccu_gates; 771 sc->ngates = nitems(h3_ccu_gates); 772 sc->clks = h3_ccu_clks; 773 sc->nclks = nitems(h3_ccu_clks); 774 sc->clk_init = h3_init_clks; 775 sc->n_clk_init = nitems(h3_init_clks); 776 777 return (aw_ccung_attach(dev)); 778 } 779 780 static device_method_t ccu_h3ng_methods[] = { 781 /* Device interface */ 782 DEVMETHOD(device_probe, ccu_h3_probe), 783 DEVMETHOD(device_attach, ccu_h3_attach), 784 785 DEVMETHOD_END 786 }; 787 788 DEFINE_CLASS_1(ccu_h3ng, ccu_h3ng_driver, ccu_h3ng_methods, 789 sizeof(struct aw_ccung_softc), aw_ccung_driver); 790 791 EARLY_DRIVER_MODULE(ccu_h3ng, simplebus, ccu_h3ng_driver, 0, 0, 792 BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
Cache object: f4d79ab640ef3a42c7b754dedc8b2d91
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