1 /*-
2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD$
26 */
27
28 /*
29 * Allwinner Gigabit Ethernet MAC (EMAC) controller
30 */
31
32 #include "opt_device_polling.h"
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/bus.h>
40 #include <sys/rman.h>
41 #include <sys/kernel.h>
42 #include <sys/endian.h>
43 #include <sys/mbuf.h>
44 #include <sys/socket.h>
45 #include <sys/sockio.h>
46 #include <sys/module.h>
47 #include <sys/gpio.h>
48
49 #include <net/bpf.h>
50 #include <net/if.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 #include <net/if_types.h>
55 #include <net/if_var.h>
56
57 #include <machine/bus.h>
58
59 #include <dev/ofw/ofw_bus.h>
60 #include <dev/ofw/ofw_bus_subr.h>
61
62 #include <arm/allwinner/if_awgreg.h>
63 #include <arm/allwinner/aw_sid.h>
64 #include <dev/mii/mii.h>
65 #include <dev/mii/miivar.h>
66
67 #include <dev/extres/clk/clk.h>
68 #include <dev/extres/hwreset/hwreset.h>
69 #include <dev/extres/regulator/regulator.h>
70 #include <dev/extres/syscon/syscon.h>
71
72 #include "syscon_if.h"
73 #include "miibus_if.h"
74 #include "gpio_if.h"
75
76 #define RD4(sc, reg) bus_read_4((sc)->res[_RES_EMAC], (reg))
77 #define WR4(sc, reg, val) bus_write_4((sc)->res[_RES_EMAC], (reg), (val))
78
79 #define AWG_LOCK(sc) mtx_lock(&(sc)->mtx)
80 #define AWG_UNLOCK(sc) mtx_unlock(&(sc)->mtx);
81 #define AWG_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
82 #define AWG_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
83
84 #define DESC_ALIGN 4
85 #define TX_DESC_COUNT 1024
86 #define TX_DESC_SIZE (sizeof(struct emac_desc) * TX_DESC_COUNT)
87 #define RX_DESC_COUNT 256
88 #define RX_DESC_SIZE (sizeof(struct emac_desc) * RX_DESC_COUNT)
89
90 #define DESC_OFF(n) ((n) * sizeof(struct emac_desc))
91 #define TX_NEXT(n) (((n) + 1) & (TX_DESC_COUNT - 1))
92 #define TX_SKIP(n, o) (((n) + (o)) & (TX_DESC_COUNT - 1))
93 #define RX_NEXT(n) (((n) + 1) & (RX_DESC_COUNT - 1))
94
95 #define TX_MAX_SEGS 20
96
97 #define SOFT_RST_RETRY 1000
98 #define MII_BUSY_RETRY 1000
99 #define MDIO_FREQ 2500000
100
101 #define BURST_LEN_DEFAULT 8
102 #define RX_TX_PRI_DEFAULT 0
103 #define PAUSE_TIME_DEFAULT 0x400
104 #define TX_INTERVAL_DEFAULT 64
105 #define RX_BATCH_DEFAULT 64
106
107 /* syscon EMAC clock register */
108 #define EMAC_CLK_REG 0x30
109 #define EMAC_CLK_EPHY_ADDR (0x1f << 20) /* H3 */
110 #define EMAC_CLK_EPHY_ADDR_SHIFT 20
111 #define EMAC_CLK_EPHY_LED_POL (1 << 17) /* H3 */
112 #define EMAC_CLK_EPHY_SHUTDOWN (1 << 16) /* H3 */
113 #define EMAC_CLK_EPHY_SELECT (1 << 15) /* H3 */
114 #define EMAC_CLK_RMII_EN (1 << 13)
115 #define EMAC_CLK_ETXDC (0x7 << 10)
116 #define EMAC_CLK_ETXDC_SHIFT 10
117 #define EMAC_CLK_ERXDC (0x1f << 5)
118 #define EMAC_CLK_ERXDC_SHIFT 5
119 #define EMAC_CLK_PIT (0x1 << 2)
120 #define EMAC_CLK_PIT_MII (0 << 2)
121 #define EMAC_CLK_PIT_RGMII (1 << 2)
122 #define EMAC_CLK_SRC (0x3 << 0)
123 #define EMAC_CLK_SRC_MII (0 << 0)
124 #define EMAC_CLK_SRC_EXT_RGMII (1 << 0)
125 #define EMAC_CLK_SRC_RGMII (2 << 0)
126
127 /* Burst length of RX and TX DMA transfers */
128 static int awg_burst_len = BURST_LEN_DEFAULT;
129 TUNABLE_INT("hw.awg.burst_len", &awg_burst_len);
130
131 /* RX / TX DMA priority. If 1, RX DMA has priority over TX DMA. */
132 static int awg_rx_tx_pri = RX_TX_PRI_DEFAULT;
133 TUNABLE_INT("hw.awg.rx_tx_pri", &awg_rx_tx_pri);
134
135 /* Pause time field in the transmitted control frame */
136 static int awg_pause_time = PAUSE_TIME_DEFAULT;
137 TUNABLE_INT("hw.awg.pause_time", &awg_pause_time);
138
139 /* Request a TX interrupt every <n> descriptors */
140 static int awg_tx_interval = TX_INTERVAL_DEFAULT;
141 TUNABLE_INT("hw.awg.tx_interval", &awg_tx_interval);
142
143 /* Maximum number of mbufs to send to if_input */
144 static int awg_rx_batch = RX_BATCH_DEFAULT;
145 TUNABLE_INT("hw.awg.rx_batch", &awg_rx_batch);
146
147 enum awg_type {
148 EMAC_A83T = 1,
149 EMAC_H3,
150 EMAC_A64,
151 };
152
153 static struct ofw_compat_data compat_data[] = {
154 { "allwinner,sun8i-a83t-emac", EMAC_A83T },
155 { "allwinner,sun8i-h3-emac", EMAC_H3 },
156 { "allwinner,sun50i-a64-emac", EMAC_A64 },
157 { NULL, 0 }
158 };
159
160 struct awg_bufmap {
161 bus_dmamap_t map;
162 struct mbuf *mbuf;
163 };
164
165 struct awg_txring {
166 bus_dma_tag_t desc_tag;
167 bus_dmamap_t desc_map;
168 struct emac_desc *desc_ring;
169 bus_addr_t desc_ring_paddr;
170 bus_dma_tag_t buf_tag;
171 struct awg_bufmap buf_map[TX_DESC_COUNT];
172 u_int cur, next, queued;
173 u_int segs;
174 };
175
176 struct awg_rxring {
177 bus_dma_tag_t desc_tag;
178 bus_dmamap_t desc_map;
179 struct emac_desc *desc_ring;
180 bus_addr_t desc_ring_paddr;
181 bus_dma_tag_t buf_tag;
182 struct awg_bufmap buf_map[RX_DESC_COUNT];
183 bus_dmamap_t buf_spare_map;
184 u_int cur;
185 };
186
187 enum {
188 _RES_EMAC,
189 _RES_IRQ,
190 _RES_SYSCON,
191 _RES_NITEMS
192 };
193
194 struct awg_softc {
195 struct resource *res[_RES_NITEMS];
196 struct mtx mtx;
197 if_t ifp;
198 device_t dev;
199 device_t miibus;
200 struct callout stat_ch;
201 void *ih;
202 u_int mdc_div_ratio_m;
203 int link;
204 int if_flags;
205 enum awg_type type;
206 struct syscon *syscon;
207
208 struct awg_txring tx;
209 struct awg_rxring rx;
210 };
211
212 static struct resource_spec awg_spec[] = {
213 { SYS_RES_MEMORY, 0, RF_ACTIVE },
214 { SYS_RES_IRQ, 0, RF_ACTIVE },
215 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL },
216 { -1, 0 }
217 };
218
219 static void awg_txeof(struct awg_softc *sc);
220 static void awg_start_locked(struct awg_softc *sc);
221
222 static void awg_tick(void *softc);
223
224 static int awg_parse_delay(device_t dev, uint32_t *tx_delay,
225 uint32_t *rx_delay);
226 static uint32_t syscon_read_emac_clk_reg(device_t dev);
227 static void syscon_write_emac_clk_reg(device_t dev, uint32_t val);
228 static phandle_t awg_get_phy_node(device_t dev);
229 static bool awg_has_internal_phy(device_t dev);
230
231 /*
232 * MII functions
233 */
234
235 static int
236 awg_miibus_readreg(device_t dev, int phy, int reg)
237 {
238 struct awg_softc *sc;
239 int retry, val;
240
241 sc = device_get_softc(dev);
242 val = 0;
243
244 WR4(sc, EMAC_MII_CMD,
245 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) |
246 (phy << PHY_ADDR_SHIFT) |
247 (reg << PHY_REG_ADDR_SHIFT) |
248 MII_BUSY);
249 for (retry = MII_BUSY_RETRY; retry > 0; retry--) {
250 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0) {
251 val = RD4(sc, EMAC_MII_DATA);
252 break;
253 }
254 DELAY(10);
255 }
256
257 if (retry == 0)
258 device_printf(dev, "phy read timeout, phy=%d reg=%d\n",
259 phy, reg);
260
261 return (val);
262 }
263
264 static int
265 awg_miibus_writereg(device_t dev, int phy, int reg, int val)
266 {
267 struct awg_softc *sc;
268 int retry;
269
270 sc = device_get_softc(dev);
271
272 WR4(sc, EMAC_MII_DATA, val);
273 WR4(sc, EMAC_MII_CMD,
274 (sc->mdc_div_ratio_m << MDC_DIV_RATIO_M_SHIFT) |
275 (phy << PHY_ADDR_SHIFT) |
276 (reg << PHY_REG_ADDR_SHIFT) |
277 MII_WR | MII_BUSY);
278 for (retry = MII_BUSY_RETRY; retry > 0; retry--) {
279 if ((RD4(sc, EMAC_MII_CMD) & MII_BUSY) == 0)
280 break;
281 DELAY(10);
282 }
283
284 if (retry == 0)
285 device_printf(dev, "phy write timeout, phy=%d reg=%d\n",
286 phy, reg);
287
288 return (0);
289 }
290
291 static void
292 awg_miibus_statchg(device_t dev)
293 {
294 struct awg_softc *sc;
295 struct mii_data *mii;
296 uint32_t val;
297
298 sc = device_get_softc(dev);
299
300 AWG_ASSERT_LOCKED(sc);
301
302 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) == 0)
303 return;
304 mii = device_get_softc(sc->miibus);
305
306 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
307 (IFM_ACTIVE | IFM_AVALID)) {
308 switch (IFM_SUBTYPE(mii->mii_media_active)) {
309 case IFM_1000_T:
310 case IFM_1000_SX:
311 case IFM_100_TX:
312 case IFM_10_T:
313 sc->link = 1;
314 break;
315 default:
316 sc->link = 0;
317 break;
318 }
319 } else
320 sc->link = 0;
321
322 if (sc->link == 0)
323 return;
324
325 val = RD4(sc, EMAC_BASIC_CTL_0);
326 val &= ~(BASIC_CTL_SPEED | BASIC_CTL_DUPLEX);
327
328 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
329 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
330 val |= BASIC_CTL_SPEED_1000 << BASIC_CTL_SPEED_SHIFT;
331 else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX)
332 val |= BASIC_CTL_SPEED_100 << BASIC_CTL_SPEED_SHIFT;
333 else
334 val |= BASIC_CTL_SPEED_10 << BASIC_CTL_SPEED_SHIFT;
335
336 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
337 val |= BASIC_CTL_DUPLEX;
338
339 WR4(sc, EMAC_BASIC_CTL_0, val);
340
341 val = RD4(sc, EMAC_RX_CTL_0);
342 val &= ~RX_FLOW_CTL_EN;
343 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
344 val |= RX_FLOW_CTL_EN;
345 WR4(sc, EMAC_RX_CTL_0, val);
346
347 val = RD4(sc, EMAC_TX_FLOW_CTL);
348 val &= ~(PAUSE_TIME|TX_FLOW_CTL_EN);
349 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
350 val |= TX_FLOW_CTL_EN;
351 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
352 val |= awg_pause_time << PAUSE_TIME_SHIFT;
353 WR4(sc, EMAC_TX_FLOW_CTL, val);
354 }
355
356 /*
357 * Media functions
358 */
359
360 static void
361 awg_media_status(if_t ifp, struct ifmediareq *ifmr)
362 {
363 struct awg_softc *sc;
364 struct mii_data *mii;
365
366 sc = if_getsoftc(ifp);
367 mii = device_get_softc(sc->miibus);
368
369 AWG_LOCK(sc);
370 mii_pollstat(mii);
371 ifmr->ifm_active = mii->mii_media_active;
372 ifmr->ifm_status = mii->mii_media_status;
373 AWG_UNLOCK(sc);
374 }
375
376 static int
377 awg_media_change(if_t ifp)
378 {
379 struct awg_softc *sc;
380 struct mii_data *mii;
381 int error;
382
383 sc = if_getsoftc(ifp);
384 mii = device_get_softc(sc->miibus);
385
386 AWG_LOCK(sc);
387 error = mii_mediachg(mii);
388 AWG_UNLOCK(sc);
389
390 return (error);
391 }
392
393 /*
394 * Core functions
395 */
396
397 /* Bit Reversal - http://aggregate.org/MAGIC/#Bit%20Reversal */
398 static uint32_t
399 bitrev32(uint32_t x)
400 {
401 x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1));
402 x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2));
403 x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4));
404 x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8));
405
406 return (x >> 16) | (x << 16);
407 }
408
409 static u_int
410 awg_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
411 {
412 uint32_t crc, hashreg, hashbit, *hash = arg;
413
414 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0x7f;
415 crc = bitrev32(~crc) >> 26;
416 hashreg = (crc >> 5);
417 hashbit = (crc & 0x1f);
418 hash[hashreg] |= (1 << hashbit);
419
420 return (1);
421 }
422
423 static void
424 awg_setup_rxfilter(struct awg_softc *sc)
425 {
426 uint32_t val, hash[2], machi, maclo;
427 uint8_t *eaddr;
428 if_t ifp;
429
430 AWG_ASSERT_LOCKED(sc);
431
432 ifp = sc->ifp;
433 val = 0;
434 hash[0] = hash[1] = 0;
435
436 if (if_getflags(ifp) & IFF_PROMISC)
437 val |= DIS_ADDR_FILTER;
438 else if (if_getflags(ifp) & IFF_ALLMULTI) {
439 val |= RX_ALL_MULTICAST;
440 hash[0] = hash[1] = ~0;
441 } else if (if_foreach_llmaddr(ifp, awg_hash_maddr, hash) > 0)
442 val |= HASH_MULTICAST;
443
444 /* Write our unicast address */
445 eaddr = IF_LLADDR(ifp);
446 machi = (eaddr[5] << 8) | eaddr[4];
447 maclo = (eaddr[3] << 24) | (eaddr[2] << 16) | (eaddr[1] << 8) |
448 (eaddr[0] << 0);
449 WR4(sc, EMAC_ADDR_HIGH(0), machi);
450 WR4(sc, EMAC_ADDR_LOW(0), maclo);
451
452 /* Multicast hash filters */
453 WR4(sc, EMAC_RX_HASH_0, hash[1]);
454 WR4(sc, EMAC_RX_HASH_1, hash[0]);
455
456 /* RX frame filter config */
457 WR4(sc, EMAC_RX_FRM_FLT, val);
458 }
459
460 static void
461 awg_setup_core(struct awg_softc *sc)
462 {
463 uint32_t val;
464
465 AWG_ASSERT_LOCKED(sc);
466 /* Configure DMA burst length and priorities */
467 val = awg_burst_len << BASIC_CTL_BURST_LEN_SHIFT;
468 if (awg_rx_tx_pri)
469 val |= BASIC_CTL_RX_TX_PRI;
470 WR4(sc, EMAC_BASIC_CTL_1, val);
471
472 }
473
474 static void
475 awg_enable_mac(struct awg_softc *sc, bool enable)
476 {
477 uint32_t tx, rx;
478
479 AWG_ASSERT_LOCKED(sc);
480
481 tx = RD4(sc, EMAC_TX_CTL_0);
482 rx = RD4(sc, EMAC_RX_CTL_0);
483 if (enable) {
484 tx |= TX_EN;
485 rx |= RX_EN | CHECK_CRC;
486 } else {
487 tx &= ~TX_EN;
488 rx &= ~(RX_EN | CHECK_CRC);
489 }
490
491 WR4(sc, EMAC_TX_CTL_0, tx);
492 WR4(sc, EMAC_RX_CTL_0, rx);
493 }
494
495 static void
496 awg_get_eaddr(device_t dev, uint8_t *eaddr)
497 {
498 struct awg_softc *sc;
499 uint32_t maclo, machi, rnd;
500 u_char rootkey[16];
501 uint32_t rootkey_size;
502
503 sc = device_get_softc(dev);
504
505 machi = RD4(sc, EMAC_ADDR_HIGH(0)) & 0xffff;
506 maclo = RD4(sc, EMAC_ADDR_LOW(0));
507
508 rootkey_size = sizeof(rootkey);
509 if (maclo == 0xffffffff && machi == 0xffff) {
510 /* MAC address in hardware is invalid, create one */
511 if (aw_sid_get_fuse(AW_SID_FUSE_ROOTKEY, rootkey,
512 &rootkey_size) == 0 &&
513 (rootkey[3] | rootkey[12] | rootkey[13] | rootkey[14] |
514 rootkey[15]) != 0) {
515 /* MAC address is derived from the root key in SID */
516 maclo = (rootkey[13] << 24) | (rootkey[12] << 16) |
517 (rootkey[3] << 8) | 0x02;
518 machi = (rootkey[15] << 8) | rootkey[14];
519 } else {
520 /* Create one */
521 rnd = arc4random();
522 maclo = 0x00f2 | (rnd & 0xffff0000);
523 machi = rnd & 0xffff;
524 }
525 }
526
527 eaddr[0] = maclo & 0xff;
528 eaddr[1] = (maclo >> 8) & 0xff;
529 eaddr[2] = (maclo >> 16) & 0xff;
530 eaddr[3] = (maclo >> 24) & 0xff;
531 eaddr[4] = machi & 0xff;
532 eaddr[5] = (machi >> 8) & 0xff;
533 }
534
535 /*
536 * DMA functions
537 */
538
539 static void
540 awg_enable_dma_intr(struct awg_softc *sc)
541 {
542 /* Enable interrupts */
543 WR4(sc, EMAC_INT_EN, RX_INT_EN | TX_INT_EN | TX_BUF_UA_INT_EN);
544 }
545
546 static void
547 awg_disable_dma_intr(struct awg_softc *sc)
548 {
549 /* Disable interrupts */
550 WR4(sc, EMAC_INT_EN, 0);
551 }
552
553 static void
554 awg_init_dma(struct awg_softc *sc)
555 {
556 uint32_t val;
557
558 AWG_ASSERT_LOCKED(sc);
559
560 /* Enable interrupts */
561 #ifdef DEVICE_POLLING
562 if ((if_getcapenable(sc->ifp) & IFCAP_POLLING) == 0)
563 awg_enable_dma_intr(sc);
564 else
565 awg_disable_dma_intr(sc);
566 #else
567 awg_enable_dma_intr(sc);
568 #endif
569
570 /* Enable transmit DMA */
571 val = RD4(sc, EMAC_TX_CTL_1);
572 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_EN | TX_MD | TX_NEXT_FRAME);
573
574 /* Enable receive DMA */
575 val = RD4(sc, EMAC_RX_CTL_1);
576 WR4(sc, EMAC_RX_CTL_1, val | RX_DMA_EN | RX_MD);
577 }
578
579 static void
580 awg_stop_dma(struct awg_softc *sc)
581 {
582 uint32_t val;
583
584 AWG_ASSERT_LOCKED(sc);
585
586 /* Stop transmit DMA and flush data in the TX FIFO */
587 val = RD4(sc, EMAC_TX_CTL_1);
588 val &= ~TX_DMA_EN;
589 val |= FLUSH_TX_FIFO;
590 WR4(sc, EMAC_TX_CTL_1, val);
591
592 /* Disable interrupts */
593 awg_disable_dma_intr(sc);
594
595 /* Disable transmit DMA */
596 val = RD4(sc, EMAC_TX_CTL_1);
597 WR4(sc, EMAC_TX_CTL_1, val & ~TX_DMA_EN);
598
599 /* Disable receive DMA */
600 val = RD4(sc, EMAC_RX_CTL_1);
601 WR4(sc, EMAC_RX_CTL_1, val & ~RX_DMA_EN);
602 }
603
604 static int
605 awg_encap(struct awg_softc *sc, struct mbuf **mp)
606 {
607 bus_dmamap_t map;
608 bus_dma_segment_t segs[TX_MAX_SEGS];
609 int error, nsegs, cur, first, last, i;
610 u_int csum_flags;
611 uint32_t flags, status;
612 struct mbuf *m;
613
614 cur = first = sc->tx.cur;
615 map = sc->tx.buf_map[first].map;
616
617 m = *mp;
618 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m, segs,
619 &nsegs, BUS_DMA_NOWAIT);
620 if (error == EFBIG) {
621 m = m_collapse(m, M_NOWAIT, TX_MAX_SEGS);
622 if (m == NULL) {
623 device_printf(sc->dev, "awg_encap: m_collapse failed\n");
624 m_freem(*mp);
625 *mp = NULL;
626 return (ENOMEM);
627 }
628 *mp = m;
629 error = bus_dmamap_load_mbuf_sg(sc->tx.buf_tag, map, m,
630 segs, &nsegs, BUS_DMA_NOWAIT);
631 if (error != 0) {
632 m_freem(*mp);
633 *mp = NULL;
634 }
635 }
636 if (error != 0) {
637 device_printf(sc->dev, "awg_encap: bus_dmamap_load_mbuf_sg failed\n");
638 return (error);
639 }
640 if (nsegs == 0) {
641 m_freem(*mp);
642 *mp = NULL;
643 return (EIO);
644 }
645
646 if (sc->tx.queued + nsegs > TX_DESC_COUNT) {
647 bus_dmamap_unload(sc->tx.buf_tag, map);
648 return (ENOBUFS);
649 }
650
651 bus_dmamap_sync(sc->tx.buf_tag, map, BUS_DMASYNC_PREWRITE);
652
653 flags = TX_FIR_DESC;
654 status = 0;
655 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) {
656 if ((m->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_UDP)) != 0)
657 csum_flags = TX_CHECKSUM_CTL_FULL;
658 else
659 csum_flags = TX_CHECKSUM_CTL_IP;
660 flags |= (csum_flags << TX_CHECKSUM_CTL_SHIFT);
661 }
662
663 for (i = 0; i < nsegs; i++) {
664 sc->tx.segs++;
665 if (i == nsegs - 1) {
666 flags |= TX_LAST_DESC;
667 /*
668 * Can only request TX completion
669 * interrupt on last descriptor.
670 */
671 if (sc->tx.segs >= awg_tx_interval) {
672 sc->tx.segs = 0;
673 flags |= TX_INT_CTL;
674 }
675 }
676
677 sc->tx.desc_ring[cur].addr = htole32((uint32_t)segs[i].ds_addr);
678 sc->tx.desc_ring[cur].size = htole32(flags | segs[i].ds_len);
679 sc->tx.desc_ring[cur].status = htole32(status);
680
681 flags &= ~TX_FIR_DESC;
682 /*
683 * Setting of the valid bit in the first descriptor is
684 * deferred until the whole chain is fully set up.
685 */
686 status = TX_DESC_CTL;
687
688 ++sc->tx.queued;
689 cur = TX_NEXT(cur);
690 }
691
692 sc->tx.cur = cur;
693
694 /* Store mapping and mbuf in the last segment */
695 last = TX_SKIP(cur, TX_DESC_COUNT - 1);
696 sc->tx.buf_map[first].map = sc->tx.buf_map[last].map;
697 sc->tx.buf_map[last].map = map;
698 sc->tx.buf_map[last].mbuf = m;
699
700 /*
701 * The whole mbuf chain has been DMA mapped,
702 * fix the first descriptor.
703 */
704 sc->tx.desc_ring[first].status = htole32(TX_DESC_CTL);
705
706 return (0);
707 }
708
709 static void
710 awg_clean_txbuf(struct awg_softc *sc, int index)
711 {
712 struct awg_bufmap *bmap;
713
714 --sc->tx.queued;
715
716 bmap = &sc->tx.buf_map[index];
717 if (bmap->mbuf != NULL) {
718 bus_dmamap_sync(sc->tx.buf_tag, bmap->map,
719 BUS_DMASYNC_POSTWRITE);
720 bus_dmamap_unload(sc->tx.buf_tag, bmap->map);
721 m_freem(bmap->mbuf);
722 bmap->mbuf = NULL;
723 }
724 }
725
726 static void
727 awg_setup_rxdesc(struct awg_softc *sc, int index, bus_addr_t paddr)
728 {
729 uint32_t status, size;
730
731 status = RX_DESC_CTL;
732 size = MCLBYTES - 1;
733
734 sc->rx.desc_ring[index].addr = htole32((uint32_t)paddr);
735 sc->rx.desc_ring[index].size = htole32(size);
736 sc->rx.desc_ring[index].status = htole32(status);
737 }
738
739 static void
740 awg_reuse_rxdesc(struct awg_softc *sc, int index)
741 {
742
743 sc->rx.desc_ring[index].status = htole32(RX_DESC_CTL);
744 }
745
746 static int
747 awg_newbuf_rx(struct awg_softc *sc, int index)
748 {
749 struct mbuf *m;
750 bus_dma_segment_t seg;
751 bus_dmamap_t map;
752 int nsegs;
753
754 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
755 if (m == NULL)
756 return (ENOBUFS);
757
758 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
759 m_adj(m, ETHER_ALIGN);
760
761 if (bus_dmamap_load_mbuf_sg(sc->rx.buf_tag, sc->rx.buf_spare_map,
762 m, &seg, &nsegs, BUS_DMA_NOWAIT) != 0) {
763 m_freem(m);
764 return (ENOBUFS);
765 }
766
767 if (sc->rx.buf_map[index].mbuf != NULL) {
768 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map,
769 BUS_DMASYNC_POSTREAD);
770 bus_dmamap_unload(sc->rx.buf_tag, sc->rx.buf_map[index].map);
771 }
772 map = sc->rx.buf_map[index].map;
773 sc->rx.buf_map[index].map = sc->rx.buf_spare_map;
774 sc->rx.buf_spare_map = map;
775 bus_dmamap_sync(sc->rx.buf_tag, sc->rx.buf_map[index].map,
776 BUS_DMASYNC_PREREAD);
777
778 sc->rx.buf_map[index].mbuf = m;
779 awg_setup_rxdesc(sc, index, seg.ds_addr);
780
781 return (0);
782 }
783
784 static void
785 awg_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
786 {
787 if (error != 0)
788 return;
789 *(bus_addr_t *)arg = segs[0].ds_addr;
790 }
791
792 static int
793 awg_setup_dma(device_t dev)
794 {
795 struct awg_softc *sc;
796 int error, i;
797
798 sc = device_get_softc(dev);
799
800 /* Setup TX ring */
801 error = bus_dma_tag_create(
802 bus_get_dma_tag(dev), /* Parent tag */
803 DESC_ALIGN, 0, /* alignment, boundary */
804 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
805 BUS_SPACE_MAXADDR, /* highaddr */
806 NULL, NULL, /* filter, filterarg */
807 TX_DESC_SIZE, 1, /* maxsize, nsegs */
808 TX_DESC_SIZE, /* maxsegsize */
809 0, /* flags */
810 NULL, NULL, /* lockfunc, lockarg */
811 &sc->tx.desc_tag);
812 if (error != 0) {
813 device_printf(dev, "cannot create TX descriptor ring tag\n");
814 return (error);
815 }
816
817 error = bus_dmamem_alloc(sc->tx.desc_tag, (void **)&sc->tx.desc_ring,
818 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->tx.desc_map);
819 if (error != 0) {
820 device_printf(dev, "cannot allocate TX descriptor ring\n");
821 return (error);
822 }
823
824 error = bus_dmamap_load(sc->tx.desc_tag, sc->tx.desc_map,
825 sc->tx.desc_ring, TX_DESC_SIZE, awg_dmamap_cb,
826 &sc->tx.desc_ring_paddr, 0);
827 if (error != 0) {
828 device_printf(dev, "cannot load TX descriptor ring\n");
829 return (error);
830 }
831
832 for (i = 0; i < TX_DESC_COUNT; i++)
833 sc->tx.desc_ring[i].next =
834 htole32(sc->tx.desc_ring_paddr + DESC_OFF(TX_NEXT(i)));
835
836 error = bus_dma_tag_create(
837 bus_get_dma_tag(dev), /* Parent tag */
838 1, 0, /* alignment, boundary */
839 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
840 BUS_SPACE_MAXADDR, /* highaddr */
841 NULL, NULL, /* filter, filterarg */
842 MCLBYTES, TX_MAX_SEGS, /* maxsize, nsegs */
843 MCLBYTES, /* maxsegsize */
844 0, /* flags */
845 NULL, NULL, /* lockfunc, lockarg */
846 &sc->tx.buf_tag);
847 if (error != 0) {
848 device_printf(dev, "cannot create TX buffer tag\n");
849 return (error);
850 }
851
852 sc->tx.queued = 0;
853 for (i = 0; i < TX_DESC_COUNT; i++) {
854 error = bus_dmamap_create(sc->tx.buf_tag, 0,
855 &sc->tx.buf_map[i].map);
856 if (error != 0) {
857 device_printf(dev, "cannot create TX buffer map\n");
858 return (error);
859 }
860 }
861
862 /* Setup RX ring */
863 error = bus_dma_tag_create(
864 bus_get_dma_tag(dev), /* Parent tag */
865 DESC_ALIGN, 0, /* alignment, boundary */
866 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
867 BUS_SPACE_MAXADDR, /* highaddr */
868 NULL, NULL, /* filter, filterarg */
869 RX_DESC_SIZE, 1, /* maxsize, nsegs */
870 RX_DESC_SIZE, /* maxsegsize */
871 0, /* flags */
872 NULL, NULL, /* lockfunc, lockarg */
873 &sc->rx.desc_tag);
874 if (error != 0) {
875 device_printf(dev, "cannot create RX descriptor ring tag\n");
876 return (error);
877 }
878
879 error = bus_dmamem_alloc(sc->rx.desc_tag, (void **)&sc->rx.desc_ring,
880 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rx.desc_map);
881 if (error != 0) {
882 device_printf(dev, "cannot allocate RX descriptor ring\n");
883 return (error);
884 }
885
886 error = bus_dmamap_load(sc->rx.desc_tag, sc->rx.desc_map,
887 sc->rx.desc_ring, RX_DESC_SIZE, awg_dmamap_cb,
888 &sc->rx.desc_ring_paddr, 0);
889 if (error != 0) {
890 device_printf(dev, "cannot load RX descriptor ring\n");
891 return (error);
892 }
893
894 error = bus_dma_tag_create(
895 bus_get_dma_tag(dev), /* Parent tag */
896 1, 0, /* alignment, boundary */
897 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
898 BUS_SPACE_MAXADDR, /* highaddr */
899 NULL, NULL, /* filter, filterarg */
900 MCLBYTES, 1, /* maxsize, nsegs */
901 MCLBYTES, /* maxsegsize */
902 0, /* flags */
903 NULL, NULL, /* lockfunc, lockarg */
904 &sc->rx.buf_tag);
905 if (error != 0) {
906 device_printf(dev, "cannot create RX buffer tag\n");
907 return (error);
908 }
909
910 error = bus_dmamap_create(sc->rx.buf_tag, 0, &sc->rx.buf_spare_map);
911 if (error != 0) {
912 device_printf(dev,
913 "cannot create RX buffer spare map\n");
914 return (error);
915 }
916
917 for (i = 0; i < RX_DESC_COUNT; i++) {
918 sc->rx.desc_ring[i].next =
919 htole32(sc->rx.desc_ring_paddr + DESC_OFF(RX_NEXT(i)));
920
921 error = bus_dmamap_create(sc->rx.buf_tag, 0,
922 &sc->rx.buf_map[i].map);
923 if (error != 0) {
924 device_printf(dev, "cannot create RX buffer map\n");
925 return (error);
926 }
927 sc->rx.buf_map[i].mbuf = NULL;
928 error = awg_newbuf_rx(sc, i);
929 if (error != 0) {
930 device_printf(dev, "cannot create RX buffer\n");
931 return (error);
932 }
933 }
934 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
935 BUS_DMASYNC_PREWRITE);
936
937 /* Write transmit and receive descriptor base address registers */
938 WR4(sc, EMAC_TX_DMA_LIST, sc->tx.desc_ring_paddr);
939 WR4(sc, EMAC_RX_DMA_LIST, sc->rx.desc_ring_paddr);
940
941 return (0);
942 }
943
944 static void
945 awg_dma_start_tx(struct awg_softc *sc)
946 {
947 uint32_t val;
948
949 AWG_ASSERT_LOCKED(sc);
950
951 /* Start and run TX DMA */
952 val = RD4(sc, EMAC_TX_CTL_1);
953 WR4(sc, EMAC_TX_CTL_1, val | TX_DMA_START);
954 }
955
956 /*
957 * if_ functions
958 */
959
960 static void
961 awg_start_locked(struct awg_softc *sc)
962 {
963 struct mbuf *m;
964 if_t ifp;
965 int cnt, err;
966
967 AWG_ASSERT_LOCKED(sc);
968
969 if (!sc->link)
970 return;
971
972 ifp = sc->ifp;
973
974 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) !=
975 IFF_DRV_RUNNING)
976 return;
977
978 for (cnt = 0; ; cnt++) {
979 m = if_dequeue(ifp);
980 if (m == NULL)
981 break;
982
983 err = awg_encap(sc, &m);
984 if (err != 0) {
985 if (err == ENOBUFS)
986 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
987 if (m != NULL)
988 if_sendq_prepend(ifp, m);
989 break;
990 }
991 if_bpfmtap(ifp, m);
992 }
993
994 if (cnt != 0) {
995 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map,
996 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
997
998 awg_dma_start_tx(sc);
999 }
1000 }
1001
1002 static void
1003 awg_start(if_t ifp)
1004 {
1005 struct awg_softc *sc;
1006
1007 sc = if_getsoftc(ifp);
1008
1009 AWG_LOCK(sc);
1010 awg_start_locked(sc);
1011 AWG_UNLOCK(sc);
1012 }
1013
1014 static void
1015 awg_init_locked(struct awg_softc *sc)
1016 {
1017 struct mii_data *mii;
1018 if_t ifp;
1019
1020 mii = device_get_softc(sc->miibus);
1021 ifp = sc->ifp;
1022
1023 AWG_ASSERT_LOCKED(sc);
1024
1025 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1026 return;
1027
1028 awg_setup_rxfilter(sc);
1029 awg_setup_core(sc);
1030 awg_enable_mac(sc, true);
1031 awg_init_dma(sc);
1032
1033 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
1034
1035 mii_mediachg(mii);
1036 callout_reset(&sc->stat_ch, hz, awg_tick, sc);
1037 }
1038
1039 static void
1040 awg_init(void *softc)
1041 {
1042 struct awg_softc *sc;
1043
1044 sc = softc;
1045
1046 AWG_LOCK(sc);
1047 awg_init_locked(sc);
1048 AWG_UNLOCK(sc);
1049 }
1050
1051 static void
1052 awg_stop(struct awg_softc *sc)
1053 {
1054 if_t ifp;
1055 uint32_t val;
1056 int i;
1057
1058 AWG_ASSERT_LOCKED(sc);
1059
1060 ifp = sc->ifp;
1061
1062 callout_stop(&sc->stat_ch);
1063
1064 awg_stop_dma(sc);
1065 awg_enable_mac(sc, false);
1066
1067 sc->link = 0;
1068
1069 /* Finish handling transmitted buffers */
1070 awg_txeof(sc);
1071
1072 /* Release any untransmitted buffers. */
1073 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) {
1074 val = le32toh(sc->tx.desc_ring[i].status);
1075 if ((val & TX_DESC_CTL) != 0)
1076 break;
1077 awg_clean_txbuf(sc, i);
1078 }
1079 sc->tx.next = i;
1080 for (; sc->tx.queued > 0; i = TX_NEXT(i)) {
1081 sc->tx.desc_ring[i].status = 0;
1082 awg_clean_txbuf(sc, i);
1083 }
1084 sc->tx.cur = sc->tx.next;
1085 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map,
1086 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1087
1088 /* Setup RX buffers for reuse */
1089 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1090 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1091
1092 for (i = sc->rx.cur; ; i = RX_NEXT(i)) {
1093 val = le32toh(sc->rx.desc_ring[i].status);
1094 if ((val & RX_DESC_CTL) != 0)
1095 break;
1096 awg_reuse_rxdesc(sc, i);
1097 }
1098 sc->rx.cur = i;
1099 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1100 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1101
1102 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1103 }
1104
1105 static int
1106 awg_ioctl(if_t ifp, u_long cmd, caddr_t data)
1107 {
1108 struct awg_softc *sc;
1109 struct mii_data *mii;
1110 struct ifreq *ifr;
1111 int flags, mask, error;
1112
1113 sc = if_getsoftc(ifp);
1114 mii = device_get_softc(sc->miibus);
1115 ifr = (struct ifreq *)data;
1116 error = 0;
1117
1118 switch (cmd) {
1119 case SIOCSIFFLAGS:
1120 AWG_LOCK(sc);
1121 if (if_getflags(ifp) & IFF_UP) {
1122 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1123 flags = if_getflags(ifp) ^ sc->if_flags;
1124 if ((flags & (IFF_PROMISC|IFF_ALLMULTI)) != 0)
1125 awg_setup_rxfilter(sc);
1126 } else
1127 awg_init_locked(sc);
1128 } else {
1129 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
1130 awg_stop(sc);
1131 }
1132 sc->if_flags = if_getflags(ifp);
1133 AWG_UNLOCK(sc);
1134 break;
1135 case SIOCADDMULTI:
1136 case SIOCDELMULTI:
1137 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
1138 AWG_LOCK(sc);
1139 awg_setup_rxfilter(sc);
1140 AWG_UNLOCK(sc);
1141 }
1142 break;
1143 case SIOCSIFMEDIA:
1144 case SIOCGIFMEDIA:
1145 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1146 break;
1147 case SIOCSIFCAP:
1148 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1149 #ifdef DEVICE_POLLING
1150 if (mask & IFCAP_POLLING) {
1151 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
1152 error = ether_poll_register(awg_poll, ifp);
1153 if (error != 0)
1154 break;
1155 AWG_LOCK(sc);
1156 awg_disable_dma_intr(sc);
1157 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
1158 AWG_UNLOCK(sc);
1159 } else {
1160 error = ether_poll_deregister(ifp);
1161 AWG_LOCK(sc);
1162 awg_enable_dma_intr(sc);
1163 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
1164 AWG_UNLOCK(sc);
1165 }
1166 }
1167 #endif
1168 if (mask & IFCAP_VLAN_MTU)
1169 if_togglecapenable(ifp, IFCAP_VLAN_MTU);
1170 if (mask & IFCAP_RXCSUM)
1171 if_togglecapenable(ifp, IFCAP_RXCSUM);
1172 if (mask & IFCAP_TXCSUM)
1173 if_togglecapenable(ifp, IFCAP_TXCSUM);
1174 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
1175 if_sethwassistbits(ifp, CSUM_IP | CSUM_UDP | CSUM_TCP, 0);
1176 else
1177 if_sethwassistbits(ifp, 0, CSUM_IP | CSUM_UDP | CSUM_TCP);
1178 break;
1179 default:
1180 error = ether_ioctl(ifp, cmd, data);
1181 break;
1182 }
1183
1184 return (error);
1185 }
1186
1187 /*
1188 * Interrupts functions
1189 */
1190
1191 static int
1192 awg_rxintr(struct awg_softc *sc)
1193 {
1194 if_t ifp;
1195 struct mbuf *m, *mh, *mt;
1196 int error, index, len, cnt, npkt;
1197 uint32_t status;
1198
1199 ifp = sc->ifp;
1200 mh = mt = NULL;
1201 cnt = 0;
1202 npkt = 0;
1203
1204 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1205 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1206
1207 for (index = sc->rx.cur; ; index = RX_NEXT(index)) {
1208 status = le32toh(sc->rx.desc_ring[index].status);
1209 if ((status & RX_DESC_CTL) != 0)
1210 break;
1211
1212 len = (status & RX_FRM_LEN) >> RX_FRM_LEN_SHIFT;
1213
1214 if (len == 0) {
1215 if ((status & (RX_NO_ENOUGH_BUF_ERR | RX_OVERFLOW_ERR)) != 0)
1216 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1217 awg_reuse_rxdesc(sc, index);
1218 continue;
1219 }
1220
1221 m = sc->rx.buf_map[index].mbuf;
1222
1223 error = awg_newbuf_rx(sc, index);
1224 if (error != 0) {
1225 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1226 awg_reuse_rxdesc(sc, index);
1227 continue;
1228 }
1229
1230 m->m_pkthdr.rcvif = ifp;
1231 m->m_pkthdr.len = len;
1232 m->m_len = len;
1233 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1234
1235 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 &&
1236 (status & RX_FRM_TYPE) != 0) {
1237 m->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
1238 if ((status & RX_HEADER_ERR) == 0)
1239 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1240 if ((status & RX_PAYLOAD_ERR) == 0) {
1241 m->m_pkthdr.csum_flags |=
1242 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1243 m->m_pkthdr.csum_data = 0xffff;
1244 }
1245 }
1246
1247 m->m_nextpkt = NULL;
1248 if (mh == NULL)
1249 mh = m;
1250 else
1251 mt->m_nextpkt = m;
1252 mt = m;
1253 ++cnt;
1254 ++npkt;
1255
1256 if (cnt == awg_rx_batch) {
1257 AWG_UNLOCK(sc);
1258 if_input(ifp, mh);
1259 AWG_LOCK(sc);
1260 mh = mt = NULL;
1261 cnt = 0;
1262 }
1263 }
1264
1265 if (index != sc->rx.cur) {
1266 bus_dmamap_sync(sc->rx.desc_tag, sc->rx.desc_map,
1267 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1268 }
1269
1270 if (mh != NULL) {
1271 AWG_UNLOCK(sc);
1272 if_input(ifp, mh);
1273 AWG_LOCK(sc);
1274 }
1275
1276 sc->rx.cur = index;
1277
1278 return (npkt);
1279 }
1280
1281 static void
1282 awg_txeof(struct awg_softc *sc)
1283 {
1284 struct emac_desc *desc;
1285 uint32_t status, size;
1286 if_t ifp;
1287 int i, prog;
1288
1289 AWG_ASSERT_LOCKED(sc);
1290
1291 bus_dmamap_sync(sc->tx.desc_tag, sc->tx.desc_map,
1292 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1293
1294 ifp = sc->ifp;
1295
1296 prog = 0;
1297 for (i = sc->tx.next; sc->tx.queued > 0; i = TX_NEXT(i)) {
1298 desc = &sc->tx.desc_ring[i];
1299 status = le32toh(desc->status);
1300 if ((status & TX_DESC_CTL) != 0)
1301 break;
1302 size = le32toh(desc->size);
1303 if (size & TX_LAST_DESC) {
1304 if ((status & (TX_HEADER_ERR | TX_PAYLOAD_ERR)) != 0)
1305 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1306 else
1307 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1308 }
1309 prog++;
1310 awg_clean_txbuf(sc, i);
1311 }
1312
1313 if (prog > 0) {
1314 sc->tx.next = i;
1315 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1316 }
1317 }
1318
1319 static void
1320 awg_intr(void *arg)
1321 {
1322 struct awg_softc *sc;
1323 uint32_t val;
1324
1325 sc = arg;
1326
1327 AWG_LOCK(sc);
1328 val = RD4(sc, EMAC_INT_STA);
1329 WR4(sc, EMAC_INT_STA, val);
1330
1331 if (val & RX_INT)
1332 awg_rxintr(sc);
1333
1334 if (val & TX_INT)
1335 awg_txeof(sc);
1336
1337 if (val & (TX_INT | TX_BUF_UA_INT)) {
1338 if (!if_sendq_empty(sc->ifp))
1339 awg_start_locked(sc);
1340 }
1341
1342 AWG_UNLOCK(sc);
1343 }
1344
1345 #ifdef DEVICE_POLLING
1346 static int
1347 awg_poll(if_t ifp, enum poll_cmd cmd, int count)
1348 {
1349 struct awg_softc *sc;
1350 uint32_t val;
1351 int rx_npkts;
1352
1353 sc = if_getsoftc(ifp);
1354 rx_npkts = 0;
1355
1356 AWG_LOCK(sc);
1357
1358 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
1359 AWG_UNLOCK(sc);
1360 return (0);
1361 }
1362
1363 rx_npkts = awg_rxintr(sc);
1364 awg_txeof(sc);
1365 if (!if_sendq_empty(ifp))
1366 awg_start_locked(sc);
1367
1368 if (cmd == POLL_AND_CHECK_STATUS) {
1369 val = RD4(sc, EMAC_INT_STA);
1370 if (val != 0)
1371 WR4(sc, EMAC_INT_STA, val);
1372 }
1373
1374 AWG_UNLOCK(sc);
1375
1376 return (rx_npkts);
1377 }
1378 #endif
1379
1380 /*
1381 * syscon functions
1382 */
1383 static uint32_t
1384 syscon_read_emac_clk_reg(device_t dev)
1385 {
1386 struct awg_softc *sc;
1387
1388 sc = device_get_softc(dev);
1389 if (sc->syscon != NULL)
1390 return (SYSCON_READ_4(sc->syscon, EMAC_CLK_REG));
1391 else if (sc->res[_RES_SYSCON] != NULL)
1392 return (bus_read_4(sc->res[_RES_SYSCON], 0));
1393
1394 return (0);
1395 }
1396
1397 static void
1398 syscon_write_emac_clk_reg(device_t dev, uint32_t val)
1399 {
1400 struct awg_softc *sc;
1401
1402 sc = device_get_softc(dev);
1403 if (sc->syscon != NULL)
1404 SYSCON_WRITE_4(sc->syscon, EMAC_CLK_REG, val);
1405 else if (sc->res[_RES_SYSCON] != NULL)
1406 bus_write_4(sc->res[_RES_SYSCON], 0, val);
1407 }
1408
1409 /*
1410 * PHY functions
1411 */
1412
1413 static phandle_t
1414 awg_get_phy_node(device_t dev)
1415 {
1416 phandle_t node;
1417 pcell_t phy_handle;
1418
1419 node = ofw_bus_get_node(dev);
1420 if (OF_getencprop(node, "phy-handle", (void *)&phy_handle,
1421 sizeof(phy_handle)) <= 0)
1422 return (0);
1423
1424 return (OF_node_from_xref(phy_handle));
1425 }
1426
1427 static bool
1428 awg_has_internal_phy(device_t dev)
1429 {
1430 phandle_t node, phy_node;
1431
1432 node = ofw_bus_get_node(dev);
1433 /* Legacy binding */
1434 if (OF_hasprop(node, "allwinner,use-internal-phy"))
1435 return (true);
1436
1437 phy_node = awg_get_phy_node(dev);
1438 return (phy_node != 0 && ofw_bus_node_is_compatible(OF_parent(phy_node),
1439 "allwinner,sun8i-h3-mdio-internal") != 0);
1440 }
1441
1442 static int
1443 awg_parse_delay(device_t dev, uint32_t *tx_delay, uint32_t *rx_delay)
1444 {
1445 phandle_t node;
1446 uint32_t delay;
1447
1448 if (tx_delay == NULL || rx_delay == NULL)
1449 return (EINVAL);
1450 *tx_delay = *rx_delay = 0;
1451 node = ofw_bus_get_node(dev);
1452
1453 if (OF_getencprop(node, "tx-delay", &delay, sizeof(delay)) >= 0)
1454 *tx_delay = delay;
1455 else if (OF_getencprop(node, "allwinner,tx-delay-ps", &delay,
1456 sizeof(delay)) >= 0) {
1457 if ((delay % 100) != 0) {
1458 device_printf(dev, "tx-delay-ps is not a multiple of 100\n");
1459 return (EDOM);
1460 }
1461 *tx_delay = delay / 100;
1462 }
1463 if (*tx_delay > 7) {
1464 device_printf(dev, "tx-delay out of range\n");
1465 return (ERANGE);
1466 }
1467
1468 if (OF_getencprop(node, "rx-delay", &delay, sizeof(delay)) >= 0)
1469 *rx_delay = delay;
1470 else if (OF_getencprop(node, "allwinner,rx-delay-ps", &delay,
1471 sizeof(delay)) >= 0) {
1472 if ((delay % 100) != 0) {
1473 device_printf(dev, "rx-delay-ps is not within documented domain\n");
1474 return (EDOM);
1475 }
1476 *rx_delay = delay / 100;
1477 }
1478 if (*rx_delay > 31) {
1479 device_printf(dev, "rx-delay out of range\n");
1480 return (ERANGE);
1481 }
1482
1483 return (0);
1484 }
1485
1486 static int
1487 awg_setup_phy(device_t dev)
1488 {
1489 struct awg_softc *sc;
1490 clk_t clk_tx, clk_tx_parent;
1491 const char *tx_parent_name;
1492 char *phy_type;
1493 phandle_t node;
1494 uint32_t reg, tx_delay, rx_delay;
1495 int error;
1496 bool use_syscon;
1497
1498 sc = device_get_softc(dev);
1499 node = ofw_bus_get_node(dev);
1500 use_syscon = false;
1501
1502 if (OF_getprop_alloc(node, "phy-mode", (void **)&phy_type) == 0)
1503 return (0);
1504
1505 if (sc->syscon != NULL || sc->res[_RES_SYSCON] != NULL)
1506 use_syscon = true;
1507
1508 if (bootverbose)
1509 device_printf(dev, "PHY type: %s, conf mode: %s\n", phy_type,
1510 use_syscon ? "reg" : "clk");
1511
1512 if (use_syscon) {
1513 /*
1514 * Abstract away writing to syscon for devices like the pine64.
1515 * For the pine64, we get dtb from U-Boot and it still uses the
1516 * legacy setup of specifying syscon register in emac node
1517 * rather than as its own node and using an xref in emac.
1518 * These abstractions can go away once U-Boot dts is up-to-date.
1519 */
1520 reg = syscon_read_emac_clk_reg(dev);
1521 reg &= ~(EMAC_CLK_PIT | EMAC_CLK_SRC | EMAC_CLK_RMII_EN);
1522 if (strncmp(phy_type, "rgmii", 5) == 0)
1523 reg |= EMAC_CLK_PIT_RGMII | EMAC_CLK_SRC_RGMII;
1524 else if (strcmp(phy_type, "rmii") == 0)
1525 reg |= EMAC_CLK_RMII_EN;
1526 else
1527 reg |= EMAC_CLK_PIT_MII | EMAC_CLK_SRC_MII;
1528
1529 /*
1530 * Fail attach if we fail to parse either of the delay
1531 * parameters. If we don't have the proper delay to write to
1532 * syscon, then awg likely won't function properly anyways.
1533 * Lack of delay is not an error!
1534 */
1535 error = awg_parse_delay(dev, &tx_delay, &rx_delay);
1536 if (error != 0)
1537 goto fail;
1538
1539 /* Default to 0 and we'll increase it if we need to. */
1540 reg &= ~(EMAC_CLK_ETXDC | EMAC_CLK_ERXDC);
1541 if (tx_delay > 0)
1542 reg |= (tx_delay << EMAC_CLK_ETXDC_SHIFT);
1543 if (rx_delay > 0)
1544 reg |= (rx_delay << EMAC_CLK_ERXDC_SHIFT);
1545
1546 if (sc->type == EMAC_H3) {
1547 if (awg_has_internal_phy(dev)) {
1548 reg |= EMAC_CLK_EPHY_SELECT;
1549 reg &= ~EMAC_CLK_EPHY_SHUTDOWN;
1550 if (OF_hasprop(node,
1551 "allwinner,leds-active-low"))
1552 reg |= EMAC_CLK_EPHY_LED_POL;
1553 else
1554 reg &= ~EMAC_CLK_EPHY_LED_POL;
1555
1556 /* Set internal PHY addr to 1 */
1557 reg &= ~EMAC_CLK_EPHY_ADDR;
1558 reg |= (1 << EMAC_CLK_EPHY_ADDR_SHIFT);
1559 } else {
1560 reg &= ~EMAC_CLK_EPHY_SELECT;
1561 }
1562 }
1563
1564 if (bootverbose)
1565 device_printf(dev, "EMAC clock: 0x%08x\n", reg);
1566 syscon_write_emac_clk_reg(dev, reg);
1567 } else {
1568 if (strncmp(phy_type, "rgmii", 5) == 0)
1569 tx_parent_name = "emac_int_tx";
1570 else
1571 tx_parent_name = "mii_phy_tx";
1572
1573 /* Get the TX clock */
1574 error = clk_get_by_ofw_name(dev, 0, "tx", &clk_tx);
1575 if (error != 0) {
1576 device_printf(dev, "cannot get tx clock\n");
1577 goto fail;
1578 }
1579
1580 /* Find the desired parent clock based on phy-mode property */
1581 error = clk_get_by_name(dev, tx_parent_name, &clk_tx_parent);
1582 if (error != 0) {
1583 device_printf(dev, "cannot get clock '%s'\n",
1584 tx_parent_name);
1585 goto fail;
1586 }
1587
1588 /* Set TX clock parent */
1589 error = clk_set_parent_by_clk(clk_tx, clk_tx_parent);
1590 if (error != 0) {
1591 device_printf(dev, "cannot set tx clock parent\n");
1592 goto fail;
1593 }
1594
1595 /* Enable TX clock */
1596 error = clk_enable(clk_tx);
1597 if (error != 0) {
1598 device_printf(dev, "cannot enable tx clock\n");
1599 goto fail;
1600 }
1601 }
1602
1603 error = 0;
1604
1605 fail:
1606 OF_prop_free(phy_type);
1607 return (error);
1608 }
1609
1610 static int
1611 awg_setup_extres(device_t dev)
1612 {
1613 struct awg_softc *sc;
1614 phandle_t node, phy_node;
1615 hwreset_t rst_ahb, rst_ephy;
1616 clk_t clk_ahb, clk_ephy;
1617 regulator_t reg;
1618 uint64_t freq;
1619 int error, div;
1620
1621 sc = device_get_softc(dev);
1622 rst_ahb = rst_ephy = NULL;
1623 clk_ahb = clk_ephy = NULL;
1624 reg = NULL;
1625 node = ofw_bus_get_node(dev);
1626 phy_node = awg_get_phy_node(dev);
1627
1628 if (phy_node == 0 && OF_hasprop(node, "phy-handle")) {
1629 error = ENXIO;
1630 device_printf(dev, "cannot get phy handle\n");
1631 goto fail;
1632 }
1633
1634 /* Get AHB clock and reset resources */
1635 error = hwreset_get_by_ofw_name(dev, 0, "stmmaceth", &rst_ahb);
1636 if (error != 0)
1637 error = hwreset_get_by_ofw_name(dev, 0, "ahb", &rst_ahb);
1638 if (error != 0) {
1639 device_printf(dev, "cannot get ahb reset\n");
1640 goto fail;
1641 }
1642 if (hwreset_get_by_ofw_name(dev, 0, "ephy", &rst_ephy) != 0)
1643 if (phy_node == 0 || hwreset_get_by_ofw_idx(dev, phy_node, 0,
1644 &rst_ephy) != 0)
1645 rst_ephy = NULL;
1646 error = clk_get_by_ofw_name(dev, 0, "stmmaceth", &clk_ahb);
1647 if (error != 0)
1648 error = clk_get_by_ofw_name(dev, 0, "ahb", &clk_ahb);
1649 if (error != 0) {
1650 device_printf(dev, "cannot get ahb clock\n");
1651 goto fail;
1652 }
1653 if (clk_get_by_ofw_name(dev, 0, "ephy", &clk_ephy) != 0)
1654 if (phy_node == 0 || clk_get_by_ofw_index(dev, phy_node, 0,
1655 &clk_ephy) != 0)
1656 clk_ephy = NULL;
1657
1658 if (OF_hasprop(node, "syscon") && syscon_get_by_ofw_property(dev, node,
1659 "syscon", &sc->syscon) != 0) {
1660 device_printf(dev, "cannot get syscon driver handle\n");
1661 goto fail;
1662 }
1663
1664 /* Configure PHY for MII or RGMII mode */
1665 if (awg_setup_phy(dev) != 0)
1666 goto fail;
1667
1668 /* Enable clocks */
1669 error = clk_enable(clk_ahb);
1670 if (error != 0) {
1671 device_printf(dev, "cannot enable ahb clock\n");
1672 goto fail;
1673 }
1674 if (clk_ephy != NULL) {
1675 error = clk_enable(clk_ephy);
1676 if (error != 0) {
1677 device_printf(dev, "cannot enable ephy clock\n");
1678 goto fail;
1679 }
1680 }
1681
1682 /* De-assert reset */
1683 error = hwreset_deassert(rst_ahb);
1684 if (error != 0) {
1685 device_printf(dev, "cannot de-assert ahb reset\n");
1686 goto fail;
1687 }
1688 if (rst_ephy != NULL) {
1689 /*
1690 * The ephy reset is left de-asserted by U-Boot. Assert it
1691 * here to make sure that we're in a known good state going
1692 * into the PHY reset.
1693 */
1694 hwreset_assert(rst_ephy);
1695 error = hwreset_deassert(rst_ephy);
1696 if (error != 0) {
1697 device_printf(dev, "cannot de-assert ephy reset\n");
1698 goto fail;
1699 }
1700 }
1701
1702 /* Enable PHY regulator if applicable */
1703 if (regulator_get_by_ofw_property(dev, 0, "phy-supply", ®) == 0) {
1704 error = regulator_enable(reg);
1705 if (error != 0) {
1706 device_printf(dev, "cannot enable PHY regulator\n");
1707 goto fail;
1708 }
1709 }
1710
1711 /* Determine MDC clock divide ratio based on AHB clock */
1712 error = clk_get_freq(clk_ahb, &freq);
1713 if (error != 0) {
1714 device_printf(dev, "cannot get AHB clock frequency\n");
1715 goto fail;
1716 }
1717 div = freq / MDIO_FREQ;
1718 if (div <= 16)
1719 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_16;
1720 else if (div <= 32)
1721 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_32;
1722 else if (div <= 64)
1723 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_64;
1724 else if (div <= 128)
1725 sc->mdc_div_ratio_m = MDC_DIV_RATIO_M_128;
1726 else {
1727 device_printf(dev, "cannot determine MDC clock divide ratio\n");
1728 error = ENXIO;
1729 goto fail;
1730 }
1731
1732 if (bootverbose)
1733 device_printf(dev, "AHB frequency %ju Hz, MDC div: 0x%x\n",
1734 (uintmax_t)freq, sc->mdc_div_ratio_m);
1735
1736 return (0);
1737
1738 fail:
1739 if (reg != NULL)
1740 regulator_release(reg);
1741 if (clk_ephy != NULL)
1742 clk_release(clk_ephy);
1743 if (clk_ahb != NULL)
1744 clk_release(clk_ahb);
1745 if (rst_ephy != NULL)
1746 hwreset_release(rst_ephy);
1747 if (rst_ahb != NULL)
1748 hwreset_release(rst_ahb);
1749 return (error);
1750 }
1751
1752 #ifdef AWG_DEBUG
1753 static void
1754 awg_dump_regs(device_t dev)
1755 {
1756 static const struct {
1757 const char *name;
1758 u_int reg;
1759 } regs[] = {
1760 { "BASIC_CTL_0", EMAC_BASIC_CTL_0 },
1761 { "BASIC_CTL_1", EMAC_BASIC_CTL_1 },
1762 { "INT_STA", EMAC_INT_STA },
1763 { "INT_EN", EMAC_INT_EN },
1764 { "TX_CTL_0", EMAC_TX_CTL_0 },
1765 { "TX_CTL_1", EMAC_TX_CTL_1 },
1766 { "TX_FLOW_CTL", EMAC_TX_FLOW_CTL },
1767 { "TX_DMA_LIST", EMAC_TX_DMA_LIST },
1768 { "RX_CTL_0", EMAC_RX_CTL_0 },
1769 { "RX_CTL_1", EMAC_RX_CTL_1 },
1770 { "RX_DMA_LIST", EMAC_RX_DMA_LIST },
1771 { "RX_FRM_FLT", EMAC_RX_FRM_FLT },
1772 { "RX_HASH_0", EMAC_RX_HASH_0 },
1773 { "RX_HASH_1", EMAC_RX_HASH_1 },
1774 { "MII_CMD", EMAC_MII_CMD },
1775 { "ADDR_HIGH0", EMAC_ADDR_HIGH(0) },
1776 { "ADDR_LOW0", EMAC_ADDR_LOW(0) },
1777 { "TX_DMA_STA", EMAC_TX_DMA_STA },
1778 { "TX_DMA_CUR_DESC", EMAC_TX_DMA_CUR_DESC },
1779 { "TX_DMA_CUR_BUF", EMAC_TX_DMA_CUR_BUF },
1780 { "RX_DMA_STA", EMAC_RX_DMA_STA },
1781 { "RX_DMA_CUR_DESC", EMAC_RX_DMA_CUR_DESC },
1782 { "RX_DMA_CUR_BUF", EMAC_RX_DMA_CUR_BUF },
1783 { "RGMII_STA", EMAC_RGMII_STA },
1784 };
1785 struct awg_softc *sc;
1786 unsigned int n;
1787
1788 sc = device_get_softc(dev);
1789
1790 for (n = 0; n < nitems(regs); n++)
1791 device_printf(dev, " %-20s %08x\n", regs[n].name,
1792 RD4(sc, regs[n].reg));
1793 }
1794 #endif
1795
1796 #define GPIO_ACTIVE_LOW 1
1797
1798 static int
1799 awg_phy_reset(device_t dev)
1800 {
1801 pcell_t gpio_prop[4], delay_prop[3];
1802 phandle_t node, gpio_node;
1803 device_t gpio;
1804 uint32_t pin, flags;
1805 uint32_t pin_value;
1806
1807 node = ofw_bus_get_node(dev);
1808 if (OF_getencprop(node, "allwinner,reset-gpio", gpio_prop,
1809 sizeof(gpio_prop)) <= 0)
1810 return (0);
1811
1812 if (OF_getencprop(node, "allwinner,reset-delays-us", delay_prop,
1813 sizeof(delay_prop)) <= 0)
1814 return (ENXIO);
1815
1816 gpio_node = OF_node_from_xref(gpio_prop[0]);
1817 if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL)
1818 return (ENXIO);
1819
1820 if (GPIO_MAP_GPIOS(gpio, node, gpio_node, nitems(gpio_prop) - 1,
1821 gpio_prop + 1, &pin, &flags) != 0)
1822 return (ENXIO);
1823
1824 pin_value = GPIO_PIN_LOW;
1825 if (OF_hasprop(node, "allwinner,reset-active-low"))
1826 pin_value = GPIO_PIN_HIGH;
1827
1828 if (flags & GPIO_ACTIVE_LOW)
1829 pin_value = !pin_value;
1830
1831 GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT);
1832 GPIO_PIN_SET(gpio, pin, pin_value);
1833 DELAY(delay_prop[0]);
1834 GPIO_PIN_SET(gpio, pin, !pin_value);
1835 DELAY(delay_prop[1]);
1836 GPIO_PIN_SET(gpio, pin, pin_value);
1837 DELAY(delay_prop[2]);
1838
1839 return (0);
1840 }
1841
1842 static int
1843 awg_reset(device_t dev)
1844 {
1845 struct awg_softc *sc;
1846 int retry;
1847
1848 sc = device_get_softc(dev);
1849
1850 /* Reset PHY if necessary */
1851 if (awg_phy_reset(dev) != 0) {
1852 device_printf(dev, "failed to reset PHY\n");
1853 return (ENXIO);
1854 }
1855
1856 /* Soft reset all registers and logic */
1857 WR4(sc, EMAC_BASIC_CTL_1, BASIC_CTL_SOFT_RST);
1858
1859 /* Wait for soft reset bit to self-clear */
1860 for (retry = SOFT_RST_RETRY; retry > 0; retry--) {
1861 if ((RD4(sc, EMAC_BASIC_CTL_1) & BASIC_CTL_SOFT_RST) == 0)
1862 break;
1863 DELAY(10);
1864 }
1865 if (retry == 0) {
1866 device_printf(dev, "soft reset timed out\n");
1867 #ifdef AWG_DEBUG
1868 awg_dump_regs(dev);
1869 #endif
1870 return (ETIMEDOUT);
1871 }
1872
1873 return (0);
1874 }
1875
1876 /*
1877 * Stats
1878 */
1879
1880 static void
1881 awg_tick(void *softc)
1882 {
1883 struct awg_softc *sc;
1884 struct mii_data *mii;
1885 if_t ifp;
1886 int link;
1887
1888 sc = softc;
1889 ifp = sc->ifp;
1890 mii = device_get_softc(sc->miibus);
1891
1892 AWG_ASSERT_LOCKED(sc);
1893
1894 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
1895 return;
1896
1897 link = sc->link;
1898 mii_tick(mii);
1899 if (sc->link && !link)
1900 awg_start_locked(sc);
1901
1902 callout_reset(&sc->stat_ch, hz, awg_tick, sc);
1903 }
1904
1905 /*
1906 * Probe/attach functions
1907 */
1908
1909 static int
1910 awg_probe(device_t dev)
1911 {
1912 if (!ofw_bus_status_okay(dev))
1913 return (ENXIO);
1914
1915 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
1916 return (ENXIO);
1917
1918 device_set_desc(dev, "Allwinner Gigabit Ethernet");
1919 return (BUS_PROBE_DEFAULT);
1920 }
1921
1922 static int
1923 awg_attach(device_t dev)
1924 {
1925 uint8_t eaddr[ETHER_ADDR_LEN];
1926 struct awg_softc *sc;
1927 int error;
1928
1929 sc = device_get_softc(dev);
1930 sc->dev = dev;
1931 sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1932
1933 if (bus_alloc_resources(dev, awg_spec, sc->res) != 0) {
1934 device_printf(dev, "cannot allocate resources for device\n");
1935 return (ENXIO);
1936 }
1937
1938 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF);
1939 callout_init_mtx(&sc->stat_ch, &sc->mtx, 0);
1940
1941 /* Setup clocks and regulators */
1942 error = awg_setup_extres(dev);
1943 if (error != 0)
1944 return (error);
1945
1946 /* Read MAC address before resetting the chip */
1947 awg_get_eaddr(dev, eaddr);
1948
1949 /* Soft reset EMAC core */
1950 error = awg_reset(dev);
1951 if (error != 0)
1952 return (error);
1953
1954 /* Setup DMA descriptors */
1955 error = awg_setup_dma(dev);
1956 if (error != 0)
1957 return (error);
1958
1959 /* Install interrupt handler */
1960 error = bus_setup_intr(dev, sc->res[_RES_IRQ],
1961 INTR_TYPE_NET | INTR_MPSAFE, NULL, awg_intr, sc, &sc->ih);
1962 if (error != 0) {
1963 device_printf(dev, "cannot setup interrupt handler\n");
1964 return (error);
1965 }
1966
1967 /* Setup ethernet interface */
1968 sc->ifp = if_alloc(IFT_ETHER);
1969 if_setsoftc(sc->ifp, sc);
1970 if_initname(sc->ifp, device_get_name(dev), device_get_unit(dev));
1971 if_setflags(sc->ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1972 if_setstartfn(sc->ifp, awg_start);
1973 if_setioctlfn(sc->ifp, awg_ioctl);
1974 if_setinitfn(sc->ifp, awg_init);
1975 if_setsendqlen(sc->ifp, TX_DESC_COUNT - 1);
1976 if_setsendqready(sc->ifp);
1977 if_sethwassist(sc->ifp, CSUM_IP | CSUM_UDP | CSUM_TCP);
1978 if_setcapabilities(sc->ifp, IFCAP_VLAN_MTU | IFCAP_HWCSUM);
1979 if_setcapenable(sc->ifp, if_getcapabilities(sc->ifp));
1980 #ifdef DEVICE_POLLING
1981 if_setcapabilitiesbit(sc->ifp, IFCAP_POLLING, 0);
1982 #endif
1983
1984 /* Attach MII driver */
1985 error = mii_attach(dev, &sc->miibus, sc->ifp, awg_media_change,
1986 awg_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
1987 MIIF_DOPAUSE);
1988 if (error != 0) {
1989 device_printf(dev, "cannot attach PHY\n");
1990 return (error);
1991 }
1992
1993 /* Attach ethernet interface */
1994 ether_ifattach(sc->ifp, eaddr);
1995
1996 return (0);
1997 }
1998
1999 static device_method_t awg_methods[] = {
2000 /* Device interface */
2001 DEVMETHOD(device_probe, awg_probe),
2002 DEVMETHOD(device_attach, awg_attach),
2003
2004 /* MII interface */
2005 DEVMETHOD(miibus_readreg, awg_miibus_readreg),
2006 DEVMETHOD(miibus_writereg, awg_miibus_writereg),
2007 DEVMETHOD(miibus_statchg, awg_miibus_statchg),
2008
2009 DEVMETHOD_END
2010 };
2011
2012 static driver_t awg_driver = {
2013 "awg",
2014 awg_methods,
2015 sizeof(struct awg_softc),
2016 };
2017
2018 static devclass_t awg_devclass;
2019
2020 DRIVER_MODULE(awg, simplebus, awg_driver, awg_devclass, 0, 0);
2021 DRIVER_MODULE(miibus, awg, miibus_driver, miibus_devclass, 0, 0);
2022 MODULE_DEPEND(awg, ether, 1, 1, 1);
2023 MODULE_DEPEND(awg, miibus, 1, 1, 1);
2024 MODULE_DEPEND(awg, aw_sid, 1, 1, 1);
2025 SIMPLEBUS_PNP_INFO(compat_data);
Cache object: 98474afe9250a3a389c7e41b41a59dae
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