Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/allwinner/if_emac.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* A10/A20 EMAC driver */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/bus.h> 41 #include <sys/lock.h> 42 #include <sys/mbuf.h> 43 #include <sys/mutex.h> 44 #include <sys/rman.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/gpio.h> 49 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #include <machine/intr.h> 53 54 #include <net/if.h> 55 #include <net/if_var.h> 56 #include <net/if_arp.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 #include <net/if_mib.h> 61 #include <net/ethernet.h> 62 #include <net/if_vlan_var.h> 63 64 #ifdef INET 65 #include <netinet/in.h> 66 #include <netinet/in_systm.h> 67 #include <netinet/in_var.h> 68 #include <netinet/ip.h> 69 #endif 70 71 #include <net/bpf.h> 72 #include <net/bpfdesc.h> 73 74 #include <dev/ofw/ofw_bus.h> 75 #include <dev/ofw/ofw_bus_subr.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 80 #include <arm/allwinner/if_emacreg.h> 81 #include <arm/allwinner/aw_sid.h> 82 83 #include <dev/extres/clk/clk.h> 84 85 #include "miibus_if.h" 86 87 #include "gpio_if.h" 88 89 #include "a10_sramc.h" 90 91 struct emac_softc { 92 struct ifnet *emac_ifp; 93 device_t emac_dev; 94 device_t emac_miibus; 95 bus_space_handle_t emac_handle; 96 bus_space_tag_t emac_tag; 97 struct resource *emac_res; 98 struct resource *emac_irq; 99 void *emac_intrhand; 100 clk_t emac_clk; 101 int emac_if_flags; 102 struct mtx emac_mtx; 103 struct callout emac_tick_ch; 104 int emac_watchdog_timer; 105 int emac_rx_process_limit; 106 int emac_link; 107 uint32_t emac_fifo_mask; 108 }; 109 110 static int emac_probe(device_t); 111 static int emac_attach(device_t); 112 static int emac_detach(device_t); 113 static int emac_shutdown(device_t); 114 static int emac_suspend(device_t); 115 static int emac_resume(device_t); 116 117 static int emac_sys_setup(struct emac_softc *); 118 static void emac_reset(struct emac_softc *); 119 120 static void emac_init_locked(struct emac_softc *); 121 static void emac_start_locked(struct ifnet *); 122 static void emac_init(void *); 123 static void emac_stop_locked(struct emac_softc *); 124 static void emac_intr(void *); 125 static int emac_ioctl(struct ifnet *, u_long, caddr_t); 126 127 static void emac_rxeof(struct emac_softc *, int); 128 static void emac_txeof(struct emac_softc *, uint32_t); 129 130 static int emac_miibus_readreg(device_t, int, int); 131 static int emac_miibus_writereg(device_t, int, int, int); 132 static void emac_miibus_statchg(device_t); 133 134 static int emac_ifmedia_upd(struct ifnet *); 135 static void emac_ifmedia_sts(struct ifnet *, struct ifmediareq *); 136 137 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 138 static int sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS); 139 140 #define EMAC_READ_REG(sc, reg) \ 141 bus_space_read_4(sc->emac_tag, sc->emac_handle, reg) 142 #define EMAC_WRITE_REG(sc, reg, val) \ 143 bus_space_write_4(sc->emac_tag, sc->emac_handle, reg, val) 144 145 static int 146 emac_sys_setup(struct emac_softc *sc) 147 { 148 int error; 149 150 /* Activate EMAC clock. */ 151 error = clk_get_by_ofw_index(sc->emac_dev, 0, 0, &sc->emac_clk); 152 if (error != 0) { 153 device_printf(sc->emac_dev, "cannot get clock\n"); 154 return (error); 155 } 156 error = clk_enable(sc->emac_clk); 157 if (error != 0) { 158 device_printf(sc->emac_dev, "cannot enable clock\n"); 159 return (error); 160 } 161 162 /* Map sram. */ 163 a10_map_to_emac(); 164 165 return (0); 166 } 167 168 static void 169 emac_get_hwaddr(struct emac_softc *sc, uint8_t *hwaddr) 170 { 171 uint32_t val0, val1, rnd; 172 u_char rootkey[16]; 173 size_t rootkey_size; 174 175 /* 176 * Try to get MAC address from running hardware. 177 * If there is something non-zero there just use it. 178 * 179 * Otherwise set the address to a convenient locally assigned address, 180 * using the SID rootkey. 181 * This is was uboot does so we end up with the same mac as if uboot 182 * did set it. 183 * If we can't get the root key, generate a random one, 184 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 185 * assigned bit set, and the broadcast/multicast bit clear. 186 */ 187 val0 = EMAC_READ_REG(sc, EMAC_MAC_A0); 188 val1 = EMAC_READ_REG(sc, EMAC_MAC_A1); 189 if ((val0 | val1) != 0 && (val0 | val1) != 0xffffff) { 190 hwaddr[0] = (val1 >> 16) & 0xff; 191 hwaddr[1] = (val1 >> 8) & 0xff; 192 hwaddr[2] = (val1 >> 0) & 0xff; 193 hwaddr[3] = (val0 >> 16) & 0xff; 194 hwaddr[4] = (val0 >> 8) & 0xff; 195 hwaddr[5] = (val0 >> 0) & 0xff; 196 } else { 197 rootkey_size = sizeof(rootkey); 198 if (aw_sid_get_fuse(AW_SID_FUSE_ROOTKEY, rootkey, 199 &rootkey_size) == 0) { 200 hwaddr[0] = 0x2; 201 hwaddr[1] = rootkey[3]; 202 hwaddr[2] = rootkey[12]; 203 hwaddr[3] = rootkey[13]; 204 hwaddr[4] = rootkey[14]; 205 hwaddr[5] = rootkey[15]; 206 } 207 else { 208 rnd = arc4random() & 0x00ffffff; 209 hwaddr[0] = 'b'; 210 hwaddr[1] = 's'; 211 hwaddr[2] = 'd'; 212 hwaddr[3] = (rnd >> 16) & 0xff; 213 hwaddr[4] = (rnd >> 8) & 0xff; 214 hwaddr[5] = (rnd >> 0) & 0xff; 215 } 216 } 217 if (bootverbose) 218 printf("MAC address: %s\n", ether_sprintf(hwaddr)); 219 } 220 221 static u_int 222 emac_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 223 { 224 uint32_t h, *hashes = arg; 225 226 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 227 hashes[h >> 5] |= 1 << (h & 0x1f); 228 229 return (1); 230 } 231 232 static void 233 emac_set_rx_mode(struct emac_softc *sc) 234 { 235 struct ifnet *ifp; 236 uint32_t hashes[2]; 237 uint32_t rcr = 0; 238 239 EMAC_ASSERT_LOCKED(sc); 240 241 ifp = sc->emac_ifp; 242 243 rcr = EMAC_READ_REG(sc, EMAC_RX_CTL); 244 245 /* Unicast packet and DA filtering */ 246 rcr |= EMAC_RX_UCAD; 247 rcr |= EMAC_RX_DAF; 248 249 hashes[0] = 0; 250 hashes[1] = 0; 251 if (ifp->if_flags & IFF_ALLMULTI) { 252 hashes[0] = 0xffffffff; 253 hashes[1] = 0xffffffff; 254 } else 255 if_foreach_llmaddr(ifp, emac_hash_maddr, hashes); 256 rcr |= EMAC_RX_MCO; 257 rcr |= EMAC_RX_MHF; 258 EMAC_WRITE_REG(sc, EMAC_RX_HASH0, hashes[0]); 259 EMAC_WRITE_REG(sc, EMAC_RX_HASH1, hashes[1]); 260 261 if (ifp->if_flags & IFF_BROADCAST) { 262 rcr |= EMAC_RX_BCO; 263 rcr |= EMAC_RX_MCO; 264 } 265 266 if (ifp->if_flags & IFF_PROMISC) 267 rcr |= EMAC_RX_PA; 268 else 269 rcr |= EMAC_RX_UCAD; 270 271 EMAC_WRITE_REG(sc, EMAC_RX_CTL, rcr); 272 } 273 274 static void 275 emac_reset(struct emac_softc *sc) 276 { 277 278 EMAC_WRITE_REG(sc, EMAC_CTL, 0); 279 DELAY(200); 280 EMAC_WRITE_REG(sc, EMAC_CTL, 1); 281 DELAY(200); 282 } 283 284 static void 285 emac_drain_rxfifo(struct emac_softc *sc) 286 { 287 uint32_t data; 288 289 while (EMAC_READ_REG(sc, EMAC_RX_FBC) > 0) 290 data = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 291 } 292 293 static void 294 emac_txeof(struct emac_softc *sc, uint32_t status) 295 { 296 struct ifnet *ifp; 297 298 EMAC_ASSERT_LOCKED(sc); 299 300 ifp = sc->emac_ifp; 301 status &= (EMAC_TX_FIFO0 | EMAC_TX_FIFO1); 302 sc->emac_fifo_mask &= ~status; 303 if (status == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 304 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 2); 305 else 306 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 307 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 308 309 /* Unarm watchdog timer if no TX */ 310 sc->emac_watchdog_timer = 0; 311 } 312 313 static void 314 emac_rxeof(struct emac_softc *sc, int count) 315 { 316 struct ifnet *ifp; 317 struct mbuf *m, *m0; 318 uint32_t reg_val, rxcount; 319 int16_t len; 320 uint16_t status; 321 int i; 322 323 ifp = sc->emac_ifp; 324 for (; count > 0 && 325 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; count--) { 326 /* 327 * Race warning: The first packet might arrive with 328 * the interrupts disabled, but the second will fix 329 */ 330 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC); 331 if (!rxcount) { 332 /* Had one stuck? */ 333 rxcount = EMAC_READ_REG(sc, EMAC_RX_FBC); 334 if (!rxcount) 335 return; 336 } 337 /* Check packet header */ 338 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 339 if (reg_val != EMAC_PACKET_HEADER) { 340 /* Packet header is wrong */ 341 if (bootverbose) 342 if_printf(ifp, "wrong packet header\n"); 343 /* Disable RX */ 344 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 345 reg_val &= ~EMAC_CTL_RX_EN; 346 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 347 348 /* Flush RX FIFO */ 349 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 350 reg_val |= EMAC_RX_FLUSH_FIFO; 351 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 352 for (i = 100; i > 0; i--) { 353 DELAY(100); 354 if ((EMAC_READ_REG(sc, EMAC_RX_CTL) & 355 EMAC_RX_FLUSH_FIFO) == 0) 356 break; 357 } 358 if (i == 0) { 359 device_printf(sc->emac_dev, 360 "flush FIFO timeout\n"); 361 /* Reinitialize controller */ 362 emac_init_locked(sc); 363 return; 364 } 365 /* Enable RX */ 366 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 367 reg_val |= EMAC_CTL_RX_EN; 368 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 369 370 return; 371 } 372 373 /* Get packet size and status */ 374 reg_val = EMAC_READ_REG(sc, EMAC_RX_IO_DATA); 375 len = reg_val & 0xffff; 376 status = (reg_val >> 16) & 0xffff; 377 378 if (len < 64 || (status & EMAC_PKT_OK) == 0) { 379 if (bootverbose) 380 if_printf(ifp, 381 "bad packet: len = %i status = %i\n", 382 len, status); 383 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 384 emac_drain_rxfifo(sc); 385 continue; 386 } 387 #if 0 388 if (status & (EMAC_CRCERR | EMAC_LENERR)) { 389 good_packet = 0; 390 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 391 if (status & EMAC_CRCERR) 392 if_printf(ifp, "crc error\n"); 393 if (status & EMAC_LENERR) 394 if_printf(ifp, "length error\n"); 395 } 396 #endif 397 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 398 if (m == NULL) { 399 emac_drain_rxfifo(sc); 400 return; 401 } 402 m->m_len = m->m_pkthdr.len = MCLBYTES; 403 404 /* Copy entire frame to mbuf first. */ 405 bus_space_read_multi_4(sc->emac_tag, sc->emac_handle, 406 EMAC_RX_IO_DATA, mtod(m, uint32_t *), roundup2(len, 4) / 4); 407 408 m->m_pkthdr.rcvif = ifp; 409 m->m_len = m->m_pkthdr.len = len - ETHER_CRC_LEN; 410 411 /* 412 * Emac controller needs strict alignment, so to avoid 413 * copying over an entire frame to align, we allocate 414 * a new mbuf and copy ethernet header + IP header to 415 * the new mbuf. The new mbuf is prepended into the 416 * existing mbuf chain. 417 */ 418 if (m->m_len <= (MHLEN - ETHER_HDR_LEN)) { 419 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 420 m->m_data += ETHER_HDR_LEN; 421 } else if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN) && 422 m->m_len > (MHLEN - ETHER_HDR_LEN)) { 423 MGETHDR(m0, M_NOWAIT, MT_DATA); 424 if (m0 != NULL) { 425 len = ETHER_HDR_LEN + m->m_pkthdr.l2hlen; 426 bcopy(m->m_data, m0->m_data, len); 427 m->m_data += len; 428 m->m_len -= len; 429 m0->m_len = len; 430 M_MOVE_PKTHDR(m0, m); 431 m0->m_next = m; 432 m = m0; 433 } else { 434 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 435 m_freem(m); 436 m = NULL; 437 continue; 438 } 439 } else if (m->m_len > EMAC_MAC_MAXF) { 440 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 441 m_freem(m); 442 m = NULL; 443 continue; 444 } 445 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 446 EMAC_UNLOCK(sc); 447 (*ifp->if_input)(ifp, m); 448 EMAC_LOCK(sc); 449 } 450 } 451 452 static void 453 emac_watchdog(struct emac_softc *sc) 454 { 455 struct ifnet *ifp; 456 457 EMAC_ASSERT_LOCKED(sc); 458 459 if (sc->emac_watchdog_timer == 0 || --sc->emac_watchdog_timer) 460 return; 461 462 ifp = sc->emac_ifp; 463 464 if (sc->emac_link == 0) { 465 if (bootverbose) 466 if_printf(sc->emac_ifp, "watchdog timeout " 467 "(missed link)\n"); 468 } else 469 if_printf(sc->emac_ifp, "watchdog timeout -- resetting\n"); 470 471 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 472 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 473 emac_init_locked(sc); 474 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 475 emac_start_locked(ifp); 476 } 477 478 static void 479 emac_tick(void *arg) 480 { 481 struct emac_softc *sc; 482 struct mii_data *mii; 483 484 sc = (struct emac_softc *)arg; 485 mii = device_get_softc(sc->emac_miibus); 486 mii_tick(mii); 487 488 emac_watchdog(sc); 489 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 490 } 491 492 static void 493 emac_init(void *xcs) 494 { 495 struct emac_softc *sc; 496 497 sc = (struct emac_softc *)xcs; 498 EMAC_LOCK(sc); 499 emac_init_locked(sc); 500 EMAC_UNLOCK(sc); 501 } 502 503 static void 504 emac_init_locked(struct emac_softc *sc) 505 { 506 struct ifnet *ifp; 507 struct mii_data *mii; 508 uint32_t reg_val; 509 uint8_t *eaddr; 510 511 EMAC_ASSERT_LOCKED(sc); 512 513 ifp = sc->emac_ifp; 514 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 515 return; 516 517 /* Flush RX FIFO */ 518 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 519 reg_val |= EMAC_RX_FLUSH_FIFO; 520 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 521 DELAY(1); 522 523 /* Soft reset MAC */ 524 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); 525 reg_val &= (~EMAC_MAC_CTL0_SOFT_RST); 526 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); 527 528 /* Set MII clock */ 529 reg_val = EMAC_READ_REG(sc, EMAC_MAC_MCFG); 530 reg_val &= (~(0xf << 2)); 531 reg_val |= (0xd << 2); 532 EMAC_WRITE_REG(sc, EMAC_MAC_MCFG, reg_val); 533 534 /* Clear RX counter */ 535 EMAC_WRITE_REG(sc, EMAC_RX_FBC, 0); 536 537 /* Disable all interrupt and clear interrupt status */ 538 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 539 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 540 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 541 DELAY(1); 542 543 /* Set up TX */ 544 reg_val = EMAC_READ_REG(sc, EMAC_TX_MODE); 545 reg_val |= EMAC_TX_AB_M; 546 reg_val &= EMAC_TX_TM; 547 EMAC_WRITE_REG(sc, EMAC_TX_MODE, reg_val); 548 549 /* Set up RX */ 550 reg_val = EMAC_READ_REG(sc, EMAC_RX_CTL); 551 reg_val |= EMAC_RX_SETUP; 552 reg_val &= EMAC_RX_TM; 553 EMAC_WRITE_REG(sc, EMAC_RX_CTL, reg_val); 554 555 /* Set up MAC CTL0. */ 556 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL0); 557 reg_val |= EMAC_MAC_CTL0_SETUP; 558 EMAC_WRITE_REG(sc, EMAC_MAC_CTL0, reg_val); 559 560 /* Set up MAC CTL1. */ 561 reg_val = EMAC_READ_REG(sc, EMAC_MAC_CTL1); 562 reg_val |= EMAC_MAC_CTL1_SETUP; 563 EMAC_WRITE_REG(sc, EMAC_MAC_CTL1, reg_val); 564 565 /* Set up IPGT */ 566 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, EMAC_MAC_IPGT_FD); 567 568 /* Set up IPGR */ 569 EMAC_WRITE_REG(sc, EMAC_MAC_IPGR, EMAC_MAC_NBTB_IPG2 | 570 (EMAC_MAC_NBTB_IPG1 << 8)); 571 572 /* Set up Collison window */ 573 EMAC_WRITE_REG(sc, EMAC_MAC_CLRT, EMAC_MAC_RM | (EMAC_MAC_CW << 8)); 574 575 /* Set up Max Frame Length */ 576 EMAC_WRITE_REG(sc, EMAC_MAC_MAXF, EMAC_MAC_MFL); 577 578 /* Setup ethernet address */ 579 eaddr = IF_LLADDR(ifp); 580 EMAC_WRITE_REG(sc, EMAC_MAC_A1, eaddr[0] << 16 | 581 eaddr[1] << 8 | eaddr[2]); 582 EMAC_WRITE_REG(sc, EMAC_MAC_A0, eaddr[3] << 16 | 583 eaddr[4] << 8 | eaddr[5]); 584 585 /* Setup rx filter */ 586 emac_set_rx_mode(sc); 587 588 /* Enable RX/TX0/RX Hlevel interrupt */ 589 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL); 590 reg_val |= EMAC_INT_EN; 591 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val); 592 593 ifp->if_drv_flags |= IFF_DRV_RUNNING; 594 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 595 596 sc->emac_link = 0; 597 598 /* Switch to the current media. */ 599 mii = device_get_softc(sc->emac_miibus); 600 mii_mediachg(mii); 601 602 callout_reset(&sc->emac_tick_ch, hz, emac_tick, sc); 603 } 604 605 static void 606 emac_start(struct ifnet *ifp) 607 { 608 struct emac_softc *sc; 609 610 sc = ifp->if_softc; 611 EMAC_LOCK(sc); 612 emac_start_locked(ifp); 613 EMAC_UNLOCK(sc); 614 } 615 616 static void 617 emac_start_locked(struct ifnet *ifp) 618 { 619 struct emac_softc *sc; 620 struct mbuf *m, *m0; 621 uint32_t fifo, reg; 622 623 sc = ifp->if_softc; 624 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 625 return; 626 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 627 return; 628 if (sc->emac_link == 0) 629 return; 630 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 631 if (m == NULL) 632 return; 633 634 /* Select channel */ 635 if (sc->emac_fifo_mask & EMAC_TX_FIFO0) 636 fifo = 1; 637 else 638 fifo = 0; 639 sc->emac_fifo_mask |= (1 << fifo); 640 if (sc->emac_fifo_mask == (EMAC_TX_FIFO0 | EMAC_TX_FIFO1)) 641 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 642 EMAC_WRITE_REG(sc, EMAC_TX_INS, fifo); 643 644 /* 645 * Emac controller wants 4 byte aligned TX buffers. 646 * We have to copy pretty much all the time. 647 */ 648 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0) { 649 m0 = m_defrag(m, M_NOWAIT); 650 if (m0 == NULL) { 651 m_freem(m); 652 m = NULL; 653 return; 654 } 655 m = m0; 656 } 657 /* Write data */ 658 bus_space_write_multi_4(sc->emac_tag, sc->emac_handle, 659 EMAC_TX_IO_DATA, mtod(m, uint32_t *), 660 roundup2(m->m_len, 4) / 4); 661 662 /* Send the data lengh. */ 663 reg = (fifo == 0) ? EMAC_TX_PL0 : EMAC_TX_PL1; 664 EMAC_WRITE_REG(sc, reg, m->m_len); 665 666 /* Start translate from fifo to phy. */ 667 reg = (fifo == 0) ? EMAC_TX_CTL0 : EMAC_TX_CTL1; 668 EMAC_WRITE_REG(sc, reg, EMAC_READ_REG(sc, reg) | 1); 669 670 /* Set timeout */ 671 sc->emac_watchdog_timer = 5; 672 673 /* Data have been sent to hardware, it is okay to free the mbuf now. */ 674 BPF_MTAP(ifp, m); 675 m_freem(m); 676 } 677 678 static void 679 emac_stop_locked(struct emac_softc *sc) 680 { 681 struct ifnet *ifp; 682 uint32_t reg_val; 683 684 EMAC_ASSERT_LOCKED(sc); 685 686 ifp = sc->emac_ifp; 687 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 688 sc->emac_link = 0; 689 690 /* Disable all interrupt and clear interrupt status */ 691 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 692 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 693 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 694 695 /* Disable RX/TX */ 696 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 697 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); 698 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 699 700 callout_stop(&sc->emac_tick_ch); 701 } 702 703 static void 704 emac_intr(void *arg) 705 { 706 struct emac_softc *sc; 707 struct ifnet *ifp; 708 uint32_t reg_val; 709 710 sc = (struct emac_softc *)arg; 711 EMAC_LOCK(sc); 712 713 /* Disable all interrupts */ 714 EMAC_WRITE_REG(sc, EMAC_INT_CTL, 0); 715 /* Get EMAC interrupt status */ 716 reg_val = EMAC_READ_REG(sc, EMAC_INT_STA); 717 /* Clear ISR status */ 718 EMAC_WRITE_REG(sc, EMAC_INT_STA, reg_val); 719 720 /* Received incoming packet */ 721 if (reg_val & EMAC_INT_STA_RX) 722 emac_rxeof(sc, sc->emac_rx_process_limit); 723 724 /* Transmit Interrupt check */ 725 if (reg_val & EMAC_INT_STA_TX) { 726 emac_txeof(sc, reg_val); 727 ifp = sc->emac_ifp; 728 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 729 emac_start_locked(ifp); 730 } 731 732 /* Re-enable interrupt mask */ 733 reg_val = EMAC_READ_REG(sc, EMAC_INT_CTL); 734 reg_val |= EMAC_INT_EN; 735 EMAC_WRITE_REG(sc, EMAC_INT_CTL, reg_val); 736 EMAC_UNLOCK(sc); 737 } 738 739 static int 740 emac_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 741 { 742 struct emac_softc *sc; 743 struct mii_data *mii; 744 struct ifreq *ifr; 745 int error = 0; 746 747 sc = ifp->if_softc; 748 ifr = (struct ifreq *)data; 749 750 switch (command) { 751 case SIOCSIFFLAGS: 752 EMAC_LOCK(sc); 753 if (ifp->if_flags & IFF_UP) { 754 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 755 if ((ifp->if_flags ^ sc->emac_if_flags) & 756 (IFF_PROMISC | IFF_ALLMULTI)) 757 emac_set_rx_mode(sc); 758 } else 759 emac_init_locked(sc); 760 } else { 761 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 762 emac_stop_locked(sc); 763 } 764 sc->emac_if_flags = ifp->if_flags; 765 EMAC_UNLOCK(sc); 766 break; 767 case SIOCADDMULTI: 768 case SIOCDELMULTI: 769 EMAC_LOCK(sc); 770 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 771 emac_set_rx_mode(sc); 772 } 773 EMAC_UNLOCK(sc); 774 break; 775 case SIOCGIFMEDIA: 776 case SIOCSIFMEDIA: 777 mii = device_get_softc(sc->emac_miibus); 778 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 779 break; 780 default: 781 error = ether_ioctl(ifp, command, data); 782 break; 783 } 784 return (error); 785 } 786 787 static int 788 emac_probe(device_t dev) 789 { 790 791 if (!ofw_bus_status_okay(dev)) 792 return (ENXIO); 793 794 if (!ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-emac")) 795 return (ENXIO); 796 797 device_set_desc(dev, "A10/A20 EMAC ethernet controller"); 798 return (BUS_PROBE_DEFAULT); 799 } 800 801 static int 802 emac_detach(device_t dev) 803 { 804 struct emac_softc *sc; 805 806 sc = device_get_softc(dev); 807 sc->emac_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 808 if (device_is_attached(dev)) { 809 ether_ifdetach(sc->emac_ifp); 810 EMAC_LOCK(sc); 811 emac_stop_locked(sc); 812 EMAC_UNLOCK(sc); 813 callout_drain(&sc->emac_tick_ch); 814 } 815 816 if (sc->emac_intrhand != NULL) 817 bus_teardown_intr(sc->emac_dev, sc->emac_irq, 818 sc->emac_intrhand); 819 820 if (sc->emac_miibus != NULL) { 821 device_delete_child(sc->emac_dev, sc->emac_miibus); 822 bus_generic_detach(sc->emac_dev); 823 } 824 825 if (sc->emac_clk != NULL) 826 clk_disable(sc->emac_clk); 827 828 if (sc->emac_res != NULL) 829 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->emac_res); 830 831 if (sc->emac_irq != NULL) 832 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->emac_irq); 833 834 if (sc->emac_ifp != NULL) 835 if_free(sc->emac_ifp); 836 837 if (mtx_initialized(&sc->emac_mtx)) 838 mtx_destroy(&sc->emac_mtx); 839 840 return (0); 841 } 842 843 static int 844 emac_shutdown(device_t dev) 845 { 846 847 return (emac_suspend(dev)); 848 } 849 850 static int 851 emac_suspend(device_t dev) 852 { 853 struct emac_softc *sc; 854 struct ifnet *ifp; 855 856 sc = device_get_softc(dev); 857 858 EMAC_LOCK(sc); 859 ifp = sc->emac_ifp; 860 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 861 emac_stop_locked(sc); 862 EMAC_UNLOCK(sc); 863 864 return (0); 865 } 866 867 static int 868 emac_resume(device_t dev) 869 { 870 struct emac_softc *sc; 871 struct ifnet *ifp; 872 873 sc = device_get_softc(dev); 874 875 EMAC_LOCK(sc); 876 ifp = sc->emac_ifp; 877 if ((ifp->if_flags & IFF_UP) != 0) { 878 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 879 emac_init_locked(sc); 880 } 881 EMAC_UNLOCK(sc); 882 883 return (0); 884 } 885 886 static int 887 emac_attach(device_t dev) 888 { 889 struct emac_softc *sc; 890 struct ifnet *ifp; 891 int error, rid; 892 uint8_t eaddr[ETHER_ADDR_LEN]; 893 894 sc = device_get_softc(dev); 895 sc->emac_dev = dev; 896 897 error = 0; 898 mtx_init(&sc->emac_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 899 MTX_DEF); 900 callout_init_mtx(&sc->emac_tick_ch, &sc->emac_mtx, 0); 901 902 rid = 0; 903 sc->emac_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 904 RF_ACTIVE); 905 if (sc->emac_res == NULL) { 906 device_printf(dev, "unable to map memory\n"); 907 error = ENXIO; 908 goto fail; 909 } 910 911 sc->emac_tag = rman_get_bustag(sc->emac_res); 912 sc->emac_handle = rman_get_bushandle(sc->emac_res); 913 914 rid = 0; 915 sc->emac_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 916 RF_SHAREABLE | RF_ACTIVE); 917 if (sc->emac_irq == NULL) { 918 device_printf(dev, "cannot allocate IRQ resources.\n"); 919 error = ENXIO; 920 goto fail; 921 } 922 /* Create device sysctl node. */ 923 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 924 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 925 OID_AUTO, "process_limit", 926 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 927 &sc->emac_rx_process_limit, 0, sysctl_hw_emac_proc_limit, "I", 928 "max number of Rx events to process"); 929 930 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT; 931 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 932 "process_limit", &sc->emac_rx_process_limit); 933 if (error == 0) { 934 if (sc->emac_rx_process_limit < EMAC_PROC_MIN || 935 sc->emac_rx_process_limit > EMAC_PROC_MAX) { 936 device_printf(dev, "process_limit value out of range; " 937 "using default: %d\n", EMAC_PROC_DEFAULT); 938 sc->emac_rx_process_limit = EMAC_PROC_DEFAULT; 939 } 940 } 941 /* Setup EMAC */ 942 error = emac_sys_setup(sc); 943 if (error != 0) 944 goto fail; 945 946 emac_reset(sc); 947 948 ifp = sc->emac_ifp = if_alloc(IFT_ETHER); 949 if (ifp == NULL) { 950 device_printf(dev, "unable to allocate ifp\n"); 951 error = ENOSPC; 952 goto fail; 953 } 954 ifp->if_softc = sc; 955 956 /* Setup MII */ 957 error = mii_attach(dev, &sc->emac_miibus, ifp, emac_ifmedia_upd, 958 emac_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 959 if (error != 0) { 960 device_printf(dev, "PHY probe failed\n"); 961 goto fail; 962 } 963 964 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 965 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 966 ifp->if_start = emac_start; 967 ifp->if_ioctl = emac_ioctl; 968 ifp->if_init = emac_init; 969 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 970 971 /* Get MAC address */ 972 emac_get_hwaddr(sc, eaddr); 973 ether_ifattach(ifp, eaddr); 974 975 /* VLAN capability setup. */ 976 ifp->if_capabilities |= IFCAP_VLAN_MTU; 977 ifp->if_capenable = ifp->if_capabilities; 978 /* Tell the upper layer we support VLAN over-sized frames. */ 979 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 980 981 error = bus_setup_intr(dev, sc->emac_irq, INTR_TYPE_NET | INTR_MPSAFE, 982 NULL, emac_intr, sc, &sc->emac_intrhand); 983 if (error != 0) { 984 device_printf(dev, "could not set up interrupt handler.\n"); 985 ether_ifdetach(ifp); 986 goto fail; 987 } 988 989 fail: 990 if (error != 0) 991 emac_detach(dev); 992 return (error); 993 } 994 995 static boolean_t 996 emac_miibus_iowait(struct emac_softc *sc) 997 { 998 uint32_t timeout; 999 1000 for (timeout = 100; timeout != 0; --timeout) { 1001 DELAY(100); 1002 if ((EMAC_READ_REG(sc, EMAC_MAC_MIND) & 0x1) == 0) 1003 return (true); 1004 } 1005 1006 return (false); 1007 } 1008 1009 /* 1010 * The MII bus interface 1011 */ 1012 static int 1013 emac_miibus_readreg(device_t dev, int phy, int reg) 1014 { 1015 struct emac_softc *sc; 1016 int rval; 1017 1018 sc = device_get_softc(dev); 1019 1020 /* Issue phy address and reg */ 1021 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg); 1022 /* Pull up the phy io line */ 1023 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1); 1024 if (!emac_miibus_iowait(sc)) { 1025 device_printf(dev, "timeout waiting for mii read\n"); 1026 return (0); 1027 } 1028 /* Push down the phy io line */ 1029 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0); 1030 /* Read data */ 1031 rval = EMAC_READ_REG(sc, EMAC_MAC_MRDD); 1032 1033 return (rval); 1034 } 1035 1036 static int 1037 emac_miibus_writereg(device_t dev, int phy, int reg, int data) 1038 { 1039 struct emac_softc *sc; 1040 1041 sc = device_get_softc(dev); 1042 1043 /* Issue phy address and reg */ 1044 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg); 1045 /* Write data */ 1046 EMAC_WRITE_REG(sc, EMAC_MAC_MWTD, data); 1047 /* Pull up the phy io line */ 1048 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x1); 1049 if (!emac_miibus_iowait(sc)) { 1050 device_printf(dev, "timeout waiting for mii write\n"); 1051 return (0); 1052 } 1053 /* Push down the phy io line */ 1054 EMAC_WRITE_REG(sc, EMAC_MAC_MCMD, 0x0); 1055 1056 return (0); 1057 } 1058 1059 static void 1060 emac_miibus_statchg(device_t dev) 1061 { 1062 struct emac_softc *sc; 1063 struct mii_data *mii; 1064 struct ifnet *ifp; 1065 uint32_t reg_val; 1066 1067 sc = device_get_softc(dev); 1068 1069 mii = device_get_softc(sc->emac_miibus); 1070 ifp = sc->emac_ifp; 1071 if (mii == NULL || ifp == NULL || 1072 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1073 return; 1074 1075 sc->emac_link = 0; 1076 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1077 (IFM_ACTIVE | IFM_AVALID)) { 1078 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1079 case IFM_10_T: 1080 case IFM_100_TX: 1081 sc->emac_link = 1; 1082 break; 1083 default: 1084 break; 1085 } 1086 } 1087 /* Program MACs with resolved speed/duplex. */ 1088 if (sc->emac_link != 0) { 1089 reg_val = EMAC_READ_REG(sc, EMAC_MAC_IPGT); 1090 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1091 reg_val &= ~EMAC_MAC_IPGT_HD; 1092 reg_val |= EMAC_MAC_IPGT_FD; 1093 } else { 1094 reg_val &= ~EMAC_MAC_IPGT_FD; 1095 reg_val |= EMAC_MAC_IPGT_HD; 1096 } 1097 EMAC_WRITE_REG(sc, EMAC_MAC_IPGT, reg_val); 1098 /* Enable RX/TX */ 1099 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 1100 reg_val |= EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN; 1101 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 1102 } else { 1103 /* Disable RX/TX */ 1104 reg_val = EMAC_READ_REG(sc, EMAC_CTL); 1105 reg_val &= ~(EMAC_CTL_RST | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN); 1106 EMAC_WRITE_REG(sc, EMAC_CTL, reg_val); 1107 } 1108 } 1109 1110 static int 1111 emac_ifmedia_upd(struct ifnet *ifp) 1112 { 1113 struct emac_softc *sc; 1114 struct mii_data *mii; 1115 struct mii_softc *miisc; 1116 int error; 1117 1118 sc = ifp->if_softc; 1119 mii = device_get_softc(sc->emac_miibus); 1120 EMAC_LOCK(sc); 1121 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1122 PHY_RESET(miisc); 1123 error = mii_mediachg(mii); 1124 EMAC_UNLOCK(sc); 1125 1126 return (error); 1127 } 1128 1129 static void 1130 emac_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1131 { 1132 struct emac_softc *sc; 1133 struct mii_data *mii; 1134 1135 sc = ifp->if_softc; 1136 mii = device_get_softc(sc->emac_miibus); 1137 1138 EMAC_LOCK(sc); 1139 mii_pollstat(mii); 1140 ifmr->ifm_active = mii->mii_media_active; 1141 ifmr->ifm_status = mii->mii_media_status; 1142 EMAC_UNLOCK(sc); 1143 } 1144 1145 static device_method_t emac_methods[] = { 1146 /* Device interface */ 1147 DEVMETHOD(device_probe, emac_probe), 1148 DEVMETHOD(device_attach, emac_attach), 1149 DEVMETHOD(device_detach, emac_detach), 1150 DEVMETHOD(device_shutdown, emac_shutdown), 1151 DEVMETHOD(device_suspend, emac_suspend), 1152 DEVMETHOD(device_resume, emac_resume), 1153 1154 /* bus interface, for miibus */ 1155 DEVMETHOD(bus_print_child, bus_generic_print_child), 1156 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1157 1158 /* MII interface */ 1159 DEVMETHOD(miibus_readreg, emac_miibus_readreg), 1160 DEVMETHOD(miibus_writereg, emac_miibus_writereg), 1161 DEVMETHOD(miibus_statchg, emac_miibus_statchg), 1162 1163 DEVMETHOD_END 1164 }; 1165 1166 static driver_t emac_driver = { 1167 "emac", 1168 emac_methods, 1169 sizeof(struct emac_softc) 1170 }; 1171 1172 static devclass_t emac_devclass; 1173 1174 DRIVER_MODULE(emac, simplebus, emac_driver, emac_devclass, 0, 0); 1175 DRIVER_MODULE(miibus, emac, miibus_driver, miibus_devclass, 0, 0); 1176 MODULE_DEPEND(emac, miibus, 1, 1, 1); 1177 MODULE_DEPEND(emac, ether, 1, 1, 1); 1178 1179 static int 1180 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 1181 { 1182 int error, value; 1183 1184 if (arg1 == NULL) 1185 return (EINVAL); 1186 value = *(int *)arg1; 1187 error = sysctl_handle_int(oidp, &value, 0, req); 1188 if (error || req->newptr == NULL) 1189 return (error); 1190 if (value < low || value > high) 1191 return (EINVAL); 1192 *(int *)arg1 = value; 1193 1194 return (0); 1195 } 1196 1197 static int 1198 sysctl_hw_emac_proc_limit(SYSCTL_HANDLER_ARGS) 1199 { 1200 1201 return (sysctl_int_range(oidp, arg1, arg2, req, 1202 EMAC_PROC_MIN, EMAC_PROC_MAX)); 1203 }
Cache object: 0f5c673b3930c806c1c4881e19eeebae
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