socfpga_rstmgr.c

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    1 /*-
    2  * Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com>
    3  * All rights reserved.
    4  *
    5  * This software was developed by SRI International and the University of
    6  * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
    7  * ("CTSRD"), as part of the DARPA CRASH research programme.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28  * SUCH DAMAGE.
   29  */
   30 
   31 /*
   32  * SOCFPGA Reset Manager.
   33  * Chapter 3, Cyclone V Device Handbook (CV-5V2 2014.07.22)
   34  */
   35 
   36 #include <sys/cdefs.h>
   37 __FBSDID("$FreeBSD$");
   38 
   39 #include <sys/param.h>
   40 #include <sys/systm.h>
   41 #include <sys/bus.h>
   42 #include <sys/kernel.h>
   43 #include <sys/module.h>
   44 #include <sys/malloc.h>
   45 #include <sys/rman.h>
   46 #include <sys/timeet.h>
   47 #include <sys/timetc.h>
   48 #include <sys/sysctl.h>
   49 
   50 #include <dev/ofw/openfirm.h>
   51 #include <dev/ofw/ofw_bus.h>
   52 #include <dev/ofw/ofw_bus_subr.h>
   53 
   54 #include <machine/bus.h>
   55 #include <machine/fdt.h>
   56 #include <machine/cpu.h>
   57 #include <machine/intr.h>
   58 
   59 #include <arm/altera/socfpga/socfpga_common.h>
   60 #include <arm/altera/socfpga/socfpga_rstmgr.h>
   61 #include <arm/altera/socfpga/socfpga_l3regs.h>
   62 
   63 struct rstmgr_softc {
   64         struct resource         *res[1];
   65         bus_space_tag_t         bst;
   66         bus_space_handle_t      bsh;
   67         device_t                dev;
   68 };
   69 
   70 struct rstmgr_softc *rstmgr_sc;
   71 
   72 static struct resource_spec rstmgr_spec[] = {
   73         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
   74         { -1, 0 }
   75 };
   76 
   77 enum {
   78         RSTMGR_SYSCTL_FPGA2HPS,
   79         RSTMGR_SYSCTL_LWHPS2FPGA,
   80         RSTMGR_SYSCTL_HPS2FPGA
   81 };
   82 
   83 static int
   84 l3remap(struct rstmgr_softc *sc, int remap, int enable)
   85 {
   86         uint32_t paddr;
   87         bus_addr_t vaddr;
   88         phandle_t node;
   89         int reg;
   90 
   91         /*
   92          * Control whether bridge is visible to L3 masters or not.
   93          * Register is write-only.
   94          */
   95 
   96         reg = REMAP_MPUZERO;
   97         if (enable)
   98                 reg |= (remap);
   99         else
  100                 reg &= ~(remap);
  101 
  102         node = OF_finddevice("l3regs");
  103         if (node == -1) {
  104                 device_printf(sc->dev, "Can't find l3regs node\n");
  105                 return (1);
  106         }
  107 
  108         if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) {
  109                 if (bus_space_map(fdtbus_bs_tag, paddr, 0x4, 0, &vaddr) == 0) {
  110                         bus_space_write_4(fdtbus_bs_tag, vaddr,
  111                             L3REGS_REMAP, reg);
  112                         return (0);
  113                 }
  114         }
  115 
  116         return (1);
  117 }
  118 
  119 static int
  120 rstmgr_sysctl(SYSCTL_HANDLER_ARGS)
  121 {
  122         struct rstmgr_softc *sc;
  123         int enable;
  124         int remap;
  125         int err;
  126         int reg;
  127         int bit;
  128 
  129         sc = arg1;
  130 
  131         switch (arg2) {
  132         case RSTMGR_SYSCTL_FPGA2HPS:
  133                 bit = BRGMODRST_FPGA2HPS;
  134                 remap = 0;
  135                 break;
  136         case RSTMGR_SYSCTL_LWHPS2FPGA:
  137                 bit = BRGMODRST_LWHPS2FPGA;
  138                 remap = REMAP_LWHPS2FPGA;
  139                 break;
  140         case RSTMGR_SYSCTL_HPS2FPGA:
  141                 bit = BRGMODRST_HPS2FPGA;
  142                 remap = REMAP_HPS2FPGA;
  143                 break;
  144         default:
  145                 return (1);
  146         }
  147 
  148         reg = READ4(sc, RSTMGR_BRGMODRST);
  149         enable = reg & bit ? 0 : 1;
  150 
  151         err = sysctl_handle_int(oidp, &enable, 0, req);
  152         if (err || !req->newptr)
  153                 return (err);
  154 
  155         if (enable == 1)
  156                 reg &= ~(bit);
  157         else if (enable == 0)
  158                 reg |= (bit);
  159         else
  160                 return (EINVAL);
  161 
  162         WRITE4(sc, RSTMGR_BRGMODRST, reg);
  163         l3remap(sc, remap, enable);
  164 
  165         return (0);
  166 }
  167 
  168 int
  169 rstmgr_warmreset(uint32_t reg)
  170 {
  171         struct rstmgr_softc *sc;
  172 
  173         sc = rstmgr_sc;
  174         if (sc == NULL)
  175                 return (1);
  176 
  177         /* Request warm reset */
  178         WRITE4(sc, reg, CTRL_SWWARMRSTREQ);
  179 
  180         return (0);
  181 }
  182 
  183 static int
  184 rstmgr_add_sysctl(struct rstmgr_softc *sc)
  185 {
  186         struct sysctl_oid_list *children;
  187         struct sysctl_ctx_list *ctx;
  188 
  189         ctx = device_get_sysctl_ctx(sc->dev);
  190         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
  191 
  192         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fpga2hps",
  193             CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
  194             sc, RSTMGR_SYSCTL_FPGA2HPS,
  195             rstmgr_sysctl, "I", "Enable fpga2hps bridge");
  196         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lwhps2fpga",
  197             CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
  198             sc, RSTMGR_SYSCTL_LWHPS2FPGA,
  199             rstmgr_sysctl, "I", "Enable lwhps2fpga bridge");
  200         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hps2fpga",
  201             CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
  202             sc, RSTMGR_SYSCTL_HPS2FPGA,
  203             rstmgr_sysctl, "I", "Enable hps2fpga bridge");
  204 
  205         return (0);
  206 }
  207 
  208 static int
  209 rstmgr_probe(device_t dev)
  210 {
  211 
  212         if (!ofw_bus_status_okay(dev))
  213                 return (ENXIO);
  214 
  215         if (!ofw_bus_is_compatible(dev, "altr,rst-mgr"))
  216                 return (ENXIO);
  217 
  218         device_set_desc(dev, "Reset Manager");
  219 
  220         return (BUS_PROBE_DEFAULT);
  221 }
  222 
  223 static int
  224 rstmgr_attach(device_t dev)
  225 {
  226         struct rstmgr_softc *sc;
  227 
  228         sc = device_get_softc(dev);
  229         sc->dev = dev;
  230 
  231         if (bus_alloc_resources(dev, rstmgr_spec, sc->res)) {
  232                 device_printf(dev, "could not allocate resources\n");
  233                 return (ENXIO);
  234         }
  235 
  236         /* Memory interface */
  237         sc->bst = rman_get_bustag(sc->res[0]);
  238         sc->bsh = rman_get_bushandle(sc->res[0]);
  239 
  240         rstmgr_sc = sc;
  241         rstmgr_add_sysctl(sc);
  242 
  243         return (0);
  244 }
  245 
  246 static device_method_t rstmgr_methods[] = {
  247         DEVMETHOD(device_probe,         rstmgr_probe),
  248         DEVMETHOD(device_attach,        rstmgr_attach),
  249         { 0, 0 }
  250 };
  251 
  252 static driver_t rstmgr_driver = {
  253         "rstmgr",
  254         rstmgr_methods,
  255         sizeof(struct rstmgr_softc),
  256 };
  257 
  258 DRIVER_MODULE(rstmgr, simplebus, rstmgr_driver, 0, 0);

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sys/arm/altera/socfpga/socfpga_rstmgr.c