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sys/arm/arm/busdma_machdep.c
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1 /*- 2 * Copyright (c) 2004 Olivier Houchard 3 * Copyright (c) 2002 Peter Grehan 4 * Copyright (c) 1997, 1998 Justin T. Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions, and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * From i386/busdma_machdep.c,v 1.26 2002/04/19 22:58:09 alfred 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 /* 35 * ARM bus dma support routines 36 */ 37 38 #define _ARM32_BUS_DMA_PRIVATE 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 #include <sys/bus.h> 43 #include <sys/interrupt.h> 44 #include <sys/lock.h> 45 #include <sys/proc.h> 46 #include <sys/mutex.h> 47 #include <sys/mbuf.h> 48 #include <sys/uio.h> 49 #include <sys/ktr.h> 50 #include <sys/kernel.h> 51 #include <sys/sysctl.h> 52 53 #include <vm/vm.h> 54 #include <vm/vm_page.h> 55 #include <vm/vm_map.h> 56 57 #include <machine/atomic.h> 58 #include <machine/bus.h> 59 #include <machine/cpufunc.h> 60 #include <machine/md_var.h> 61 62 #define MAX_BPAGES 64 63 #define BUS_DMA_COULD_BOUNCE BUS_DMA_BUS3 64 #define BUS_DMA_MIN_ALLOC_COMP BUS_DMA_BUS4 65 66 struct bounce_zone; 67 68 struct bus_dma_tag { 69 bus_dma_tag_t parent; 70 bus_size_t alignment; 71 bus_size_t boundary; 72 bus_addr_t lowaddr; 73 bus_addr_t highaddr; 74 bus_dma_filter_t *filter; 75 void *filterarg; 76 bus_size_t maxsize; 77 u_int nsegments; 78 bus_size_t maxsegsz; 79 int flags; 80 int ref_count; 81 int map_count; 82 bus_dma_lock_t *lockfunc; 83 void *lockfuncarg; 84 /* 85 * DMA range for this tag. If the page doesn't fall within 86 * one of these ranges, an error is returned. The caller 87 * may then decide what to do with the transfer. If the 88 * range pointer is NULL, it is ignored. 89 */ 90 struct arm32_dma_range *ranges; 91 int _nranges; 92 struct bounce_zone *bounce_zone; 93 }; 94 95 struct bounce_page { 96 vm_offset_t vaddr; /* kva of bounce buffer */ 97 vm_offset_t vaddr_nocache; /* kva of bounce buffer uncached */ 98 bus_addr_t busaddr; /* Physical address */ 99 vm_offset_t datavaddr; /* kva of client data */ 100 bus_size_t datacount; /* client data count */ 101 STAILQ_ENTRY(bounce_page) links; 102 }; 103 104 int busdma_swi_pending; 105 106 struct bounce_zone { 107 STAILQ_ENTRY(bounce_zone) links; 108 STAILQ_HEAD(bp_list, bounce_page) bounce_page_list; 109 int total_bpages; 110 int free_bpages; 111 int reserved_bpages; 112 int active_bpages; 113 int total_bounced; 114 int total_deferred; 115 bus_size_t alignment; 116 bus_addr_t lowaddr; 117 char zoneid[8]; 118 char lowaddrid[20]; 119 struct sysctl_ctx_list sysctl_tree; 120 struct sysctl_oid *sysctl_tree_top; 121 }; 122 123 static struct mtx bounce_lock; 124 static int total_bpages; 125 static int busdma_zonecount; 126 static STAILQ_HEAD(, bounce_zone) bounce_zone_list; 127 128 SYSCTL_NODE(_hw, OID_AUTO, busdma, CTLFLAG_RD, 0, "Busdma parameters"); 129 SYSCTL_INT(_hw_busdma, OID_AUTO, total_bpages, CTLFLAG_RD, &total_bpages, 0, 130 "Total bounce pages"); 131 132 #define DMAMAP_LINEAR 0x1 133 #define DMAMAP_MBUF 0x2 134 #define DMAMAP_UIO 0x4 135 #define DMAMAP_ALLOCATED 0x10 136 #define DMAMAP_TYPE_MASK (DMAMAP_LINEAR|DMAMAP_MBUF|DMAMAP_UIO) 137 #define DMAMAP_COHERENT 0x8 138 struct bus_dmamap { 139 struct bp_list bpages; 140 int pagesneeded; 141 int pagesreserved; 142 bus_dma_tag_t dmat; 143 int flags; 144 void *buffer; 145 void *origbuffer; 146 void *allocbuffer; 147 TAILQ_ENTRY(bus_dmamap) freelist; 148 int len; 149 STAILQ_ENTRY(bus_dmamap) links; 150 bus_dmamap_callback_t *callback; 151 void *callback_arg; 152 153 }; 154 155 static STAILQ_HEAD(, bus_dmamap) bounce_map_waitinglist; 156 static STAILQ_HEAD(, bus_dmamap) bounce_map_callbacklist; 157 158 static TAILQ_HEAD(,bus_dmamap) dmamap_freelist = 159 TAILQ_HEAD_INITIALIZER(dmamap_freelist); 160 161 #define BUSDMA_STATIC_MAPS 500 162 static struct bus_dmamap map_pool[BUSDMA_STATIC_MAPS]; 163 164 static struct mtx busdma_mtx; 165 166 MTX_SYSINIT(busdma_mtx, &busdma_mtx, "busdma lock", MTX_DEF); 167 168 static void init_bounce_pages(void *dummy); 169 static int alloc_bounce_zone(bus_dma_tag_t dmat); 170 static int alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages); 171 static int reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, 172 int commit); 173 static bus_addr_t add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, 174 vm_offset_t vaddr, bus_size_t size); 175 static void free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage); 176 177 /* Default tag, as most drivers provide no parent tag. */ 178 bus_dma_tag_t arm_root_dma_tag; 179 180 /* 181 * Return true if a match is made. 182 * 183 * To find a match walk the chain of bus_dma_tag_t's looking for 'paddr'. 184 * 185 * If paddr is within the bounds of the dma tag then call the filter callback 186 * to check for a match, if there is no filter callback then assume a match. 187 */ 188 static int 189 run_filter(bus_dma_tag_t dmat, bus_addr_t paddr) 190 { 191 int retval; 192 193 retval = 0; 194 195 do { 196 if (((paddr > dmat->lowaddr && paddr <= dmat->highaddr) 197 || ((paddr & (dmat->alignment - 1)) != 0)) 198 && (dmat->filter == NULL 199 || (*dmat->filter)(dmat->filterarg, paddr) != 0)) 200 retval = 1; 201 202 dmat = dmat->parent; 203 } while (retval == 0 && dmat != NULL); 204 return (retval); 205 } 206 207 static void 208 arm_dmamap_freelist_init(void *dummy) 209 { 210 int i; 211 212 for (i = 0; i < BUSDMA_STATIC_MAPS; i++) 213 TAILQ_INSERT_HEAD(&dmamap_freelist, &map_pool[i], freelist); 214 } 215 216 SYSINIT(busdma, SI_SUB_VM, SI_ORDER_ANY, arm_dmamap_freelist_init, NULL); 217 218 /* 219 * Check to see if the specified page is in an allowed DMA range. 220 */ 221 222 static __inline int 223 bus_dmamap_load_buffer(bus_dma_tag_t dmat, bus_dma_segment_t *segs, 224 bus_dmamap_t map, void *buf, bus_size_t buflen, struct pmap *pmap, 225 int flags, vm_offset_t *lastaddrp, int *segp); 226 227 static __inline int 228 _bus_dma_can_bounce(vm_offset_t lowaddr, vm_offset_t highaddr) 229 { 230 int i; 231 for (i = 0; phys_avail[i] && phys_avail[i + 1]; i += 2) { 232 if ((lowaddr >= phys_avail[i] && lowaddr <= phys_avail[i + 1]) 233 || (lowaddr < phys_avail[i] && 234 highaddr > phys_avail[i])) 235 return (1); 236 } 237 return (0); 238 } 239 240 static __inline struct arm32_dma_range * 241 _bus_dma_inrange(struct arm32_dma_range *ranges, int nranges, 242 bus_addr_t curaddr) 243 { 244 struct arm32_dma_range *dr; 245 int i; 246 247 for (i = 0, dr = ranges; i < nranges; i++, dr++) { 248 if (curaddr >= dr->dr_sysbase && 249 round_page(curaddr) <= (dr->dr_sysbase + dr->dr_len)) 250 return (dr); 251 } 252 253 return (NULL); 254 } 255 /* 256 * Convenience function for manipulating driver locks from busdma (during 257 * busdma_swi, for example). Drivers that don't provide their own locks 258 * should specify &Giant to dmat->lockfuncarg. Drivers that use their own 259 * non-mutex locking scheme don't have to use this at all. 260 */ 261 void 262 busdma_lock_mutex(void *arg, bus_dma_lock_op_t op) 263 { 264 struct mtx *dmtx; 265 266 dmtx = (struct mtx *)arg; 267 switch (op) { 268 case BUS_DMA_LOCK: 269 mtx_lock(dmtx); 270 break; 271 case BUS_DMA_UNLOCK: 272 mtx_unlock(dmtx); 273 break; 274 default: 275 panic("Unknown operation 0x%x for busdma_lock_mutex!", op); 276 } 277 } 278 279 /* 280 * dflt_lock should never get called. It gets put into the dma tag when 281 * lockfunc == NULL, which is only valid if the maps that are associated 282 * with the tag are meant to never be defered. 283 * XXX Should have a way to identify which driver is responsible here. 284 */ 285 static void 286 dflt_lock(void *arg, bus_dma_lock_op_t op) 287 { 288 #ifdef INVARIANTS 289 panic("driver error: busdma dflt_lock called"); 290 #else 291 printf("DRIVER_ERROR: busdma dflt_lock called\n"); 292 #endif 293 } 294 295 static __inline bus_dmamap_t 296 _busdma_alloc_dmamap(void) 297 { 298 bus_dmamap_t map; 299 300 mtx_lock(&busdma_mtx); 301 map = TAILQ_FIRST(&dmamap_freelist); 302 if (map) 303 TAILQ_REMOVE(&dmamap_freelist, map, freelist); 304 mtx_unlock(&busdma_mtx); 305 if (!map) { 306 map = malloc(sizeof(*map), M_DEVBUF, M_NOWAIT | M_ZERO); 307 if (map) 308 map->flags = DMAMAP_ALLOCATED; 309 } else 310 map->flags = 0; 311 STAILQ_INIT(&map->bpages); 312 return (map); 313 } 314 315 static __inline void 316 _busdma_free_dmamap(bus_dmamap_t map) 317 { 318 if (map->flags & DMAMAP_ALLOCATED) 319 free(map, M_DEVBUF); 320 else { 321 mtx_lock(&busdma_mtx); 322 TAILQ_INSERT_HEAD(&dmamap_freelist, map, freelist); 323 mtx_unlock(&busdma_mtx); 324 } 325 } 326 327 /* 328 * Allocate a device specific dma_tag. 329 */ 330 #define SEG_NB 1024 331 332 int 333 bus_dma_tag_create(bus_dma_tag_t parent, bus_size_t alignment, 334 bus_size_t boundary, bus_addr_t lowaddr, 335 bus_addr_t highaddr, bus_dma_filter_t *filter, 336 void *filterarg, bus_size_t maxsize, int nsegments, 337 bus_size_t maxsegsz, int flags, bus_dma_lock_t *lockfunc, 338 void *lockfuncarg, bus_dma_tag_t *dmat) 339 { 340 bus_dma_tag_t newtag; 341 int error = 0; 342 /* Return a NULL tag on failure */ 343 *dmat = NULL; 344 if (!parent) 345 parent = arm_root_dma_tag; 346 347 newtag = (bus_dma_tag_t)malloc(sizeof(*newtag), M_DEVBUF, M_NOWAIT); 348 if (newtag == NULL) { 349 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d", 350 __func__, newtag, 0, error); 351 return (ENOMEM); 352 } 353 354 newtag->parent = parent; 355 newtag->alignment = alignment; 356 newtag->boundary = boundary; 357 newtag->lowaddr = trunc_page((vm_offset_t)lowaddr) + (PAGE_SIZE - 1); 358 newtag->highaddr = trunc_page((vm_offset_t)highaddr) + (PAGE_SIZE - 1); 359 newtag->filter = filter; 360 newtag->filterarg = filterarg; 361 newtag->maxsize = maxsize; 362 newtag->nsegments = nsegments; 363 newtag->maxsegsz = maxsegsz; 364 newtag->flags = flags; 365 newtag->ref_count = 1; /* Count ourself */ 366 newtag->map_count = 0; 367 newtag->ranges = bus_dma_get_range(); 368 newtag->_nranges = bus_dma_get_range_nb(); 369 if (lockfunc != NULL) { 370 newtag->lockfunc = lockfunc; 371 newtag->lockfuncarg = lockfuncarg; 372 } else { 373 newtag->lockfunc = dflt_lock; 374 newtag->lockfuncarg = NULL; 375 } 376 /* 377 * Take into account any restrictions imposed by our parent tag 378 */ 379 if (parent != NULL) { 380 newtag->lowaddr = min(parent->lowaddr, newtag->lowaddr); 381 newtag->highaddr = max(parent->highaddr, newtag->highaddr); 382 if (newtag->boundary == 0) 383 newtag->boundary = parent->boundary; 384 else if (parent->boundary != 0) 385 newtag->boundary = min(parent->boundary, 386 newtag->boundary); 387 if ((newtag->filter != NULL) || 388 ((parent->flags & BUS_DMA_COULD_BOUNCE) != 0)) 389 newtag->flags |= BUS_DMA_COULD_BOUNCE; 390 if (newtag->filter == NULL) { 391 /* 392 * Short circuit looking at our parent directly 393 * since we have encapsulated all of its information 394 */ 395 newtag->filter = parent->filter; 396 newtag->filterarg = parent->filterarg; 397 newtag->parent = parent->parent; 398 } 399 if (newtag->parent != NULL) 400 atomic_add_int(&parent->ref_count, 1); 401 } 402 if (_bus_dma_can_bounce(newtag->lowaddr, newtag->highaddr) 403 || newtag->alignment > 1) 404 newtag->flags |= BUS_DMA_COULD_BOUNCE; 405 406 if (((newtag->flags & BUS_DMA_COULD_BOUNCE) != 0) && 407 (flags & BUS_DMA_ALLOCNOW) != 0) { 408 struct bounce_zone *bz; 409 410 /* Must bounce */ 411 412 if ((error = alloc_bounce_zone(newtag)) != 0) { 413 free(newtag, M_DEVBUF); 414 return (error); 415 } 416 bz = newtag->bounce_zone; 417 418 if (ptoa(bz->total_bpages) < maxsize) { 419 int pages; 420 421 pages = atop(maxsize) - bz->total_bpages; 422 423 /* Add pages to our bounce pool */ 424 if (alloc_bounce_pages(newtag, pages) < pages) 425 error = ENOMEM; 426 } 427 /* Performed initial allocation */ 428 newtag->flags |= BUS_DMA_MIN_ALLOC_COMP; 429 } else 430 newtag->bounce_zone = NULL; 431 if (error != 0) 432 free(newtag, M_DEVBUF); 433 else 434 *dmat = newtag; 435 CTR4(KTR_BUSDMA, "%s returned tag %p tag flags 0x%x error %d", 436 __func__, newtag, (newtag != NULL ? newtag->flags : 0), error); 437 438 return (error); 439 } 440 441 int 442 bus_dma_tag_destroy(bus_dma_tag_t dmat) 443 { 444 #ifdef KTR 445 bus_dma_tag_t dmat_copy = dmat; 446 #endif 447 448 if (dmat != NULL) { 449 450 if (dmat->map_count != 0) 451 return (EBUSY); 452 453 while (dmat != NULL) { 454 bus_dma_tag_t parent; 455 456 parent = dmat->parent; 457 atomic_subtract_int(&dmat->ref_count, 1); 458 if (dmat->ref_count == 0) { 459 free(dmat, M_DEVBUF); 460 /* 461 * Last reference count, so 462 * release our reference 463 * count on our parent. 464 */ 465 dmat = parent; 466 } else 467 dmat = NULL; 468 } 469 } 470 CTR2(KTR_BUSDMA, "%s tag %p", __func__, dmat_copy); 471 472 return (0); 473 } 474 475 #include <sys/kdb.h> 476 /* 477 * Allocate a handle for mapping from kva/uva/physical 478 * address space into bus device space. 479 */ 480 int 481 bus_dmamap_create(bus_dma_tag_t dmat, int flags, bus_dmamap_t *mapp) 482 { 483 bus_dmamap_t newmap; 484 int error = 0; 485 486 newmap = _busdma_alloc_dmamap(); 487 if (newmap == NULL) { 488 CTR3(KTR_BUSDMA, "%s: tag %p error %d", __func__, dmat, ENOMEM); 489 return (ENOMEM); 490 } 491 *mapp = newmap; 492 newmap->dmat = dmat; 493 newmap->allocbuffer = NULL; 494 dmat->map_count++; 495 496 /* 497 * Bouncing might be required if the driver asks for an active 498 * exclusion region, a data alignment that is stricter than 1, and/or 499 * an active address boundary. 500 */ 501 if (dmat->flags & BUS_DMA_COULD_BOUNCE) { 502 503 /* Must bounce */ 504 struct bounce_zone *bz; 505 int maxpages; 506 507 if (dmat->bounce_zone == NULL) { 508 if ((error = alloc_bounce_zone(dmat)) != 0) { 509 _busdma_free_dmamap(newmap); 510 *mapp = NULL; 511 return (error); 512 } 513 } 514 bz = dmat->bounce_zone; 515 516 /* Initialize the new map */ 517 STAILQ_INIT(&((*mapp)->bpages)); 518 519 /* 520 * Attempt to add pages to our pool on a per-instance 521 * basis up to a sane limit. 522 */ 523 maxpages = MAX_BPAGES; 524 if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0 525 || (dmat->map_count > 0 && bz->total_bpages < maxpages)) { 526 int pages; 527 528 pages = MAX(atop(dmat->maxsize), 1); 529 pages = MIN(maxpages - bz->total_bpages, pages); 530 pages = MAX(pages, 1); 531 if (alloc_bounce_pages(dmat, pages) < pages) 532 error = ENOMEM; 533 534 if ((dmat->flags & BUS_DMA_MIN_ALLOC_COMP) == 0) { 535 if (error == 0) 536 dmat->flags |= BUS_DMA_MIN_ALLOC_COMP; 537 } else { 538 error = 0; 539 } 540 } 541 } 542 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 543 __func__, dmat, dmat->flags, error); 544 545 return (0); 546 } 547 548 /* 549 * Destroy a handle for mapping from kva/uva/physical 550 * address space into bus device space. 551 */ 552 int 553 bus_dmamap_destroy(bus_dma_tag_t dmat, bus_dmamap_t map) 554 { 555 556 _busdma_free_dmamap(map); 557 if (STAILQ_FIRST(&map->bpages) != NULL) { 558 CTR3(KTR_BUSDMA, "%s: tag %p error %d", 559 __func__, dmat, EBUSY); 560 return (EBUSY); 561 } 562 dmat->map_count--; 563 CTR2(KTR_BUSDMA, "%s: tag %p error 0", __func__, dmat); 564 return (0); 565 } 566 567 /* 568 * Allocate a piece of memory that can be efficiently mapped into 569 * bus device space based on the constraints lited in the dma tag. 570 * A dmamap to for use with dmamap_load is also allocated. 571 */ 572 int 573 bus_dmamem_alloc(bus_dma_tag_t dmat, void** vaddr, int flags, 574 bus_dmamap_t *mapp) 575 { 576 bus_dmamap_t newmap = NULL; 577 578 int mflags; 579 580 if (flags & BUS_DMA_NOWAIT) 581 mflags = M_NOWAIT; 582 else 583 mflags = M_WAITOK; 584 if (flags & BUS_DMA_ZERO) 585 mflags |= M_ZERO; 586 587 newmap = _busdma_alloc_dmamap(); 588 if (newmap == NULL) { 589 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d", 590 __func__, dmat, dmat->flags, ENOMEM); 591 return (ENOMEM); 592 } 593 dmat->map_count++; 594 *mapp = newmap; 595 newmap->dmat = dmat; 596 597 if (dmat->maxsize <= PAGE_SIZE && 598 (dmat->alignment < dmat->maxsize) && 599 !_bus_dma_can_bounce(dmat->lowaddr, dmat->highaddr)) { 600 *vaddr = malloc(dmat->maxsize, M_DEVBUF, mflags); 601 } else { 602 /* 603 * XXX Use Contigmalloc until it is merged into this facility 604 * and handles multi-seg allocations. Nobody is doing 605 * multi-seg allocations yet though. 606 */ 607 *vaddr = contigmalloc(dmat->maxsize, M_DEVBUF, mflags, 608 0ul, dmat->lowaddr, dmat->alignment? dmat->alignment : 1ul, 609 dmat->boundary); 610 } 611 if (*vaddr == NULL) { 612 if (newmap != NULL) { 613 _busdma_free_dmamap(newmap); 614 dmat->map_count--; 615 } 616 *mapp = NULL; 617 return (ENOMEM); 618 } 619 if (flags & BUS_DMA_COHERENT) { 620 void *tmpaddr = arm_remap_nocache( 621 (void *)((vm_offset_t)*vaddr &~ PAGE_MASK), 622 dmat->maxsize + ((vm_offset_t)*vaddr & PAGE_MASK)); 623 624 if (tmpaddr) { 625 tmpaddr = (void *)((vm_offset_t)(tmpaddr) + 626 ((vm_offset_t)*vaddr & PAGE_MASK)); 627 newmap->origbuffer = *vaddr; 628 newmap->allocbuffer = tmpaddr; 629 cpu_idcache_wbinv_range((vm_offset_t)*vaddr, 630 dmat->maxsize); 631 *vaddr = tmpaddr; 632 } else 633 newmap->origbuffer = newmap->allocbuffer = NULL; 634 } else 635 newmap->origbuffer = newmap->allocbuffer = NULL; 636 return (0); 637 } 638 639 /* 640 * Free a piece of memory and it's allocated dmamap, that was allocated 641 * via bus_dmamem_alloc. Make the same choice for free/contigfree. 642 */ 643 void 644 bus_dmamem_free(bus_dma_tag_t dmat, void *vaddr, bus_dmamap_t map) 645 { 646 if (map->allocbuffer) { 647 KASSERT(map->allocbuffer == vaddr, 648 ("Trying to freeing the wrong DMA buffer")); 649 vaddr = map->origbuffer; 650 arm_unmap_nocache(map->allocbuffer, dmat->maxsize); 651 } 652 if (dmat->maxsize <= PAGE_SIZE && 653 dmat->alignment < dmat->maxsize && 654 !_bus_dma_can_bounce(dmat->lowaddr, dmat->highaddr)) 655 free(vaddr, M_DEVBUF); 656 else { 657 contigfree(vaddr, dmat->maxsize, M_DEVBUF); 658 } 659 dmat->map_count--; 660 _busdma_free_dmamap(map); 661 CTR3(KTR_BUSDMA, "%s: tag %p flags 0x%x", __func__, dmat, dmat->flags); 662 } 663 664 static int 665 _bus_dmamap_count_pages(bus_dma_tag_t dmat, bus_dmamap_t map, pmap_t pmap, 666 void *buf, bus_size_t buflen, int flags) 667 { 668 vm_offset_t vaddr; 669 vm_offset_t vendaddr; 670 bus_addr_t paddr; 671 672 if ((map->pagesneeded == 0)) { 673 CTR3(KTR_BUSDMA, "lowaddr= %d, boundary= %d, alignment= %d", 674 dmat->lowaddr, dmat->boundary, dmat->alignment); 675 CTR2(KTR_BUSDMA, "map= %p, pagesneeded= %d", 676 map, map->pagesneeded); 677 /* 678 * Count the number of bounce pages 679 * needed in order to complete this transfer 680 */ 681 vaddr = trunc_page((vm_offset_t)buf); 682 vendaddr = (vm_offset_t)buf + buflen; 683 684 while (vaddr < vendaddr) { 685 if (__predict_true(pmap == pmap_kernel())) 686 paddr = pmap_kextract(vaddr); 687 else 688 paddr = pmap_extract(pmap, vaddr); 689 if (((dmat->flags & BUS_DMA_COULD_BOUNCE) != 0) && 690 run_filter(dmat, paddr) != 0) 691 map->pagesneeded++; 692 vaddr += PAGE_SIZE; 693 } 694 CTR1(KTR_BUSDMA, "pagesneeded= %d\n", map->pagesneeded); 695 } 696 697 /* Reserve Necessary Bounce Pages */ 698 if (map->pagesneeded != 0) { 699 mtx_lock(&bounce_lock); 700 if (flags & BUS_DMA_NOWAIT) { 701 if (reserve_bounce_pages(dmat, map, 0) != 0) { 702 mtx_unlock(&bounce_lock); 703 return (ENOMEM); 704 } 705 } else { 706 if (reserve_bounce_pages(dmat, map, 1) != 0) { 707 /* Queue us for resources */ 708 STAILQ_INSERT_TAIL(&bounce_map_waitinglist, 709 map, links); 710 mtx_unlock(&bounce_lock); 711 return (EINPROGRESS); 712 } 713 } 714 mtx_unlock(&bounce_lock); 715 } 716 717 return (0); 718 } 719 720 /* 721 * Utility function to load a linear buffer. lastaddrp holds state 722 * between invocations (for multiple-buffer loads). segp contains 723 * the starting segment on entrance, and the ending segment on exit. 724 * first indicates if this is the first invocation of this function. 725 */ 726 static __inline int 727 bus_dmamap_load_buffer(bus_dma_tag_t dmat, bus_dma_segment_t *segs, 728 bus_dmamap_t map, void *buf, bus_size_t buflen, struct pmap *pmap, 729 int flags, vm_offset_t *lastaddrp, int *segp) 730 { 731 bus_size_t sgsize; 732 bus_addr_t curaddr, lastaddr, baddr, bmask; 733 vm_offset_t vaddr = (vm_offset_t)buf; 734 int seg; 735 int error = 0; 736 pd_entry_t *pde; 737 pt_entry_t pte; 738 pt_entry_t *ptep; 739 740 lastaddr = *lastaddrp; 741 bmask = ~(dmat->boundary - 1); 742 743 if ((dmat->flags & BUS_DMA_COULD_BOUNCE) != 0) { 744 error = _bus_dmamap_count_pages(dmat, map, pmap, buf, buflen, 745 flags); 746 if (error) 747 return (error); 748 } 749 CTR3(KTR_BUSDMA, "lowaddr= %d boundary= %d, " 750 "alignment= %d", dmat->lowaddr, dmat->boundary, dmat->alignment); 751 752 for (seg = *segp; buflen > 0 ; ) { 753 /* 754 * Get the physical address for this segment. 755 * 756 * XXX Don't support checking for coherent mappings 757 * XXX in user address space. 758 */ 759 if (__predict_true(pmap == pmap_kernel())) { 760 if (pmap_get_pde_pte(pmap, vaddr, &pde, &ptep) == FALSE) 761 return (EFAULT); 762 763 if (__predict_false(pmap_pde_section(pde))) { 764 if (*pde & L1_S_SUPERSEC) 765 curaddr = (*pde & L1_SUP_FRAME) | 766 (vaddr & L1_SUP_OFFSET); 767 else 768 curaddr = (*pde & L1_S_FRAME) | 769 (vaddr & L1_S_OFFSET); 770 if (*pde & L1_S_CACHE_MASK) { 771 map->flags &= 772 ~DMAMAP_COHERENT; 773 } 774 } else { 775 pte = *ptep; 776 KASSERT((pte & L2_TYPE_MASK) != L2_TYPE_INV, 777 ("INV type")); 778 if (__predict_false((pte & L2_TYPE_MASK) 779 == L2_TYPE_L)) { 780 curaddr = (pte & L2_L_FRAME) | 781 (vaddr & L2_L_OFFSET); 782 if (pte & L2_L_CACHE_MASK) { 783 map->flags &= 784 ~DMAMAP_COHERENT; 785 786 } 787 } else { 788 curaddr = (pte & L2_S_FRAME) | 789 (vaddr & L2_S_OFFSET); 790 if (pte & L2_S_CACHE_MASK) { 791 map->flags &= 792 ~DMAMAP_COHERENT; 793 } 794 } 795 } 796 } else { 797 curaddr = pmap_extract(pmap, vaddr); 798 map->flags &= ~DMAMAP_COHERENT; 799 } 800 801 /* 802 * Compute the segment size, and adjust counts. 803 */ 804 sgsize = PAGE_SIZE - ((u_long)curaddr & PAGE_MASK); 805 if (sgsize > dmat->maxsegsz) 806 sgsize = dmat->maxsegsz; 807 if (buflen < sgsize) 808 sgsize = buflen; 809 810 /* 811 * Make sure we don't cross any boundaries. 812 */ 813 if (dmat->boundary > 0) { 814 baddr = (curaddr + dmat->boundary) & bmask; 815 if (sgsize > (baddr - curaddr)) 816 sgsize = (baddr - curaddr); 817 } 818 if (((dmat->flags & BUS_DMA_COULD_BOUNCE) != 0) && 819 map->pagesneeded != 0 && run_filter(dmat, curaddr)) 820 curaddr = add_bounce_page(dmat, map, vaddr, sgsize); 821 822 if (dmat->ranges) { 823 struct arm32_dma_range *dr; 824 825 dr = _bus_dma_inrange(dmat->ranges, dmat->_nranges, 826 curaddr); 827 if (dr == NULL) 828 return (EINVAL); 829 /* 830 * In a valid DMA range. Translate the physical 831 * memory address to an address in the DMA window. 832 */ 833 curaddr = (curaddr - dr->dr_sysbase) + dr->dr_busbase; 834 835 } 836 837 /* 838 * Insert chunk into a segment, coalescing with 839 * the previous segment if possible. 840 */ 841 if (seg >= 0 && curaddr == lastaddr && 842 (segs[seg].ds_len + sgsize) <= dmat->maxsegsz && 843 (dmat->boundary == 0 || 844 (segs[seg].ds_addr & bmask) == 845 (curaddr & bmask))) { 846 segs[seg].ds_len += sgsize; 847 goto segdone; 848 } else { 849 if (++seg >= dmat->nsegments) 850 break; 851 segs[seg].ds_addr = curaddr; 852 segs[seg].ds_len = sgsize; 853 } 854 if (error) 855 break; 856 segdone: 857 lastaddr = curaddr + sgsize; 858 vaddr += sgsize; 859 buflen -= sgsize; 860 } 861 862 *segp = seg; 863 *lastaddrp = lastaddr; 864 865 /* 866 * Did we fit? 867 */ 868 if (buflen != 0) 869 error = EFBIG; /* XXX better return value here? */ 870 return (error); 871 } 872 873 /* 874 * Map the buffer buf into bus space using the dmamap map. 875 */ 876 int 877 bus_dmamap_load(bus_dma_tag_t dmat, bus_dmamap_t map, void *buf, 878 bus_size_t buflen, bus_dmamap_callback_t *callback, 879 void *callback_arg, int flags) 880 { 881 vm_offset_t lastaddr = 0; 882 int error, nsegs = -1; 883 #ifdef __CC_SUPPORTS_DYNAMIC_ARRAY_INIT 884 bus_dma_segment_t dm_segments[dmat->nsegments]; 885 #else 886 bus_dma_segment_t dm_segments[BUS_DMAMAP_NSEGS]; 887 #endif 888 889 KASSERT(dmat != NULL, ("dmatag is NULL")); 890 KASSERT(map != NULL, ("dmamap is NULL")); 891 map->callback = callback; 892 map->callback_arg = callback_arg; 893 map->flags &= ~DMAMAP_TYPE_MASK; 894 map->flags |= DMAMAP_LINEAR|DMAMAP_COHERENT; 895 map->buffer = buf; 896 map->len = buflen; 897 error = bus_dmamap_load_buffer(dmat, 898 dm_segments, map, buf, buflen, kernel_pmap, 899 flags, &lastaddr, &nsegs); 900 if (error == EINPROGRESS) 901 return (error); 902 if (error) 903 (*callback)(callback_arg, NULL, 0, error); 904 else 905 (*callback)(callback_arg, dm_segments, nsegs + 1, error); 906 907 CTR5(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d nsegs %d", 908 __func__, dmat, dmat->flags, nsegs + 1, error); 909 910 return (error); 911 } 912 913 /* 914 * Like bus_dmamap_load(), but for mbufs. 915 */ 916 int 917 bus_dmamap_load_mbuf(bus_dma_tag_t dmat, bus_dmamap_t map, struct mbuf *m0, 918 bus_dmamap_callback2_t *callback, void *callback_arg, 919 int flags) 920 { 921 #ifdef __CC_SUPPORTS_DYNAMIC_ARRAY_INIT 922 bus_dma_segment_t dm_segments[dmat->nsegments]; 923 #else 924 bus_dma_segment_t dm_segments[BUS_DMAMAP_NSEGS]; 925 #endif 926 int nsegs = -1, error = 0; 927 928 M_ASSERTPKTHDR(m0); 929 930 map->flags &= ~DMAMAP_TYPE_MASK; 931 map->flags |= DMAMAP_MBUF | DMAMAP_COHERENT; 932 map->buffer = m0; 933 map->len = 0; 934 if (m0->m_pkthdr.len <= dmat->maxsize) { 935 vm_offset_t lastaddr = 0; 936 struct mbuf *m; 937 938 for (m = m0; m != NULL && error == 0; m = m->m_next) { 939 if (m->m_len > 0) { 940 error = bus_dmamap_load_buffer(dmat, 941 dm_segments, map, m->m_data, m->m_len, 942 pmap_kernel(), flags, &lastaddr, &nsegs); 943 map->len += m->m_len; 944 } 945 } 946 } else { 947 error = EINVAL; 948 } 949 950 if (error) { 951 /* 952 * force "no valid mappings" on error in callback. 953 */ 954 (*callback)(callback_arg, dm_segments, 0, 0, error); 955 } else { 956 (*callback)(callback_arg, dm_segments, nsegs + 1, 957 m0->m_pkthdr.len, error); 958 } 959 CTR5(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d nsegs %d", 960 __func__, dmat, dmat->flags, error, nsegs + 1); 961 962 return (error); 963 } 964 965 int 966 bus_dmamap_load_mbuf_sg(bus_dma_tag_t dmat, bus_dmamap_t map, 967 struct mbuf *m0, bus_dma_segment_t *segs, int *nsegs, 968 int flags) 969 { 970 int error = 0; 971 M_ASSERTPKTHDR(m0); 972 973 flags |= BUS_DMA_NOWAIT; 974 *nsegs = -1; 975 map->flags &= ~DMAMAP_TYPE_MASK; 976 map->flags |= DMAMAP_MBUF | DMAMAP_COHERENT; 977 map->buffer = m0; 978 map->len = 0; 979 if (m0->m_pkthdr.len <= dmat->maxsize) { 980 vm_offset_t lastaddr = 0; 981 struct mbuf *m; 982 983 for (m = m0; m != NULL && error == 0; m = m->m_next) { 984 if (m->m_len > 0) { 985 error = bus_dmamap_load_buffer(dmat, segs, map, 986 m->m_data, m->m_len, 987 pmap_kernel(), flags, &lastaddr, 988 nsegs); 989 map->len += m->m_len; 990 } 991 } 992 } else { 993 error = EINVAL; 994 } 995 996 /* XXX FIXME: Having to increment nsegs is really annoying */ 997 ++*nsegs; 998 CTR5(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d nsegs %d", 999 __func__, dmat, dmat->flags, error, *nsegs); 1000 return (error); 1001 } 1002 1003 /* 1004 * Like bus_dmamap_load(), but for uios. 1005 */ 1006 int 1007 bus_dmamap_load_uio(bus_dma_tag_t dmat, bus_dmamap_t map, struct uio *uio, 1008 bus_dmamap_callback2_t *callback, void *callback_arg, 1009 int flags) 1010 { 1011 vm_offset_t lastaddr = 0; 1012 #ifdef __CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1013 bus_dma_segment_t dm_segments[dmat->nsegments]; 1014 #else 1015 bus_dma_segment_t dm_segments[BUS_DMAMAP_NSEGS]; 1016 #endif 1017 int nsegs, i, error; 1018 bus_size_t resid; 1019 struct iovec *iov; 1020 struct pmap *pmap; 1021 1022 resid = uio->uio_resid; 1023 iov = uio->uio_iov; 1024 map->flags &= ~DMAMAP_TYPE_MASK; 1025 map->flags |= DMAMAP_UIO|DMAMAP_COHERENT; 1026 map->buffer = uio; 1027 map->len = 0; 1028 1029 if (uio->uio_segflg == UIO_USERSPACE) { 1030 KASSERT(uio->uio_td != NULL, 1031 ("bus_dmamap_load_uio: USERSPACE but no proc")); 1032 pmap = vmspace_pmap(uio->uio_td->td_proc->p_vmspace); 1033 } else 1034 pmap = kernel_pmap; 1035 1036 error = 0; 1037 nsegs = -1; 1038 for (i = 0; i < uio->uio_iovcnt && resid != 0 && !error; i++) { 1039 /* 1040 * Now at the first iovec to load. Load each iovec 1041 * until we have exhausted the residual count. 1042 */ 1043 bus_size_t minlen = 1044 resid < iov[i].iov_len ? resid : iov[i].iov_len; 1045 caddr_t addr = (caddr_t) iov[i].iov_base; 1046 1047 if (minlen > 0) { 1048 error = bus_dmamap_load_buffer(dmat, dm_segments, map, 1049 addr, minlen, pmap, flags, &lastaddr, &nsegs); 1050 1051 map->len += minlen; 1052 resid -= minlen; 1053 } 1054 } 1055 1056 if (error) { 1057 /* 1058 * force "no valid mappings" on error in callback. 1059 */ 1060 (*callback)(callback_arg, dm_segments, 0, 0, error); 1061 } else { 1062 (*callback)(callback_arg, dm_segments, nsegs+1, 1063 uio->uio_resid, error); 1064 } 1065 1066 CTR5(KTR_BUSDMA, "%s: tag %p tag flags 0x%x error %d nsegs %d", 1067 __func__, dmat, dmat->flags, error, nsegs + 1); 1068 return (error); 1069 } 1070 1071 /* 1072 * Release the mapping held by map. 1073 */ 1074 void 1075 _bus_dmamap_unload(bus_dma_tag_t dmat, bus_dmamap_t map) 1076 { 1077 struct bounce_page *bpage; 1078 1079 map->flags &= ~DMAMAP_TYPE_MASK; 1080 while ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) { 1081 STAILQ_REMOVE_HEAD(&map->bpages, links); 1082 free_bounce_page(dmat, bpage); 1083 } 1084 return; 1085 } 1086 1087 static void 1088 bus_dmamap_sync_buf(void *buf, int len, bus_dmasync_op_t op) 1089 { 1090 char _tmp_cl[arm_dcache_align], _tmp_clend[arm_dcache_align]; 1091 1092 if ((op & BUS_DMASYNC_PREWRITE) && !(op & BUS_DMASYNC_PREREAD)) { 1093 cpu_dcache_wb_range((vm_offset_t)buf, len); 1094 cpu_l2cache_wb_range((vm_offset_t)buf, len); 1095 } 1096 if (op & BUS_DMASYNC_PREREAD) { 1097 if (!(op & BUS_DMASYNC_PREWRITE) && 1098 ((((vm_offset_t)(buf) | len) & arm_dcache_align_mask) == 0)) { 1099 cpu_dcache_inv_range((vm_offset_t)buf, len); 1100 cpu_l2cache_inv_range((vm_offset_t)buf, len); 1101 } else { 1102 cpu_dcache_wbinv_range((vm_offset_t)buf, len); 1103 cpu_l2cache_wbinv_range((vm_offset_t)buf, len); 1104 } 1105 } 1106 if (op & BUS_DMASYNC_POSTREAD) { 1107 if ((vm_offset_t)buf & arm_dcache_align_mask) { 1108 memcpy(_tmp_cl, (void *)((vm_offset_t)buf & ~ 1109 arm_dcache_align_mask), 1110 (vm_offset_t)buf & arm_dcache_align_mask); 1111 } 1112 if (((vm_offset_t)buf + len) & arm_dcache_align_mask) { 1113 memcpy(_tmp_clend, (void *)((vm_offset_t)buf + len), 1114 arm_dcache_align - (((vm_offset_t)(buf) + len) & 1115 arm_dcache_align_mask)); 1116 } 1117 cpu_dcache_inv_range((vm_offset_t)buf, len); 1118 cpu_l2cache_inv_range((vm_offset_t)buf, len); 1119 1120 if ((vm_offset_t)buf & arm_dcache_align_mask) 1121 memcpy((void *)((vm_offset_t)buf & 1122 ~arm_dcache_align_mask), _tmp_cl, 1123 (vm_offset_t)buf & arm_dcache_align_mask); 1124 if (((vm_offset_t)buf + len) & arm_dcache_align_mask) 1125 memcpy((void *)((vm_offset_t)buf + len), _tmp_clend, 1126 arm_dcache_align - (((vm_offset_t)(buf) + len) & 1127 arm_dcache_align_mask)); 1128 } 1129 } 1130 1131 static void 1132 _bus_dmamap_sync_bp(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op) 1133 { 1134 struct bounce_page *bpage; 1135 1136 STAILQ_FOREACH(bpage, &map->bpages, links) { 1137 if (op & BUS_DMASYNC_PREWRITE) { 1138 bcopy((void *)bpage->datavaddr, 1139 (void *)(bpage->vaddr_nocache != 0 ? 1140 bpage->vaddr_nocache : bpage->vaddr), 1141 bpage->datacount); 1142 if (bpage->vaddr_nocache == 0) { 1143 cpu_dcache_wb_range(bpage->vaddr, 1144 bpage->datacount); 1145 cpu_l2cache_wb_range(bpage->vaddr, 1146 bpage->datacount); 1147 } 1148 } 1149 if (op & BUS_DMASYNC_POSTREAD) { 1150 if (bpage->vaddr_nocache == 0) { 1151 cpu_dcache_inv_range(bpage->vaddr, 1152 bpage->datacount); 1153 cpu_l2cache_inv_range(bpage->vaddr, 1154 bpage->datacount); 1155 } 1156 bcopy((void *)(bpage->vaddr_nocache != 0 ? 1157 bpage->vaddr_nocache : bpage->vaddr), 1158 (void *)bpage->datavaddr, bpage->datacount); 1159 } 1160 } 1161 } 1162 1163 static __inline int 1164 _bus_dma_buf_is_in_bp(bus_dmamap_t map, void *buf, int len) 1165 { 1166 struct bounce_page *bpage; 1167 1168 STAILQ_FOREACH(bpage, &map->bpages, links) { 1169 if ((vm_offset_t)buf >= bpage->datavaddr && 1170 (vm_offset_t)buf + len <= bpage->datavaddr + 1171 bpage->datacount) 1172 return (1); 1173 } 1174 return (0); 1175 1176 } 1177 1178 void 1179 _bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map, bus_dmasync_op_t op) 1180 { 1181 struct mbuf *m; 1182 struct uio *uio; 1183 int resid; 1184 struct iovec *iov; 1185 1186 if (op == BUS_DMASYNC_POSTWRITE) 1187 return; 1188 if (STAILQ_FIRST(&map->bpages)) 1189 _bus_dmamap_sync_bp(dmat, map, op); 1190 if (map->flags & DMAMAP_COHERENT) 1191 return; 1192 CTR3(KTR_BUSDMA, "%s: op %x flags %x", __func__, op, map->flags); 1193 switch(map->flags & DMAMAP_TYPE_MASK) { 1194 case DMAMAP_LINEAR: 1195 if (!(_bus_dma_buf_is_in_bp(map, map->buffer, map->len))) 1196 bus_dmamap_sync_buf(map->buffer, map->len, op); 1197 break; 1198 case DMAMAP_MBUF: 1199 m = map->buffer; 1200 while (m) { 1201 if (m->m_len > 0 && 1202 !(_bus_dma_buf_is_in_bp(map, m->m_data, m->m_len))) 1203 bus_dmamap_sync_buf(m->m_data, m->m_len, op); 1204 m = m->m_next; 1205 } 1206 break; 1207 case DMAMAP_UIO: 1208 uio = map->buffer; 1209 iov = uio->uio_iov; 1210 resid = uio->uio_resid; 1211 for (int i = 0; i < uio->uio_iovcnt && resid != 0; i++) { 1212 bus_size_t minlen = resid < iov[i].iov_len ? resid : 1213 iov[i].iov_len; 1214 if (minlen > 0) { 1215 if (!_bus_dma_buf_is_in_bp(map, iov[i].iov_base, 1216 minlen)) 1217 bus_dmamap_sync_buf(iov[i].iov_base, 1218 minlen, op); 1219 resid -= minlen; 1220 } 1221 } 1222 break; 1223 default: 1224 break; 1225 } 1226 cpu_drain_writebuf(); 1227 } 1228 1229 static void 1230 init_bounce_pages(void *dummy __unused) 1231 { 1232 1233 total_bpages = 0; 1234 STAILQ_INIT(&bounce_zone_list); 1235 STAILQ_INIT(&bounce_map_waitinglist); 1236 STAILQ_INIT(&bounce_map_callbacklist); 1237 mtx_init(&bounce_lock, "bounce pages lock", NULL, MTX_DEF); 1238 } 1239 SYSINIT(bpages, SI_SUB_LOCK, SI_ORDER_ANY, init_bounce_pages, NULL); 1240 1241 static struct sysctl_ctx_list * 1242 busdma_sysctl_tree(struct bounce_zone *bz) 1243 { 1244 return (&bz->sysctl_tree); 1245 } 1246 1247 static struct sysctl_oid * 1248 busdma_sysctl_tree_top(struct bounce_zone *bz) 1249 { 1250 return (bz->sysctl_tree_top); 1251 } 1252 1253 static int 1254 alloc_bounce_zone(bus_dma_tag_t dmat) 1255 { 1256 struct bounce_zone *bz; 1257 1258 /* Check to see if we already have a suitable zone */ 1259 STAILQ_FOREACH(bz, &bounce_zone_list, links) { 1260 if ((dmat->alignment <= bz->alignment) 1261 && (dmat->lowaddr >= bz->lowaddr)) { 1262 dmat->bounce_zone = bz; 1263 return (0); 1264 } 1265 } 1266 1267 if ((bz = (struct bounce_zone *)malloc(sizeof(*bz), M_DEVBUF, 1268 M_NOWAIT | M_ZERO)) == NULL) 1269 return (ENOMEM); 1270 1271 STAILQ_INIT(&bz->bounce_page_list); 1272 bz->free_bpages = 0; 1273 bz->reserved_bpages = 0; 1274 bz->active_bpages = 0; 1275 bz->lowaddr = dmat->lowaddr; 1276 bz->alignment = MAX(dmat->alignment, PAGE_SIZE); 1277 snprintf(bz->zoneid, 8, "zone%d", busdma_zonecount); 1278 busdma_zonecount++; 1279 snprintf(bz->lowaddrid, 18, "%#jx", (uintmax_t)bz->lowaddr); 1280 STAILQ_INSERT_TAIL(&bounce_zone_list, bz, links); 1281 dmat->bounce_zone = bz; 1282 1283 sysctl_ctx_init(&bz->sysctl_tree); 1284 bz->sysctl_tree_top = SYSCTL_ADD_NODE(&bz->sysctl_tree, 1285 SYSCTL_STATIC_CHILDREN(_hw_busdma), OID_AUTO, bz->zoneid, 1286 CTLFLAG_RD, 0, ""); 1287 if (bz->sysctl_tree_top == NULL) { 1288 sysctl_ctx_free(&bz->sysctl_tree); 1289 return (0); /* XXX error code? */ 1290 } 1291 1292 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1293 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1294 "total_bpages", CTLFLAG_RD, &bz->total_bpages, 0, 1295 "Total bounce pages"); 1296 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1297 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1298 "free_bpages", CTLFLAG_RD, &bz->free_bpages, 0, 1299 "Free bounce pages"); 1300 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1301 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1302 "reserved_bpages", CTLFLAG_RD, &bz->reserved_bpages, 0, 1303 "Reserved bounce pages"); 1304 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1305 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1306 "active_bpages", CTLFLAG_RD, &bz->active_bpages, 0, 1307 "Active bounce pages"); 1308 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1309 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1310 "total_bounced", CTLFLAG_RD, &bz->total_bounced, 0, 1311 "Total bounce requests"); 1312 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1313 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1314 "total_deferred", CTLFLAG_RD, &bz->total_deferred, 0, 1315 "Total bounce requests that were deferred"); 1316 SYSCTL_ADD_STRING(busdma_sysctl_tree(bz), 1317 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1318 "lowaddr", CTLFLAG_RD, bz->lowaddrid, 0, ""); 1319 SYSCTL_ADD_INT(busdma_sysctl_tree(bz), 1320 SYSCTL_CHILDREN(busdma_sysctl_tree_top(bz)), OID_AUTO, 1321 "alignment", CTLFLAG_RD, &bz->alignment, 0, ""); 1322 1323 return (0); 1324 } 1325 1326 static int 1327 alloc_bounce_pages(bus_dma_tag_t dmat, u_int numpages) 1328 { 1329 struct bounce_zone *bz; 1330 int count; 1331 1332 bz = dmat->bounce_zone; 1333 count = 0; 1334 while (numpages > 0) { 1335 struct bounce_page *bpage; 1336 1337 bpage = (struct bounce_page *)malloc(sizeof(*bpage), M_DEVBUF, 1338 M_NOWAIT | M_ZERO); 1339 1340 if (bpage == NULL) 1341 break; 1342 bpage->vaddr = (vm_offset_t)contigmalloc(PAGE_SIZE, M_DEVBUF, 1343 M_NOWAIT, 0ul, 1344 bz->lowaddr, 1345 PAGE_SIZE, 1346 0); 1347 if (bpage->vaddr == 0) { 1348 free(bpage, M_DEVBUF); 1349 break; 1350 } 1351 bpage->busaddr = pmap_kextract(bpage->vaddr); 1352 bpage->vaddr_nocache = (vm_offset_t)arm_remap_nocache( 1353 (void *)bpage->vaddr, PAGE_SIZE); 1354 mtx_lock(&bounce_lock); 1355 STAILQ_INSERT_TAIL(&bz->bounce_page_list, bpage, links); 1356 total_bpages++; 1357 bz->total_bpages++; 1358 bz->free_bpages++; 1359 mtx_unlock(&bounce_lock); 1360 count++; 1361 numpages--; 1362 } 1363 return (count); 1364 } 1365 1366 static int 1367 reserve_bounce_pages(bus_dma_tag_t dmat, bus_dmamap_t map, int commit) 1368 { 1369 struct bounce_zone *bz; 1370 int pages; 1371 1372 mtx_assert(&bounce_lock, MA_OWNED); 1373 bz = dmat->bounce_zone; 1374 pages = MIN(bz->free_bpages, map->pagesneeded - map->pagesreserved); 1375 if (commit == 0 && map->pagesneeded > (map->pagesreserved + pages)) 1376 return (map->pagesneeded - (map->pagesreserved + pages)); 1377 bz->free_bpages -= pages; 1378 bz->reserved_bpages += pages; 1379 map->pagesreserved += pages; 1380 pages = map->pagesneeded - map->pagesreserved; 1381 1382 return (pages); 1383 } 1384 1385 static bus_addr_t 1386 add_bounce_page(bus_dma_tag_t dmat, bus_dmamap_t map, vm_offset_t vaddr, 1387 bus_size_t size) 1388 { 1389 struct bounce_zone *bz; 1390 struct bounce_page *bpage; 1391 1392 KASSERT(dmat->bounce_zone != NULL, ("no bounce zone in dma tag")); 1393 KASSERT(map != NULL, ("add_bounce_page: bad map %p", map)); 1394 1395 bz = dmat->bounce_zone; 1396 if (map->pagesneeded == 0) 1397 panic("add_bounce_page: map doesn't need any pages"); 1398 map->pagesneeded--; 1399 1400 if (map->pagesreserved == 0) 1401 panic("add_bounce_page: map doesn't need any pages"); 1402 map->pagesreserved--; 1403 1404 mtx_lock(&bounce_lock); 1405 bpage = STAILQ_FIRST(&bz->bounce_page_list); 1406 if (bpage == NULL) 1407 panic("add_bounce_page: free page list is empty"); 1408 1409 STAILQ_REMOVE_HEAD(&bz->bounce_page_list, links); 1410 bz->reserved_bpages--; 1411 bz->active_bpages++; 1412 mtx_unlock(&bounce_lock); 1413 1414 bpage->datavaddr = vaddr; 1415 bpage->datacount = size; 1416 STAILQ_INSERT_TAIL(&(map->bpages), bpage, links); 1417 return (bpage->busaddr); 1418 } 1419 1420 static void 1421 free_bounce_page(bus_dma_tag_t dmat, struct bounce_page *bpage) 1422 { 1423 struct bus_dmamap *map; 1424 struct bounce_zone *bz; 1425 1426 bz = dmat->bounce_zone; 1427 bpage->datavaddr = 0; 1428 bpage->datacount = 0; 1429 1430 mtx_lock(&bounce_lock); 1431 STAILQ_INSERT_HEAD(&bz->bounce_page_list, bpage, links); 1432 bz->free_bpages++; 1433 bz->active_bpages--; 1434 if ((map = STAILQ_FIRST(&bounce_map_waitinglist)) != NULL) { 1435 if (reserve_bounce_pages(map->dmat, map, 1) == 0) { 1436 STAILQ_REMOVE_HEAD(&bounce_map_waitinglist, links); 1437 STAILQ_INSERT_TAIL(&bounce_map_callbacklist, 1438 map, links); 1439 busdma_swi_pending = 1; 1440 bz->total_deferred++; 1441 swi_sched(vm_ih, 0); 1442 } 1443 } 1444 mtx_unlock(&bounce_lock); 1445 } 1446 1447 void 1448 busdma_swi(void) 1449 { 1450 bus_dma_tag_t dmat; 1451 struct bus_dmamap *map; 1452 1453 mtx_lock(&bounce_lock); 1454 while ((map = STAILQ_FIRST(&bounce_map_callbacklist)) != NULL) { 1455 STAILQ_REMOVE_HEAD(&bounce_map_callbacklist, links); 1456 mtx_unlock(&bounce_lock); 1457 dmat = map->dmat; 1458 (dmat->lockfunc)(dmat->lockfuncarg, BUS_DMA_LOCK); 1459 bus_dmamap_load(map->dmat, map, map->buffer, map->len, 1460 map->callback, map->callback_arg, /*flags*/0); 1461 (dmat->lockfunc)(dmat->lockfuncarg, BUS_DMA_UNLOCK); 1462 mtx_lock(&bounce_lock); 1463 } 1464 mtx_unlock(&bounce_lock); 1465 }
Cache object: 5b689ce0d4ab656127895e88c3080aeb
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