The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/arm/cpufunc_asm.S

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    1 /*      $NetBSD: cpufunc_asm.S,v 1.12 2003/09/06 09:14:52 rearnsha Exp $        */
    2 
    3 /*-
    4  * Copyright (c) 1997,1998 Mark Brinicombe.
    5  * Copyright (c) 1997 Causality Limited
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. All advertising materials mentioning features or use of this software
   17  *    must display the following acknowledgement:
   18  *      This product includes software developed by Causality Limited.
   19  * 4. The name of Causality Limited may not be used to endorse or promote
   20  *    products derived from this software without specific prior written
   21  *    permission.
   22  *
   23  * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
   24  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
   25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
   26  * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
   27  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
   29  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   33  * SUCH DAMAGE.
   34  *
   35  * RiscBSD kernel project
   36  *
   37  * cpufunc.S
   38  *
   39  * Assembly functions for CPU / MMU / TLB specific operations
   40  *
   41  * Created      : 30/01/97
   42  *
   43  */
   44 
   45 #include <machine/asm.h>
   46 __FBSDID("$FreeBSD: releng/10.0/sys/arm/arm/cpufunc_asm.S 248361 2013-03-16 02:48:49Z andrew $");
   47 
   48         .text
   49         .align  0
   50 
   51 ENTRY(cpufunc_nullop)
   52         RET
   53 END(cpufunc_nullop)
   54 
   55 /*
   56  * Generic functions to read the internal coprocessor registers
   57  *
   58  * Currently these registers are :
   59  *  c0 - CPU ID
   60  *  c5 - Fault status
   61  *  c6 - Fault address
   62  *
   63  */
   64 
   65 ENTRY(cpufunc_id)
   66         mrc     p15, 0, r0, c0, c0, 0
   67         RET
   68 END(cpufunc_id)
   69 
   70 ENTRY(cpufunc_cpuid)
   71         mrc     p15, 0, r0, c0, c0, 0
   72         RET
   73 END(cpufunc_cpuid)
   74 
   75 ENTRY(cpu_get_control)
   76         mrc     p15, 0, r0, c1, c0, 0
   77         RET
   78 END(cpu_get_control)
   79 
   80 ENTRY(cpu_read_cache_config)
   81         mrc     p15, 0, r0, c0, c0, 1
   82         RET
   83 END(cpu_read_cache_config)
   84 
   85 ENTRY(cpufunc_faultstatus)
   86         mrc     p15, 0, r0, c5, c0, 0
   87         RET
   88 END(cpufunc_faultstatus)
   89 
   90 ENTRY(cpufunc_faultaddress)
   91         mrc     p15, 0, r0, c6, c0, 0
   92         RET
   93 END(cpufunc_faultaddress)
   94 
   95 /*
   96  * Generic functions to write the internal coprocessor registers
   97  *
   98  *
   99  * Currently these registers are
  100  *  c1 - CPU Control
  101  *  c3 - Domain Access Control
  102  *
  103  * All other registers are CPU architecture specific
  104  */
  105 
  106 #if 0 /* See below. */
  107 ENTRY(cpufunc_control)
  108         mcr     p15, 0, r0, c1, c0, 0
  109         RET
  110 END(cpufunc_control)
  111 #endif
  112 
  113 ENTRY(cpufunc_domains)
  114         mcr     p15, 0, r0, c3, c0, 0
  115         RET
  116 END(cpufunc_domains)
  117 
  118 /*
  119  * Generic functions to read/modify/write the internal coprocessor registers
  120  *
  121  *
  122  * Currently these registers are
  123  *  c1 - CPU Control
  124  *
  125  * All other registers are CPU architecture specific
  126  */
  127 
  128 ENTRY(cpufunc_control)
  129         mrc     p15, 0, r3, c1, c0, 0   /* Read the control register */
  130         bic     r2, r3, r0              /* Clear bits */
  131         eor     r2, r2, r1              /* XOR bits */
  132 
  133 
  134         teq     r2, r3                  /* Only write if there is a change */
  135         mcrne   p15, 0, r2, c1, c0, 0   /* Write new control register */
  136         mov     r0, r3                  /* Return old value */
  137 
  138         RET
  139 .Lglou:
  140         .asciz "plop %p\n"
  141         .align 0
  142 END(cpufunc_control)
  143 
  144 /*
  145  * other potentially useful software functions are:
  146  *  clean D cache entry and flush I cache entry
  147  *   for the moment use cache_purgeID_E
  148  */
  149 
  150 /* Random odd functions */
  151 
  152 /*
  153  * Function to get the offset of a stored program counter from the
  154  * instruction doing the store.  This offset is defined to be the same
  155  * for all STRs and STMs on a given implementation.  Code based on
  156  * section 2.4.3 of the ARM ARM (2nd Ed.), with modifications to work
  157  * in 26-bit modes as well.
  158  */
  159 ENTRY(get_pc_str_offset)
  160         mov     ip, sp
  161         stmfd   sp!, {fp, ip, lr, pc}
  162         sub     fp, ip, #4
  163         sub     sp, sp, #4
  164         mov     r1, pc          /* R1 = addr of following STR */
  165         mov     r0, r0
  166         str     pc, [sp]        /* [SP] = . + offset */
  167         ldr     r0, [sp]
  168         sub     r0, r0, r1
  169         ldmdb   fp, {fp, sp, pc}
  170 END(get_pc_str_offset)
  171 
  172 /* Allocate and lock a cacheline for the specified address. */
  173 
  174 #define CPWAIT_BRANCH                   \
  175         sub     pc, pc, #4
  176 #define CPWAIT() \
  177         mrc     p15, 0, r2, c2, c0, 0;  \
  178         mov     r2, r2;                 \
  179         CPWAIT_BRANCH
  180 
  181 ENTRY(arm_lock_cache_line)
  182         mcr     p15, 0, r0, c7, c10, 4 /* Drain write buffer */
  183         mov     r1, #1
  184         mcr     p15, 0, r1, c9, c2, 0 /* Enable data cache lock mode */
  185         CPWAIT()
  186         mcr     p15, 0, r0, c7, c2, 5 /* Allocate the cache line */
  187         mcr     p15, 0, r0, c7, c10, 4 /* Drain write buffer */
  188         mov     r1, #0
  189         str     r1, [r0]
  190         mcr     p15, 0, r0, c7, c10, 4 /* Drain write buffer */
  191         mcr     p15, 0, r1, c9, c2, 0 /* Disable data cache lock mode */
  192         CPWAIT()
  193         RET
  194 END(arm_lock_cache_line)
  195 

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