1 /* $NetBSD: cpufunc_asm_arm11.S,v 1.2 2005/12/11 12:16:41 christos Exp $ */
2
3 /*
4 * Copyright (c) 2002, 2005 ARM Limited
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the company may not be used to endorse or promote
16 * products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * ARM11 assembly functions for CPU / MMU / TLB specific operations
32 *
33 * XXX We make no attempt at present to take advantage of the v6 memroy
34 * architecture or physically tagged cache.
35 */
36
37 #include <machine/asm.h>
38 __FBSDID("$FreeBSD: releng/10.0/sys/arm/arm/cpufunc_asm_arm11.S 248361 2013-03-16 02:48:49Z andrew $");
39
40 /*
41 * Functions to set the MMU Translation Table Base register
42 *
43 * We need to clean and flush the cache as it uses virtual
44 * addresses that are about to change.
45 */
46 ENTRY(arm11_setttb)
47 #ifdef PMAP_CACHE_VIVT
48 stmfd sp!, {r0, lr}
49 bl _C_LABEL(armv5_idcache_wbinv_all)
50 ldmfd sp!, {r0, lr}
51 #endif
52
53 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
54
55 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
56 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
57 RET
58 END(arm11_setttb)
59
60 /*
61 * TLB functions
62 */
63 ENTRY(arm11_tlb_flushID_SE)
64 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
65 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
66 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
67 RET
68 END(arm11_tlb_flushID_SE)
69
70 ENTRY(arm11_tlb_flushI_SE)
71 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
72 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
73 RET
74 END(arm11_tlb_flushI_SE)
75
76 /*
77 * Context switch.
78 *
79 * These is the CPU-specific parts of the context switcher cpu_switch()
80 * These functions actually perform the TTB reload.
81 *
82 * NOTE: Special calling convention
83 * r1, r4-r13 must be preserved
84 */
85 ENTRY(arm11_context_switch)
86 /*
87 * We can assume that the caches will only contain kernel addresses
88 * at this point. So no need to flush them again.
89 */
90 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
91 mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
92 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
93
94 /* Paranoia -- make sure the pipeline is empty. */
95 nop
96 nop
97 nop
98 RET
99 END(arm11_context_switch)
100
101 /*
102 * TLB functions
103 */
104 ENTRY(arm11_tlb_flushID)
105 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
106 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
107 mov pc, lr
108 END(arm11_tlb_flushID)
109
110 ENTRY(arm11_tlb_flushI)
111 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
112 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
113 mov pc, lr
114 END(arm11_tlb_flushI)
115
116 ENTRY(arm11_tlb_flushD)
117 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
118 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
119 mov pc, lr
120 END(arm11_tlb_flushD)
121
122 ENTRY(arm11_tlb_flushD_SE)
123 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
124 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
125 mov pc, lr
126 END(arm11_tlb_flushD_SE)
127
128 /*
129 * Other functions
130 */
131 ENTRY(arm11_drain_writebuf)
132 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
133 mov pc, lr
134 END(arm11_drain_writebuf)
135
136 ENTRY_NP(arm11_sleep)
137 mov r0, #0
138 mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */
139 RET
140 END(arm11_sleep)
141
Cache object: 773955b584711e6e0d161de2ac63d308
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