1 /* $NetBSD: cpufunc_asm_arm11.S,v 1.2 2005/12/11 12:16:41 christos Exp $ */
2
3 /*
4 * Copyright (c) 2002, 2005 ARM Limited
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the company may not be used to endorse or promote
16 * products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * ARM11 assembly functions for CPU / MMU / TLB specific operations
32 *
33 * XXX We make no attempt at present to take advantage of the v6 memroy
34 * architecture or physically tagged cache.
35 */
36
37 #include <machine/asm.h>
38 __FBSDID("$FreeBSD: releng/9.0/sys/arm/arm/cpufunc_asm_arm11.S 172738 2007-10-18 05:33:06Z imp $");
39
40 /*
41 * Functions to set the MMU Translation Table Base register
42 *
43 * We need to clean and flush the cache as it uses virtual
44 * addresses that are about to change.
45 */
46 ENTRY(arm11_setttb)
47 stmfd sp!, {r0, lr}
48 bl _C_LABEL(armv5_idcache_wbinv_all)
49 ldmfd sp!, {r0, lr}
50
51 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
52
53 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
54 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
55 RET
56
57 /*
58 * TLB functions
59 */
60 ENTRY(arm11_tlb_flushID_SE)
61 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
62 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
63 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
64 RET
65
66 ENTRY(arm11_tlb_flushI_SE)
67 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
68 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
69 RET
70
71
72 /*
73 * Context switch.
74 *
75 * These is the CPU-specific parts of the context switcher cpu_switch()
76 * These functions actually perform the TTB reload.
77 *
78 * NOTE: Special calling convention
79 * r1, r4-r13 must be preserved
80 */
81 ENTRY(arm11_context_switch)
82 /*
83 * We can assume that the caches will only contain kernel addresses
84 * at this point. So no need to flush them again.
85 */
86 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
87 mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
88 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */
89
90 /* Paranoia -- make sure the pipeline is empty. */
91 nop
92 nop
93 nop
94 RET
95
96 /*
97 * TLB functions
98 */
99 ENTRY(arm11_tlb_flushID)
100 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
101 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
102 mov pc, lr
103
104 ENTRY(arm11_tlb_flushI)
105 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
106 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
107 mov pc, lr
108
109 ENTRY(arm11_tlb_flushD)
110 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
111 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
112 mov pc, lr
113
114 ENTRY(arm11_tlb_flushD_SE)
115 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
116 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
117 mov pc, lr
118
119 /*
120 * Other functions
121 */
122 ENTRY(arm11_drain_writebuf)
123 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
124 mov pc, lr
Cache object: 99b6b1b6057449f6c96e48b6f407d5cf
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