1 /* $NetBSD: cpufunc_asm_arm11x6.S,v 1.1 2012/07/21 12:19:15 skrll Exp $ */
2
3 /*
4 * Copyright (c) 2007 Microsoft
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Microsoft
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 /*-
33 * Copyright (c) 2012 The NetBSD Foundation, Inc.
34 * All rights reserved.
35 *
36 * This code is derived from software contributed to The NetBSD Foundation
37 * by Eben Upton
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 * 1. Redistributions of source code must retain the above copyright
43 * notice, this list of conditions and the following disclaimer.
44 * 2. Redistributions in binary form must reproduce the above copyright
45 * notice, this list of conditions and the following disclaimer in the
46 * documentation and/or other materials provided with the distribution.
47 *
48 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
58 * POSSIBILITY OF SUCH DAMAGE.
59 */
60
61
62 #include <machine/asm.h>
63 __FBSDID("$FreeBSD: releng/10.0/sys/arm/arm/cpufunc_asm_arm11x6.S 248361 2013-03-16 02:48:49Z andrew $");
64
65 .cpu arm1136js
66
67 #if 0
68 #define Invalidate_I_cache(Rtmp1, Rtmp2) \
69 mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */
70 #else
71 /*
72 * Workaround for
73 *
74 * Erratum 411920 in ARM1136 (fixed in r1p4)
75 * Erratum 415045 in ARM1176 (fixed in r0p5?)
76 *
77 * - value of arg 'reg' Should Be Zero
78 */
79 #define Invalidate_I_cache(Rtmp1, Rtmp2) \
80 mov Rtmp1, #0; /* SBZ */ \
81 mrs Rtmp2, cpsr; \
82 cpsid ifa; \
83 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
84 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
85 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
86 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \
87 msr cpsr_cx, Rtmp2; \
88 nop; \
89 nop; \
90 nop; \
91 nop; \
92 nop; \
93 nop; \
94 nop; \
95 nop; \
96 nop; \
97 nop; \
98 nop;
99 #endif
100
101 #if 1
102 #define Flush_D_cache(reg) \
103 mov reg, #0; /* SBZ */ \
104 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
105 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
106 #else
107 #define Flush_D_cache(reg) \
108 1: mov reg, #0; /* SBZ */ \
109 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \
110 mrc p15, 0, reg, C7, C10, 6;/* Read Cache Dirty Status Register */ \
111 ands reg, reg, #01; /* Check if it is clean */ \
112 bne 1b; /* loop if not */ \
113 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */
114 #endif
115
116 ENTRY(arm11x6_setttb)
117 #ifdef PMAP_CACHE_VIVT
118 Flush_D_cache(r1)
119 Invalidate_I_cache(r1, r2)
120 #else
121 mov r1, #0
122 #endif
123 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
124 mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLBs */
125 mcr p15, 0, r1, c7, c10, 4 /* drain write buffer */
126 RET
127 END(arm11x6_setttb)
128
129 ENTRY_NP(arm11x6_idcache_wbinv_all)
130 Flush_D_cache(r0)
131 Invalidate_I_cache(r0, r1)
132 RET
133 END(arm11x6_idcache_wbinv_all)
134
135 ENTRY_NP(arm11x6_dcache_wbinv_all)
136 Flush_D_cache(r0)
137 RET
138 END(arm11x6_dcache_wbinv_all)
139
140 ENTRY_NP(arm11x6_icache_sync_all)
141 Flush_D_cache(r0)
142 Invalidate_I_cache(r0, r1)
143 RET
144 END(arm11x6_icache_sync_all)
145
146 ENTRY_NP(arm11x6_flush_prefetchbuf)
147 mcr p15, 0, r0, c7, c5, 4 /* Flush Prefetch Buffer */
148 RET
149 END(arm11x6_flush_prefetchbuf)
150
151 ENTRY_NP(arm11x6_icache_sync_range)
152 add r1, r1, r0
153 sub r1, r1, #1
154 /* Erratum ARM1136 371025, workaround #2 */
155 /* Erratum ARM1176 371367 */
156 mrs r2, cpsr /* save the CPSR */
157 cpsid ifa /* disable interrupts (irq,fiq,abort) */
158 mov r3, #0
159 mcr p15, 0, r3, c13, c0, 0 /* write FCSE (uTLB invalidate) */
160 mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */
161 add r3, pc, #0x24
162 mcr p15, 0, r3, c7, c13, 1 /* prefetch I-cache line */
163 mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */
164 msr cpsr_cx, r2 /* local_irq_restore */
165 nop
166 nop
167 nop
168 nop
169 nop
170 nop
171 nop
172
173 mcrr p15, 0, r1, r0, c12 /* clean and invalidate D cache range */ /* XXXNH */
174 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
175 RET
176 END(arm11x6_icache_sync_range)
177
178 ENTRY_NP(arm11x6_idcache_wbinv_range)
179 add r1, r1, r0
180 sub r1, r1, #1
181 /* Erratum ARM1136 371025, workaround #2 */
182 /* Erratum ARM1176 371367 */
183 mrs r2, cpsr /* save the CPSR */
184 cpsid ifa /* disable interrupts (irq,fiq,abort) */
185 mov r3, #0
186 mcr p15, 0, r3, c13, c0, 0 /* write FCSE (uTLB invalidate) */
187 mcr p15, 0, r3, c7, c5, 4 /* flush prefetch buffer */
188 add r3, pc, #0x24
189 mcr p15, 0, r3, c7, c13, 1 /* prefetch I-cache line */
190 mcrr p15, 0, r1, r0, c5 /* invalidate I-cache range */
191 msr cpsr_cx, r2 /* local_irq_restore */
192 nop
193 nop
194 nop
195 nop
196 nop
197 nop
198 nop
199
200 mcrr p15, 0, r1, r0, c14 /* clean and invalidate D cache range */
201 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
202 RET
203 END(arm11x6_idcache_wbinv_range)
204
205 /*
206 * Preload the cache before issuing the WFI by conditionally disabling the
207 * mcr intstructions the first time around the loop. Ensure the function is
208 * cacheline aligned.
209 */
210 .arch armv6
211 .p2align 5
212
213 ENTRY_NP(arm11x6_sleep)
214 mov r0, #0
215 mov r1, #2
216 1:
217 subs r1, #1
218 nop
219 mcreq p15, 0, r0, c7, c10, 4 /* data sync barrier */
220 mcreq p15, 0, r0, c7, c0, 4 /* wait for interrupt */
221 nop
222 nop
223 nop
224 bne 1b
225 RET
226 END(arm11x6_sleep)
227
Cache object: 60321dccada09040a582518be39c1e20
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