1 /* $NetBSD: cpufunc_asm_armv5.S,v 1.3 2007/01/06 00:50:54 christos Exp $ */
2
3 /*
4 * Copyright (c) 2002, 2005 ARM Limited
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the company may not be used to endorse or promote
16 * products derived from this software without specific prior written
17 * permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * ARMv5 assembly functions for manipulating caches.
32 * These routines can be used by any core that supports the set/index
33 * operations.
34 */
35
36 #include <machine/asm.h>
37 __FBSDID("$FreeBSD$");
38
39 /*
40 * Functions to set the MMU Translation Table Base register
41 *
42 * We need to clean and flush the cache as it uses virtual
43 * addresses that are about to change.
44 */
45 ENTRY(armv5_setttb)
46 stmfd sp!, {r0, lr}
47 bl _C_LABEL(armv5_idcache_wbinv_all)
48 ldmfd sp!, {r0, lr}
49
50 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
51
52 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
53 RET
54
55 /*
56 * Cache operations. For the entire cache we use the set/index
57 * operations.
58 */
59 s_max .req r0
60 i_max .req r1
61 s_inc .req r2
62 i_inc .req r3
63
64 ENTRY_NP(armv5_icache_sync_range)
65 ldr ip, .Larmv5_line_size
66 cmp r1, #0x4000
67 bcs .Larmv5_icache_sync_all
68 ldr ip, [ip]
69 sub r1, r1, #1 /* Don't overrun */
70 sub r3, ip, #1
71 and r2, r0, r3
72 add r1, r1, r2
73 bic r0, r0, r3
74 1:
75 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
76 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
77 add r0, r0, ip
78 subs r1, r1, ip
79 bpl 1b
80 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
81 RET
82
83 ENTRY_NP(armv5_icache_sync_all)
84 .Larmv5_icache_sync_all:
85 /*
86 * We assume that the code here can never be out of sync with the
87 * dcache, so that we can safely flush the Icache and fall through
88 * into the Dcache cleaning code.
89 */
90 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
91 /* Fall through to clean Dcache. */
92
93 .Larmv5_dcache_wb:
94 ldr ip, .Larmv5_cache_data
95 ldmia ip, {s_max, i_max, s_inc, i_inc}
96 1:
97 orr ip, s_max, i_max
98 2:
99 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
100 sub ip, ip, i_inc
101 tst ip, i_max /* Index 0 is last one */
102 bne 2b /* Next index */
103 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
104 subs s_max, s_max, s_inc
105 bpl 1b /* Next set */
106 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
107 RET
108
109 .Larmv5_line_size:
110 .word _C_LABEL(arm_pdcache_line_size)
111
112 ENTRY(armv5_dcache_wb_range)
113 ldr ip, .Larmv5_line_size
114 cmp r1, #0x4000
115 bcs .Larmv5_dcache_wb
116 ldr ip, [ip]
117 sub r1, r1, #1 /* Don't overrun */
118 sub r3, ip, #1
119 and r2, r0, r3
120 add r1, r1, r2
121 bic r0, r0, r3
122 1:
123 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
124 add r0, r0, ip
125 subs r1, r1, ip
126 bpl 1b
127 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
128 RET
129
130 ENTRY(armv5_dcache_wbinv_range)
131 ldr ip, .Larmv5_line_size
132 cmp r1, #0x4000
133 bcs .Larmv5_dcache_wbinv_all
134 ldr ip, [ip]
135 sub r1, r1, #1 /* Don't overrun */
136 sub r3, ip, #1
137 and r2, r0, r3
138 add r1, r1, r2
139 bic r0, r0, r3
140 1:
141 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
142 add r0, r0, ip
143 subs r1, r1, ip
144 bpl 1b
145 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
146 RET
147
148 /*
149 * Note, we must not invalidate everything. If the range is too big we
150 * must use wb-inv of the entire cache.
151 */
152 ENTRY(armv5_dcache_inv_range)
153 ldr ip, .Larmv5_line_size
154 cmp r1, #0x4000
155 bcs .Larmv5_dcache_wbinv_all
156 ldr ip, [ip]
157 sub r1, r1, #1 /* Don't overrun */
158 sub r3, ip, #1
159 and r2, r0, r3
160 add r1, r1, r2
161 bic r0, r0, r3
162 1:
163 mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
164 add r0, r0, ip
165 subs r1, r1, ip
166 bpl 1b
167 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
168 RET
169
170 ENTRY(armv5_idcache_wbinv_range)
171 ldr ip, .Larmv5_line_size
172 cmp r1, #0x4000
173 bcs .Larmv5_idcache_wbinv_all
174 ldr ip, [ip]
175 sub r1, r1, #1 /* Don't overrun */
176 sub r3, ip, #1
177 and r2, r0, r3
178 add r1, r1, r2
179 bic r0, r0, r3
180 1:
181 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
182 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
183 add r0, r0, ip
184 subs r1, r1, ip
185 bpl 1b
186 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
187 RET
188
189 ENTRY_NP(armv5_idcache_wbinv_all)
190 .Larmv5_idcache_wbinv_all:
191 /*
192 * We assume that the code here can never be out of sync with the
193 * dcache, so that we can safely flush the Icache and fall through
194 * into the Dcache purging code.
195 */
196 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
197 /* Fall through to purge Dcache. */
198
199 ENTRY(armv5_dcache_wbinv_all)
200 .Larmv5_dcache_wbinv_all:
201 ldr ip, .Larmv5_cache_data
202 ldmia ip, {s_max, i_max, s_inc, i_inc}
203 1:
204 orr ip, s_max, i_max
205 2:
206 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
207 sub ip, ip, i_inc
208 tst ip, i_max /* Index 0 is last one */
209 bne 2b /* Next index */
210 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
211 subs s_max, s_max, s_inc
212 bpl 1b /* Next set */
213 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
214 RET
215
216 .Larmv5_cache_data:
217 .word _C_LABEL(armv5_dcache_sets_max)
218
219 .bss
220
221 /* XXX The following macros should probably be moved to asm.h */
222 #define _DATA_OBJECT(x) .globl x; .type x,_ASM_TYPE_OBJECT; x:
223 #define C_OBJECT(x) _DATA_OBJECT(_C_LABEL(x))
224
225 /*
226 * Parameters for the cache cleaning code. Note that the order of these
227 * four variables is assumed in the code above. Hence the reason for
228 * declaring them in the assembler file.
229 */
230 .align 0
231 C_OBJECT(armv5_dcache_sets_max)
232 .space 4
233 C_OBJECT(armv5_dcache_index_max)
234 .space 4
235 C_OBJECT(armv5_dcache_sets_inc)
236 .space 4
237 C_OBJECT(armv5_dcache_index_inc)
238 .space 4
Cache object: b910d65a3f5902f163e5c2ca9c10ad38
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