1 /*-
2 * Copyright (C) 2011 MARVELL INTERNATIONAL LTD.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 #include <machine/asm.h>
33 __FBSDID("$FreeBSD: releng/10.0/sys/arm/arm/cpufunc_asm_pj4b.S 250293 2013-05-06 14:12:36Z gber $");
34
35 #include <machine/param.h>
36
37 .Lpj4b_cache_line_size:
38 .word _C_LABEL(arm_pdcache_line_size)
39
40 .Lpj4b_sf_ctrl_reg:
41 .word 0xf1021820
42
43
44 ENTRY(pj4b_setttb)
45 /* Cache synchronization is not required as this core has PIPT caches */
46 mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */
47 #ifdef SMP
48 orr r0, r0, #2 /* Set TTB shared memory flag */
49 #endif
50 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
51 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
52 RET
53 END(pj4b_setttb)
54
55 ENTRY_NP(armv6_icache_sync_all)
56 /*
57 * We assume that the code here can never be out of sync with the
58 * dcache, so that we can safely flush the Icache and fall through
59 * into the Dcache cleaning code.
60 */
61 mov r0, #0
62 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
63 mcr p15, 0, r0, c7, c10, 0 /* Clean (don't invalidate) DCache */
64 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
65 RET
66 END(armv6_icache_sync_all)
67
68 ENTRY(pj4b_icache_sync_range)
69 sub r1, r1, #1
70 add r1, r0, r1
71 mcrr p15, 0, r1, r0, c5 /* invalidate IC range */
72 mcrr p15, 0, r1, r0, c12 /* clean DC range */
73 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
74 RET
75 END(pj4b_icache_sync_range)
76
77 ENTRY(pj4b_dcache_inv_range)
78 ldr ip, .Lpj4b_cache_line_size
79 ldr ip, [ip]
80 sub r1, r1, #1 /* Don't overrun */
81 sub r3, ip, #1
82 and r2, r0, r3
83 add r1, r1, r2
84 bic r0, r0, r3
85
86 mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4413 */
87 1:
88 mcr p15, 0, r0, c7, c6, 1
89 add r0, r0, ip
90 subs r1, r1, ip
91 bpl 1b
92 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
93 RET
94 END(pj4b_dcache_inv_range)
95
96 ENTRY(armv6_idcache_wbinv_all)
97 mov r0, #0
98 mcr p15, 0, r0, c7, c5, 0 /* invalidate ICache */
99 mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate DCache */
100 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
101 RET
102 END(armv6_idcache_wbinv_all)
103
104 ENTRY(armv6_dcache_wbinv_all)
105 mov r0, #0
106 mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate DCache */
107 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
108 RET
109 END(armv6_dcache_wbinv_all)
110
111 ENTRY(pj4b_idcache_wbinv_range)
112 ldr ip, .Lpj4b_cache_line_size
113 ldr ip, [ip]
114 sub r1, r1, #1 /* Don't overrun */
115 sub r3, ip, #1
116 and r2, r0, r3
117 add r1, r1, r2
118 bic r0, r0, r3
119
120 mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */
121 1:
122 #ifdef SMP
123 /* Request for ownership */
124 ldr r2, [r0]
125 str r2, [r0]
126 #endif
127 mcr p15, 0, r0, c7, c5, 1
128 mcr p15, 0, r0, c7, c14, 1 /* L2C clean and invalidate entry */
129 add r0, r0, ip
130 subs r1, r1, ip
131 bpl 1b
132 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
133 RET
134 END(pj4b_idcache_wbinv_range)
135
136 ENTRY(pj4b_dcache_wbinv_range)
137 ldr ip, .Lpj4b_cache_line_size
138 ldr ip, [ip]
139 sub r1, r1, #1 /* Don't overrun */
140 sub r3, ip, #1
141 and r2, r0, r3
142 add r1, r1, r2
143 bic r0, r0, r3
144
145 mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */
146 1:
147 #ifdef SMP
148 /* Request for ownership */
149 ldr r2, [r0]
150 str r2, [r0]
151 #endif
152 mcr p15, 0, r0, c7, c14, 1
153 add r0, r0, ip
154 subs r1, r1, ip
155 bpl 1b
156 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
157 RET
158 END(pj4b_dcache_wbinv_range)
159
160 ENTRY(pj4b_dcache_wb_range)
161 ldr ip, .Lpj4b_cache_line_size
162 ldr ip, [ip]
163 sub r1, r1, #1 /* Don't overrun */
164 sub r3, ip, #1
165 and r2, r0, r3
166 add r1, r1, r2
167 bic r0, r0, r3
168
169 mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */
170 1:
171 #ifdef SMP
172 /* Request for ownership */
173 ldr r2, [r0]
174 str r2, [r0]
175 #endif
176 mcr p15, 0, r0, c7, c10, 1 /* L2C clean single entry by MVA */
177 add r0, r0, ip
178 subs r1, r1, ip
179 bpl 1b
180 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
181 RET
182 END(pj4b_dcache_wb_range)
183
184 ENTRY(pj4b_drain_readbuf)
185 mcr p15, 0, r0, c7, c5, 4 /* flush prefetch buffers */
186 RET
187 END(pj4b_drain_readbuf)
188
189 ENTRY(pj4b_flush_brnchtgt_all)
190 mcr p15, 0, r0, c7, c5, 6 /* flush entrie branch target cache */
191 RET
192 END(pj4b_flush_brnchtgt_all)
193
194 ENTRY(pj4b_flush_brnchtgt_va)
195 mcr p15, 0, r0, c7, c5, 7 /* flush branch target cache by VA */
196 RET
197 END(pj4b_flush_brnchtgt_va)
198
199 ENTRY(get_core_id)
200 mrc p15, 0, r0, c0, c0, 5
201 RET
202 END(get_core_id)
203
204 ENTRY(pj4b_config)
205
206 /* Set Auxiliary Debug Modes Control 0 register */
207 mrc p15, 1, r0, c15, c1, 0
208 /* ARMADAXP errata fix: ARM-CPU-6136 */
209 bic r0, r0, #(1 << 12) /* LDSTM first issue is single word */
210
211 orr r0, r0, #(1 << 22) /* DVM_WAKEUP disable */
212 mcr p15, 1, r0, c15, c1, 0
213
214 /* Set Auxiliary Debug Modes Control 1 register */
215 mrc p15, 1, r0, c15, c1, 1
216 /* ARMADAXP errata fix: ARM-CPU-6409 */
217 bic r0, r0, #(1 << 2) /* Disable static branch prediction */
218
219 orr r0, r0, #(1 << 5) /* STREX backoff disable */
220 orr r0, r0, #(1 << 8) /* Internal parity handling disable */
221 orr r0, r0, #(1 << 16) /* Disable data transfer for clean line */
222 mcr p15, 1, r0, c15, c1, 1
223
224 /* Set Auxiliary Function Modes Control 0 register */
225 mrc p15, 1, r0, c15, c2, 0
226 #if defined(SMP)
227 orr r0, r0, #(1 << 1) /* SMP/nAMP enabled (coherency) */
228 #endif
229 orr r0, r0, #(1 << 2) /* L1 parite enable */
230 orr r0, r0, #(1 << 8) /* Cache and TLB maintenance broadcast enable */
231 mcr p15, 1, r0, c15, c2, 0
232
233 /* Set Auxiliary Debug Modes Control 2 register */
234 mrc p15, 1, r0, c15, c1, 2
235 bic r0, r0, #(1 << 23) /* Enable fast LDR */
236 orr r0, r0, #(1 << 25) /* Intervention Interleave disable */
237 orr r0, r0, #(1 << 27) /* Critical word first sequencing disable */
238 orr r0, r0, #(1 << 29) /* Disable MO device read / write */
239 orr r0, r0, #(1 << 30) /* L1 cache strict round-robin replacement policy*/
240 orr r0, r0, #(1 << 31) /* Enable write evict */
241 mcr p15, 1, r0, c15, c1, 2
242 #if defined(SMP)
243 /* Set SMP mode in Auxiliary Control Register */
244 mrc p15, 0, r0, c1, c0, 1
245 orr r0, r0, #(1 << 5)
246 mcr p15, 0, r0, c1, c0, 1
247 #endif
248
249 /* Load CPU number */
250 mrc p15, 0, r0, c0, c0, 5
251 and r0, r0, #0xf
252
253 /* SF Enable and invalidate */
254 ldr r1, .Lpj4b_sf_ctrl_reg
255 ldr r2, [r1, r0, lsl #8]
256 orr r2, r2, #(1 << 0)
257 bic r2, r2, #(1 << 8)
258 str r2, [r1, r0, lsl #8]
259
260 RET
261 END(pj4b_config)
262
Cache object: 924720f4a96ae2e03a088a9edb7f9b6d
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