cpufunc_asm_pj4b.S

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    1 /*-
    2  * Copyright (C) 2011 MARVELL INTERNATIONAL LTD.
    3  * All rights reserved.
    4  *
    5  * Developed by Semihalf.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. Neither the name of MARVELL nor the names of contributors
   16  *    may be used to endorse or promote products derived from this software
   17  *    without specific prior written permission.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
   23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  */
   31 
   32 #include <machine/asm.h>
   33 __FBSDID("$FreeBSD$");
   34 
   35 #include <machine/param.h>
   36 
   37 .Lpj4b_sf_ctrl_reg:
   38         .word   0xf1021820
   39 
   40 ENTRY(pj4b_config)
   41 
   42         /* Set Auxiliary Debug Modes Control 0 register */
   43         mrc     p15, 1, r0, c15, c1, 0
   44         /* ARMADAXP errata fix: ARM-CPU-6136 */
   45         bic     r0, r0, #(1 << 12)      /* LDSTM first issue is single word */
   46 
   47         orr     r0, r0, #(1 << 22)      /* DVM_WAKEUP disable */
   48         mcr     p15, 1, r0, c15, c1, 0
   49 
   50         /* Set Auxiliary Debug Modes Control 1 register */
   51         mrc     p15, 1, r0, c15, c1, 1
   52         /* ARMADAXP errata fix: ARM-CPU-6409 */
   53         bic     r0, r0, #(1 << 2)       /* Disable static branch prediction */
   54 
   55         orr     r0, r0, #(1 << 5)       /* STREX backoff disable */
   56         orr     r0, r0, #(1 << 8)       /* Internal parity handling disable */
   57         orr     r0, r0, #(1 << 16)      /* Disable data transfer for clean line */
   58         mcr     p15, 1, r0, c15, c1, 1
   59 
   60         /* Set Auxiliary Function Modes Control 0 register */
   61         mrc     p15, 1, r0, c15, c2, 0
   62 #if defined(SMP)
   63         orr     r0, r0, #(1 << 1)       /* SMP/nAMP enabled (coherency) */
   64 #endif
   65         orr     r0, r0, #(1 << 2)       /* L1 parite enable */
   66         orr     r0, r0, #(1 << 8)       /* Cache and TLB maintenance broadcast enable */
   67         mcr     p15, 1, r0, c15, c2, 0
   68 
   69         /* Set Auxiliary Debug Modes Control 2 register */
   70         mrc     p15, 1, r0, c15, c1, 2
   71         bic     r0, r0, #(1 << 23)      /* Enable fast LDR */
   72         orr     r0, r0, #(1 << 25)      /* Intervention Interleave disable */
   73         orr     r0, r0, #(1 << 27)      /* Critical word first sequencing disable */
   74         orr     r0, r0, #(1 << 29)      /* Disable MO device read / write */
   75         orr     r0, r0, #(1 << 30)      /* L1 cache strict round-robin replacement policy*/
   76         orr     r0, r0, #(1 << 31)      /* Enable write evict */
   77         mcr     p15, 1, r0, c15, c1, 2
   78 #if defined(SMP)
   79         /* Set SMP mode in Auxiliary Control Register */
   80         mrc     p15, 0, r0, c1, c0, 1
   81         orr     r0, r0, #(1 << 5)
   82         mcr     p15, 0, r0, c1, c0, 1
   83 #endif
   84 
   85         /* Load CPU number */
   86         mrc     p15, 0, r0, c0, c0, 5
   87         and     r0, r0, #0xf
   88 
   89         /* SF Enable and invalidate */
   90         ldr     r1, .Lpj4b_sf_ctrl_reg
   91         ldr     r2, [r1, r0, lsl #8]
   92         orr     r2, r2, #(1 << 0)
   93         bic     r2, r2, #(1 << 8)
   94         str     r2, [r1, r0, lsl #8]
   95 
   96         RET
   97 END(pj4b_config)
   98

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FreeBSD/Linux Kernel Cross Reference sys/arm/arm/cpufunc_asm_pj4b.S

FreeBSD/Linux Kernel Cross Reference
sys/arm/arm/cpufunc_asm_pj4b.S