1 /* $NetBSD: db_interface.c,v 1.33 2003/08/25 04:51:10 mrg Exp $ */
2
3 /*-
4 * Copyright (c) 1996 Scott K. Stevens
5 *
6 * Mach Operating System
7 * Copyright (c) 1991,1990 Carnegie Mellon University
8 * All Rights Reserved.
9 *
10 * Permission to use, copy, modify and distribute this software and its
11 * documentation is hereby granted, provided that both the copyright
12 * notice and this permission notice appear in all copies of the
13 * software, derivative works or modified versions, and any portions
14 * thereof, and that both notices appear in supporting documentation.
15 *
16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
19 *
20 * Carnegie Mellon requests users of this software to return to
21 *
22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
23 * School of Computer Science
24 * Carnegie Mellon University
25 * Pittsburgh PA 15213-3890
26 *
27 * any improvements or extensions that they make and grant Carnegie the
28 * rights to redistribute these changes.
29 *
30 * From: db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU)
31 */
32
33 /*
34 * Interface to new debugger.
35 */
36
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD: src/sys/arm/arm/db_interface.c,v 1.9 2008/08/03 15:35:32 cognet Exp $");
39 #include "opt_ddb.h"
40
41 #include <sys/param.h>
42 #include <sys/proc.h>
43 #include <sys/reboot.h>
44 #include <sys/systm.h> /* just for boothowto */
45 #include <sys/exec.h>
46 #ifdef KDB
47 #include <sys/kdb.h>
48 #endif
49
50 #include <vm/vm.h>
51 #include <vm/pmap.h>
52 #include <vm/vm_map.h>
53 #include <vm/vm_extern.h>
54
55 #include <machine/db_machdep.h>
56 #include <machine/vmparam.h>
57 #include <machine/cpu.h>
58
59 #include <ddb/ddb.h>
60 #include <ddb/db_access.h>
61 #include <ddb/db_command.h>
62 #include <ddb/db_output.h>
63 #include <ddb/db_variables.h>
64 #include <ddb/db_sym.h>
65 #include <sys/cons.h>
66
67 static int nil = 0;
68
69 int db_access_und_sp (struct db_variable *, db_expr_t *, int);
70 int db_access_abt_sp (struct db_variable *, db_expr_t *, int);
71 int db_access_irq_sp (struct db_variable *, db_expr_t *, int);
72
73 static db_varfcn_t db_frame;
74
75 #define DB_OFFSET(x) (db_expr_t *)offsetof(struct trapframe, x)
76 struct db_variable db_regs[] = {
77 { "spsr", DB_OFFSET(tf_spsr), db_frame },
78 { "r0", DB_OFFSET(tf_r0), db_frame },
79 { "r1", DB_OFFSET(tf_r1), db_frame },
80 { "r2", DB_OFFSET(tf_r2), db_frame },
81 { "r3", DB_OFFSET(tf_r3), db_frame },
82 { "r4", DB_OFFSET(tf_r4), db_frame },
83 { "r5", DB_OFFSET(tf_r5), db_frame },
84 { "r6", DB_OFFSET(tf_r6), db_frame },
85 { "r7", DB_OFFSET(tf_r7), db_frame },
86 { "r8", DB_OFFSET(tf_r8), db_frame },
87 { "r9", DB_OFFSET(tf_r9), db_frame },
88 { "r10", DB_OFFSET(tf_r10), db_frame },
89 { "r11", DB_OFFSET(tf_r11), db_frame },
90 { "r12", DB_OFFSET(tf_r12), db_frame },
91 { "usr_sp", DB_OFFSET(tf_usr_sp), db_frame },
92 { "usr_lr", DB_OFFSET(tf_usr_lr), db_frame },
93 { "svc_sp", DB_OFFSET(tf_svc_sp), db_frame },
94 { "svc_lr", DB_OFFSET(tf_svc_lr), db_frame },
95 { "pc", DB_OFFSET(tf_pc), db_frame },
96 { "und_sp", &nil, db_access_und_sp, },
97 { "abt_sp", &nil, db_access_abt_sp, },
98 { "irq_sp", &nil, db_access_irq_sp, },
99 };
100
101 struct db_variable *db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]);
102
103 int
104 db_access_und_sp(struct db_variable *vp, db_expr_t *valp, int rw)
105 {
106
107 if (rw == DB_VAR_GET) {
108 *valp = get_stackptr(PSR_UND32_MODE);
109 return (1);
110 }
111 return (0);
112 }
113
114 int
115 db_access_abt_sp(struct db_variable *vp, db_expr_t *valp, int rw)
116 {
117
118 if (rw == DB_VAR_GET) {
119 *valp = get_stackptr(PSR_ABT32_MODE);
120 return (1);
121 }
122 return (0);
123 }
124
125 int
126 db_access_irq_sp(struct db_variable *vp, db_expr_t *valp, int rw)
127 {
128
129 if (rw == DB_VAR_GET) {
130 *valp = get_stackptr(PSR_IRQ32_MODE);
131 return (1);
132 }
133 return (0);
134 }
135
136 int db_frame(struct db_variable *vp, db_expr_t *valp, int rw)
137 {
138 int *reg;
139
140 if (kdb_frame == NULL)
141 return (0);
142
143 reg = (int *)((uintptr_t)kdb_frame + (db_expr_t)vp->valuep);
144 if (rw == DB_VAR_GET)
145 *valp = *reg;
146 else
147 *reg = *valp;
148 return (1);
149 }
150
151 void
152 db_show_mdpcpu(struct pcpu *pc)
153 {
154 }
155 int
156 db_validate_address(vm_offset_t addr)
157 {
158 struct proc *p = curproc;
159 struct pmap *pmap;
160
161 if (!p || !p->p_vmspace || !p->p_vmspace->vm_map.pmap ||
162 #ifndef ARM32_NEW_VM_LAYOUT
163 addr >= VM_MAXUSER_ADDRESS
164 #else
165 addr >= VM_MIN_KERNEL_ADDRESS
166 #endif
167 )
168 pmap = pmap_kernel();
169 else
170 pmap = p->p_vmspace->vm_map.pmap;
171
172 return (pmap_extract(pmap, addr) == FALSE);
173 }
174
175 /*
176 * Read bytes from kernel address space for debugger.
177 */
178 int
179 db_read_bytes(addr, size, data)
180 vm_offset_t addr;
181 size_t size;
182 char *data;
183 {
184 char *src = (char *)addr;
185
186 if (db_validate_address((u_int)src)) {
187 db_printf("address %p is invalid\n", src);
188 return (-1);
189 }
190
191 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) {
192 *((int*)data) = *((int*)src);
193 return (0);
194 }
195
196 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) {
197 *((short*)data) = *((short*)src);
198 return (0);
199 }
200
201 while (size-- > 0) {
202 if (db_validate_address((u_int)src)) {
203 db_printf("address %p is invalid\n", src);
204 return (-1);
205 }
206 *data++ = *src++;
207 }
208 return (0);
209 }
210
211 /*
212 * Write bytes to kernel address space for debugger.
213 */
214 int
215 db_write_bytes(vm_offset_t addr, size_t size, char *data)
216 {
217 char *dst;
218 size_t loop;
219
220 dst = (char *)addr;
221 if (db_validate_address((u_int)dst)) {
222 db_printf("address %p is invalid\n", dst);
223 return (0);
224 }
225
226 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0)
227 *((int*)dst) = *((int*)data);
228 else
229 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0)
230 *((short*)dst) = *((short*)data);
231 else {
232 loop = size;
233 while (loop-- > 0) {
234 if (db_validate_address((u_int)dst)) {
235 db_printf("address %p is invalid\n", dst);
236 return (-1);
237 }
238 *dst++ = *data++;
239 }
240 }
241
242 /* make sure the caches and memory are in sync */
243 cpu_icache_sync_range(addr, size);
244
245 /* In case the current page tables have been modified ... */
246 cpu_tlb_flushID();
247 cpu_cpwait();
248 return (0);
249 }
250
251
252 static u_int
253 db_fetch_reg(int reg)
254 {
255
256 switch (reg) {
257 case 0:
258 return (kdb_frame->tf_r0);
259 case 1:
260 return (kdb_frame->tf_r1);
261 case 2:
262 return (kdb_frame->tf_r2);
263 case 3:
264 return (kdb_frame->tf_r3);
265 case 4:
266 return (kdb_frame->tf_r4);
267 case 5:
268 return (kdb_frame->tf_r5);
269 case 6:
270 return (kdb_frame->tf_r6);
271 case 7:
272 return (kdb_frame->tf_r7);
273 case 8:
274 return (kdb_frame->tf_r8);
275 case 9:
276 return (kdb_frame->tf_r9);
277 case 10:
278 return (kdb_frame->tf_r10);
279 case 11:
280 return (kdb_frame->tf_r11);
281 case 12:
282 return (kdb_frame->tf_r12);
283 case 13:
284 return (kdb_frame->tf_svc_sp);
285 case 14:
286 return (kdb_frame->tf_svc_lr);
287 case 15:
288 return (kdb_frame->tf_pc);
289 default:
290 panic("db_fetch_reg: botch");
291 }
292 }
293
294 u_int
295 branch_taken(u_int insn, db_addr_t pc)
296 {
297 u_int addr, nregs, offset = 0;
298
299 switch ((insn >> 24) & 0xf) {
300 case 0x2: /* add pc, reg1, #value */
301 case 0x0: /* add pc, reg1, reg2, lsl #offset */
302 addr = db_fetch_reg((insn >> 16) & 0xf);
303 if (((insn >> 16) & 0xf) == 15)
304 addr += 8;
305 if (insn & 0x0200000) {
306 offset = (insn >> 7) & 0x1e;
307 offset = (insn & 0xff) << (32 - offset) |
308 (insn & 0xff) >> offset;
309 } else {
310
311 offset = db_fetch_reg(insn & 0x0f);
312 if ((insn & 0x0000ff0) != 0x00000000) {
313 if (insn & 0x10)
314 nregs = db_fetch_reg((insn >> 8) & 0xf);
315 else
316 nregs = (insn >> 7) & 0x1f;
317 switch ((insn >> 5) & 3) {
318 case 0:
319 /* lsl */
320 offset = offset << nregs;
321 break;
322 case 1:
323 /* lsr */
324 offset = offset >> nregs;
325 break;
326 default:
327 break; /* XXX */
328 }
329
330 }
331 return (addr + offset);
332
333 }
334
335 case 0xa: /* b ... */
336 case 0xb: /* bl ... */
337 addr = ((insn << 2) & 0x03ffffff);
338 if (addr & 0x02000000)
339 addr |= 0xfc000000;
340 return (pc + 8 + addr);
341 case 0x7: /* ldr pc, [pc, reg, lsl #2] */
342 addr = db_fetch_reg(insn & 0xf);
343 addr = pc + 8 + (addr << 2);
344 db_read_bytes(addr, 4, (char *)&addr);
345 return (addr);
346 case 0x1: /* mov pc, reg */
347 addr = db_fetch_reg(insn & 0xf);
348 return (addr);
349 case 0x4:
350 case 0x5: /* ldr pc, [reg] */
351 addr = db_fetch_reg((insn >> 16) & 0xf);
352 /* ldr pc, [reg, #offset] */
353 if (insn & (1 << 24))
354 offset = insn & 0xfff;
355 if (insn & 0x00800000)
356 addr += offset;
357 else
358 addr -= offset;
359 db_read_bytes(addr, 4, (char *)&addr);
360 return (addr);
361 case 0x8: /* ldmxx reg, {..., pc} */
362 case 0x9:
363 addr = db_fetch_reg((insn >> 16) & 0xf);
364 nregs = (insn & 0x5555) + ((insn >> 1) & 0x5555);
365 nregs = (nregs & 0x3333) + ((nregs >> 2) & 0x3333);
366 nregs = (nregs + (nregs >> 4)) & 0x0f0f;
367 nregs = (nregs + (nregs >> 8)) & 0x001f;
368 switch ((insn >> 23) & 0x3) {
369 case 0x0: /* ldmda */
370 addr = addr - 0;
371 break;
372 case 0x1: /* ldmia */
373 addr = addr + 0 + ((nregs - 1) << 2);
374 break;
375 case 0x2: /* ldmdb */
376 addr = addr - 4;
377 break;
378 case 0x3: /* ldmib */
379 addr = addr + 4 + ((nregs - 1) << 2);
380 break;
381 }
382 db_read_bytes(addr, 4, (char *)&addr);
383 return (addr);
384 default:
385 panic("branch_taken: botch");
386 }
387 }
388 Cache object: f7519dbaf5786a13e947df15d748271c
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