1 /* $NetBSD: db_interface.c,v 1.33 2003/08/25 04:51:10 mrg Exp $ */
2
3 /*-
4 * Copyright (c) 1996 Scott K. Stevens
5 *
6 * Mach Operating System
7 * Copyright (c) 1991,1990 Carnegie Mellon University
8 * All Rights Reserved.
9 *
10 * Permission to use, copy, modify and distribute this software and its
11 * documentation is hereby granted, provided that both the copyright
12 * notice and this permission notice appear in all copies of the
13 * software, derivative works or modified versions, and any portions
14 * thereof, and that both notices appear in supporting documentation.
15 *
16 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
17 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
18 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
19 *
20 * Carnegie Mellon requests users of this software to return to
21 *
22 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
23 * School of Computer Science
24 * Carnegie Mellon University
25 * Pittsburgh PA 15213-3890
26 *
27 * any improvements or extensions that they make and grant Carnegie the
28 * rights to redistribute these changes.
29 *
30 * From: db_interface.c,v 2.4 1991/02/05 17:11:13 mrt (CMU)
31 */
32
33 /*
34 * Interface to new debugger.
35 */
36
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
39 #include "opt_ddb.h"
40
41 #include <sys/param.h>
42 #include <sys/cons.h>
43 #include <sys/proc.h>
44 #include <sys/reboot.h>
45 #include <sys/systm.h> /* just for boothowto */
46 #include <sys/exec.h>
47 #ifdef KDB
48 #include <sys/kdb.h>
49 #endif
50
51 #include <vm/vm.h>
52 #include <vm/pmap.h>
53 #include <vm/vm_map.h>
54 #include <vm/vm_extern.h>
55
56 #include <machine/db_machdep.h>
57 #include <machine/cpu.h>
58 #include <machine/machdep.h>
59 #include <machine/vmparam.h>
60
61 #include <ddb/ddb.h>
62 #include <ddb/db_access.h>
63 #include <ddb/db_command.h>
64 #include <ddb/db_output.h>
65 #include <ddb/db_variables.h>
66 #include <ddb/db_sym.h>
67
68 static int nil = 0;
69
70 int db_access_und_sp (struct db_variable *, db_expr_t *, int);
71 int db_access_abt_sp (struct db_variable *, db_expr_t *, int);
72 int db_access_irq_sp (struct db_variable *, db_expr_t *, int);
73
74 static db_varfcn_t db_frame;
75
76 #define DB_OFFSET(x) (db_expr_t *)offsetof(struct trapframe, x)
77 struct db_variable db_regs[] = {
78 { "spsr", DB_OFFSET(tf_spsr), db_frame },
79 { "r0", DB_OFFSET(tf_r0), db_frame },
80 { "r1", DB_OFFSET(tf_r1), db_frame },
81 { "r2", DB_OFFSET(tf_r2), db_frame },
82 { "r3", DB_OFFSET(tf_r3), db_frame },
83 { "r4", DB_OFFSET(tf_r4), db_frame },
84 { "r5", DB_OFFSET(tf_r5), db_frame },
85 { "r6", DB_OFFSET(tf_r6), db_frame },
86 { "r7", DB_OFFSET(tf_r7), db_frame },
87 { "r8", DB_OFFSET(tf_r8), db_frame },
88 { "r9", DB_OFFSET(tf_r9), db_frame },
89 { "r10", DB_OFFSET(tf_r10), db_frame },
90 { "r11", DB_OFFSET(tf_r11), db_frame },
91 { "r12", DB_OFFSET(tf_r12), db_frame },
92 { "usr_sp", DB_OFFSET(tf_usr_sp), db_frame },
93 { "usr_lr", DB_OFFSET(tf_usr_lr), db_frame },
94 { "svc_sp", DB_OFFSET(tf_svc_sp), db_frame },
95 { "svc_lr", DB_OFFSET(tf_svc_lr), db_frame },
96 { "pc", DB_OFFSET(tf_pc), db_frame },
97 { "und_sp", &nil, db_access_und_sp, },
98 { "abt_sp", &nil, db_access_abt_sp, },
99 { "irq_sp", &nil, db_access_irq_sp, },
100 };
101
102 struct db_variable *db_eregs = db_regs + nitems(db_regs);
103
104 int
105 db_access_und_sp(struct db_variable *vp, db_expr_t *valp, int rw)
106 {
107
108 if (rw == DB_VAR_GET) {
109 *valp = get_stackptr(PSR_UND32_MODE);
110 return (1);
111 }
112 return (0);
113 }
114
115 int
116 db_access_abt_sp(struct db_variable *vp, db_expr_t *valp, int rw)
117 {
118
119 if (rw == DB_VAR_GET) {
120 *valp = get_stackptr(PSR_ABT32_MODE);
121 return (1);
122 }
123 return (0);
124 }
125
126 int
127 db_access_irq_sp(struct db_variable *vp, db_expr_t *valp, int rw)
128 {
129
130 if (rw == DB_VAR_GET) {
131 *valp = get_stackptr(PSR_IRQ32_MODE);
132 return (1);
133 }
134 return (0);
135 }
136
137 int db_frame(struct db_variable *vp, db_expr_t *valp, int rw)
138 {
139 int *reg;
140
141 if (kdb_frame == NULL)
142 return (0);
143
144 reg = (int *)((uintptr_t)kdb_frame + (db_expr_t)vp->valuep);
145 if (rw == DB_VAR_GET)
146 *valp = *reg;
147 else
148 *reg = *valp;
149 return (1);
150 }
151
152 void
153 db_show_mdpcpu(struct pcpu *pc)
154 {
155
156 db_printf("curpmap = %p\n", pc->pc_curpmap);
157 }
158
159 int
160 db_validate_address(vm_offset_t addr)
161 {
162 struct proc *p = curproc;
163 struct pmap *pmap;
164
165 if (!p || !p->p_vmspace || !p->p_vmspace->vm_map.pmap ||
166 #ifndef ARM32_NEW_VM_LAYOUT
167 addr >= VM_MAXUSER_ADDRESS
168 #else
169 addr >= VM_MIN_KERNEL_ADDRESS
170 #endif
171 )
172 pmap = kernel_pmap;
173 else
174 pmap = p->p_vmspace->vm_map.pmap;
175
176 return (pmap_extract(pmap, addr) == FALSE);
177 }
178
179 /*
180 * Read bytes from kernel address space for debugger.
181 */
182 int
183 db_read_bytes(addr, size, data)
184 vm_offset_t addr;
185 size_t size;
186 char *data;
187 {
188 char *src = (char *)addr;
189
190 if (db_validate_address((u_int)src)) {
191 db_printf("address %p is invalid\n", src);
192 return (-1);
193 }
194
195 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0) {
196 *((int*)data) = *((int*)src);
197 return (0);
198 }
199
200 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0) {
201 *((short*)data) = *((short*)src);
202 return (0);
203 }
204
205 while (size-- > 0) {
206 if (db_validate_address((u_int)src)) {
207 db_printf("address %p is invalid\n", src);
208 return (-1);
209 }
210 *data++ = *src++;
211 }
212 return (0);
213 }
214
215 /*
216 * Write bytes to kernel address space for debugger.
217 */
218 int
219 db_write_bytes(vm_offset_t addr, size_t size, char *data)
220 {
221 char *dst;
222 size_t loop;
223
224 dst = (char *)addr;
225 if (db_validate_address((u_int)dst)) {
226 db_printf("address %p is invalid\n", dst);
227 return (0);
228 }
229
230 if (size == 4 && (addr & 3) == 0 && ((uintptr_t)data & 3) == 0)
231 *((int*)dst) = *((int*)data);
232 else
233 if (size == 2 && (addr & 1) == 0 && ((uintptr_t)data & 1) == 0)
234 *((short*)dst) = *((short*)data);
235 else {
236 loop = size;
237 while (loop-- > 0) {
238 if (db_validate_address((u_int)dst)) {
239 db_printf("address %p is invalid\n", dst);
240 return (-1);
241 }
242 *dst++ = *data++;
243 }
244 }
245
246 /* make sure the caches and memory are in sync */
247 icache_sync(addr, size);
248
249 /* In case the current page tables have been modified ... */
250 tlb_flush_all();
251 return (0);
252 }
253
254 static u_int
255 db_fetch_reg(int reg)
256 {
257
258 switch (reg) {
259 case 0:
260 return (kdb_frame->tf_r0);
261 case 1:
262 return (kdb_frame->tf_r1);
263 case 2:
264 return (kdb_frame->tf_r2);
265 case 3:
266 return (kdb_frame->tf_r3);
267 case 4:
268 return (kdb_frame->tf_r4);
269 case 5:
270 return (kdb_frame->tf_r5);
271 case 6:
272 return (kdb_frame->tf_r6);
273 case 7:
274 return (kdb_frame->tf_r7);
275 case 8:
276 return (kdb_frame->tf_r8);
277 case 9:
278 return (kdb_frame->tf_r9);
279 case 10:
280 return (kdb_frame->tf_r10);
281 case 11:
282 return (kdb_frame->tf_r11);
283 case 12:
284 return (kdb_frame->tf_r12);
285 case 13:
286 return (kdb_frame->tf_svc_sp);
287 case 14:
288 return (kdb_frame->tf_svc_lr);
289 case 15:
290 return (kdb_frame->tf_pc);
291 default:
292 panic("db_fetch_reg: botch");
293 }
294 }
295
296 static u_int
297 db_branch_taken_read_int(void *cookie __unused, vm_offset_t offset, u_int *val)
298 {
299 u_int ret;
300
301 db_read_bytes(offset, 4, (char *)&ret);
302 *val = ret;
303
304 return (0);
305 }
306
307 static u_int
308 db_branch_taken_fetch_reg(void *cookie __unused, int reg)
309 {
310
311 return (db_fetch_reg(reg));
312 }
313
314 u_int
315 branch_taken(u_int insn, db_addr_t pc)
316 {
317 register_t new_pc;
318 int ret;
319
320 ret = arm_predict_branch(NULL, insn, (register_t)pc, &new_pc,
321 db_branch_taken_fetch_reg, db_branch_taken_read_int);
322
323 if (ret != 0)
324 kdb_reenter();
325
326 return (new_pc);
327 }
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