Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/arm/disassem.c
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1 /* $NetBSD: disassem.c,v 1.14 2003/03/27 16:58:36 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1996 Mark Brinicombe. 5 * Copyright (c) 1996 Brini. 6 * 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Brini. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * RiscBSD kernel project 37 * 38 * db_disasm.c 39 * 40 * Kernel disassembler 41 * 42 * Created : 10/02/96 43 * 44 * Structured after the sparc/sparc/db_disasm.c by David S. Miller & 45 * Paul Kranenburg 46 * 47 * This code is not complete. Not all instructions are disassembled. 48 */ 49 50 #include <sys/cdefs.h> 51 __FBSDID("$FreeBSD$"); 52 #include <sys/param.h> 53 54 55 #include <sys/systm.h> 56 #include <machine/disassem.h> 57 #include <machine/armreg.h> 58 #include <machine/acle-compat.h> 59 #include <ddb/ddb.h> 60 61 /* 62 * General instruction format 63 * 64 * insn[cc][mod] [operands] 65 * 66 * Those fields with an uppercase format code indicate that the field 67 * follows directly after the instruction before the separator i.e. 68 * they modify the instruction rather than just being an operand to 69 * the instruction. The only exception is the writeback flag which 70 * follows a operand. 71 * 72 * 73 * 2 - print Operand 2 of a data processing instruction 74 * d - destination register (bits 12-15) 75 * n - n register (bits 16-19) 76 * s - s register (bits 8-11) 77 * o - indirect register rn (bits 16-19) (used by swap) 78 * m - m register (bits 0-3) 79 * a - address operand of ldr/str instruction 80 * l - register list for ldm/stm instruction 81 * f - 1st fp operand (register) (bits 12-14) 82 * g - 2nd fp operand (register) (bits 16-18) 83 * h - 3rd fp operand (register/immediate) (bits 0-4) 84 * b - branch address 85 * t - thumb branch address (bits 24, 0-23) 86 * k - breakpoint comment (bits 0-3, 8-19) 87 * X - block transfer type 88 * Y - block transfer type (r13 base) 89 * c - comment field bits(0-23) 90 * p - saved or current status register 91 * F - PSR transfer fields 92 * D - destination-is-r15 (P) flag on TST, TEQ, CMP, CMN 93 * L - co-processor transfer size 94 * S - set status flag 95 * P - fp precision 96 * Q - fp precision (for ldf/stf) 97 * R - fp rounding 98 * v - co-processor data transfer registers + addressing mode 99 * W - writeback flag 100 * x - instruction in hex 101 * # - co-processor number 102 * y - co-processor data processing registers 103 * z - co-processor register transfer registers 104 */ 105 106 struct arm32_insn { 107 u_int mask; 108 u_int pattern; 109 char* name; 110 char* format; 111 }; 112 113 static const struct arm32_insn arm32_i[] = { 114 { 0x0fffffff, 0x0ff00000, "imb", "c" }, /* Before swi */ 115 { 0x0fffffff, 0x0ff00001, "imbrange", "c" }, /* Before swi */ 116 { 0x0f000000, 0x0f000000, "swi", "c" }, 117 { 0xfe000000, 0xfa000000, "blx", "t" }, /* Before b and bl */ 118 { 0x0f000000, 0x0a000000, "b", "b" }, 119 { 0x0f000000, 0x0b000000, "bl", "b" }, 120 { 0x0fe000f0, 0x00000090, "mul", "Snms" }, 121 { 0x0fe000f0, 0x00200090, "mla", "Snmsd" }, 122 { 0x0fe000f0, 0x00800090, "umull", "Sdnms" }, 123 { 0x0fe000f0, 0x00c00090, "smull", "Sdnms" }, 124 { 0x0fe000f0, 0x00a00090, "umlal", "Sdnms" }, 125 { 0x0fe000f0, 0x00e00090, "smlal", "Sdnms" }, 126 { 0x0d700000, 0x04200000, "strt", "daW" }, 127 { 0x0d700000, 0x04300000, "ldrt", "daW" }, 128 { 0x0d700000, 0x04600000, "strbt", "daW" }, 129 { 0x0d700000, 0x04700000, "ldrbt", "daW" }, 130 { 0x0c500000, 0x04000000, "str", "daW" }, 131 { 0x0c500000, 0x04100000, "ldr", "daW" }, 132 { 0x0c500000, 0x04400000, "strb", "daW" }, 133 { 0x0c500000, 0x04500000, "ldrb", "daW" }, 134 #if __ARM_ARCH >= 6 135 { 0xffffffff, 0xf57ff01f, "clrex", "c" }, 136 { 0x0ff00ff0, 0x01800f90, "strex", "dmo" }, 137 { 0x0ff00fff, 0x01900f9f, "ldrex", "do" }, 138 { 0x0ff00ff0, 0x01a00f90, "strexd", "dmo" }, 139 { 0x0ff00fff, 0x01b00f9f, "ldrexd", "do" }, 140 { 0x0ff00ff0, 0x01c00f90, "strexb", "dmo" }, 141 { 0x0ff00fff, 0x01d00f9f, "ldrexb", "do" }, 142 { 0x0ff00ff0, 0x01e00f90, "strexh", "dmo" }, 143 { 0x0ff00fff, 0x01f00f9f, "ldrexh", "do" }, 144 #endif 145 { 0x0e1f0000, 0x080d0000, "stm", "YnWl" },/* separate out r13 base */ 146 { 0x0e1f0000, 0x081d0000, "ldm", "YnWl" },/* separate out r13 base */ 147 { 0x0e100000, 0x08000000, "stm", "XnWl" }, 148 { 0x0e100000, 0x08100000, "ldm", "XnWl" }, 149 { 0x0e1000f0, 0x00100090, "ldrb", "de" }, 150 { 0x0e1000f0, 0x00000090, "strb", "de" }, 151 { 0x0e1000f0, 0x001000d0, "ldrsb", "de" }, 152 { 0x0e1000f0, 0x001000b0, "ldrh", "de" }, 153 { 0x0e1000f0, 0x000000b0, "strh", "de" }, 154 { 0x0e1000f0, 0x001000f0, "ldrsh", "de" }, 155 { 0x0f200090, 0x00200090, "und", "x" }, /* Before data processing */ 156 { 0x0e1000d0, 0x000000d0, "und", "x" }, /* Before data processing */ 157 { 0x0ff00ff0, 0x01000090, "swp", "dmo" }, 158 { 0x0ff00ff0, 0x01400090, "swpb", "dmo" }, 159 { 0x0fbf0fff, 0x010f0000, "mrs", "dp" }, /* Before data processing */ 160 { 0x0fb0fff0, 0x0120f000, "msr", "pFm" },/* Before data processing */ 161 { 0x0fb0f000, 0x0320f000, "msr", "pF2" },/* Before data processing */ 162 { 0x0ffffff0, 0x012fff10, "bx", "m" }, 163 { 0x0fff0ff0, 0x016f0f10, "clz", "dm" }, 164 { 0x0ffffff0, 0x012fff30, "blx", "m" }, 165 { 0xfff000f0, 0xe1200070, "bkpt", "k" }, 166 { 0x0de00000, 0x00000000, "and", "Sdn2" }, 167 { 0x0de00000, 0x00200000, "eor", "Sdn2" }, 168 { 0x0de00000, 0x00400000, "sub", "Sdn2" }, 169 { 0x0de00000, 0x00600000, "rsb", "Sdn2" }, 170 { 0x0de00000, 0x00800000, "add", "Sdn2" }, 171 { 0x0de00000, 0x00a00000, "adc", "Sdn2" }, 172 { 0x0de00000, 0x00c00000, "sbc", "Sdn2" }, 173 { 0x0de00000, 0x00e00000, "rsc", "Sdn2" }, 174 { 0x0df00000, 0x01100000, "tst", "Dn2" }, 175 { 0x0df00000, 0x01300000, "teq", "Dn2" }, 176 { 0x0de00000, 0x01400000, "cmp", "Dn2" }, 177 { 0x0de00000, 0x01600000, "cmn", "Dn2" }, 178 { 0x0de00000, 0x01800000, "orr", "Sdn2" }, 179 { 0x0de00000, 0x01a00000, "mov", "Sd2" }, 180 { 0x0de00000, 0x01c00000, "bic", "Sdn2" }, 181 { 0x0de00000, 0x01e00000, "mvn", "Sd2" }, 182 { 0x0ff08f10, 0x0e000100, "adf", "PRfgh" }, 183 { 0x0ff08f10, 0x0e100100, "muf", "PRfgh" }, 184 { 0x0ff08f10, 0x0e200100, "suf", "PRfgh" }, 185 { 0x0ff08f10, 0x0e300100, "rsf", "PRfgh" }, 186 { 0x0ff08f10, 0x0e400100, "dvf", "PRfgh" }, 187 { 0x0ff08f10, 0x0e500100, "rdf", "PRfgh" }, 188 { 0x0ff08f10, 0x0e600100, "pow", "PRfgh" }, 189 { 0x0ff08f10, 0x0e700100, "rpw", "PRfgh" }, 190 { 0x0ff08f10, 0x0e800100, "rmf", "PRfgh" }, 191 { 0x0ff08f10, 0x0e900100, "fml", "PRfgh" }, 192 { 0x0ff08f10, 0x0ea00100, "fdv", "PRfgh" }, 193 { 0x0ff08f10, 0x0eb00100, "frd", "PRfgh" }, 194 { 0x0ff08f10, 0x0ec00100, "pol", "PRfgh" }, 195 { 0x0f008f10, 0x0e000100, "fpbop", "PRfgh" }, 196 { 0x0ff08f10, 0x0e008100, "mvf", "PRfh" }, 197 { 0x0ff08f10, 0x0e108100, "mnf", "PRfh" }, 198 { 0x0ff08f10, 0x0e208100, "abs", "PRfh" }, 199 { 0x0ff08f10, 0x0e308100, "rnd", "PRfh" }, 200 { 0x0ff08f10, 0x0e408100, "sqt", "PRfh" }, 201 { 0x0ff08f10, 0x0e508100, "log", "PRfh" }, 202 { 0x0ff08f10, 0x0e608100, "lgn", "PRfh" }, 203 { 0x0ff08f10, 0x0e708100, "exp", "PRfh" }, 204 { 0x0ff08f10, 0x0e808100, "sin", "PRfh" }, 205 { 0x0ff08f10, 0x0e908100, "cos", "PRfh" }, 206 { 0x0ff08f10, 0x0ea08100, "tan", "PRfh" }, 207 { 0x0ff08f10, 0x0eb08100, "asn", "PRfh" }, 208 { 0x0ff08f10, 0x0ec08100, "acs", "PRfh" }, 209 { 0x0ff08f10, 0x0ed08100, "atn", "PRfh" }, 210 { 0x0f008f10, 0x0e008100, "fpuop", "PRfh" }, 211 { 0x0e100f00, 0x0c000100, "stf", "QLv" }, 212 { 0x0e100f00, 0x0c100100, "ldf", "QLv" }, 213 { 0x0ff00f10, 0x0e000110, "flt", "PRgd" }, 214 { 0x0ff00f10, 0x0e100110, "fix", "PRdh" }, 215 { 0x0ff00f10, 0x0e200110, "wfs", "d" }, 216 { 0x0ff00f10, 0x0e300110, "rfs", "d" }, 217 { 0x0ff00f10, 0x0e400110, "wfc", "d" }, 218 { 0x0ff00f10, 0x0e500110, "rfc", "d" }, 219 { 0x0ff0ff10, 0x0e90f110, "cmf", "PRgh" }, 220 { 0x0ff0ff10, 0x0eb0f110, "cnf", "PRgh" }, 221 { 0x0ff0ff10, 0x0ed0f110, "cmfe", "PRgh" }, 222 { 0x0ff0ff10, 0x0ef0f110, "cnfe", "PRgh" }, 223 { 0xff100010, 0xfe000010, "mcr2", "#z" }, 224 { 0x0f100010, 0x0e000010, "mcr", "#z" }, 225 { 0xff100010, 0xfe100010, "mrc2", "#z" }, 226 { 0x0f100010, 0x0e100010, "mrc", "#z" }, 227 { 0xff000010, 0xfe000000, "cdp2", "#y" }, 228 { 0x0f000010, 0x0e000000, "cdp", "#y" }, 229 { 0xfe100090, 0xfc100000, "ldc2", "L#v" }, 230 { 0x0e100090, 0x0c100000, "ldc", "L#v" }, 231 { 0xfe100090, 0xfc000000, "stc2", "L#v" }, 232 { 0x0e100090, 0x0c000000, "stc", "L#v" }, 233 { 0x00000000, 0x00000000, NULL, NULL } 234 }; 235 236 static char const arm32_insn_conditions[][4] = { 237 "eq", "ne", "cs", "cc", 238 "mi", "pl", "vs", "vc", 239 "hi", "ls", "ge", "lt", 240 "gt", "le", "", "nv" 241 }; 242 243 static char const insn_block_transfers[][4] = { 244 "da", "ia", "db", "ib" 245 }; 246 247 static char const insn_stack_block_transfers[][4] = { 248 "ed", "ea", "fd", "fa" 249 }; 250 251 static char const op_shifts[][4] = { 252 "lsl", "lsr", "asr", "ror" 253 }; 254 255 static char const insn_fpa_rounding[][2] = { 256 "", "p", "m", "z" 257 }; 258 259 static char const insn_fpa_precision[][2] = { 260 "s", "d", "e", "p" 261 }; 262 263 static char const insn_fpaconstants[][8] = { 264 "0.0", "1.0", "2.0", "3.0", 265 "4.0", "5.0", "0.5", "10.0" 266 }; 267 268 #define insn_condition(x) arm32_insn_conditions[(x >> 28) & 0x0f] 269 #define insn_blktrans(x) insn_block_transfers[(x >> 23) & 3] 270 #define insn_stkblktrans(x) insn_stack_block_transfers[(x >> 23) & 3] 271 #define op2_shift(x) op_shifts[(x >> 5) & 3] 272 #define insn_fparnd(x) insn_fpa_rounding[(x >> 5) & 0x03] 273 #define insn_fpaprec(x) insn_fpa_precision[(((x >> 18) & 2)|(x >> 7)) & 1] 274 #define insn_fpaprect(x) insn_fpa_precision[(((x >> 21) & 2)|(x >> 15)) & 1] 275 #define insn_fpaimm(x) insn_fpaconstants[x & 0x07] 276 277 /* Local prototypes */ 278 static void disasm_register_shift(const disasm_interface_t *di, u_int insn); 279 static void disasm_print_reglist(const disasm_interface_t *di, u_int insn); 280 static void disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, 281 u_int loc); 282 static void disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, 283 u_int loc); 284 static void disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, 285 u_int loc); 286 static u_int disassemble_readword(u_int address); 287 static void disassemble_printaddr(u_int address); 288 289 vm_offset_t 290 disasm(const disasm_interface_t *di, vm_offset_t loc, int altfmt) 291 { 292 const struct arm32_insn *i_ptr = arm32_i; 293 294 u_int insn; 295 int matchp; 296 int branch; 297 char* f_ptr; 298 int fmt; 299 300 fmt = 0; 301 matchp = 0; 302 insn = di->di_readword(loc); 303 304 /* di->di_printf("loc=%08x insn=%08x : ", loc, insn);*/ 305 306 while (i_ptr->name) { 307 if ((insn & i_ptr->mask) == i_ptr->pattern) { 308 matchp = 1; 309 break; 310 } 311 i_ptr++; 312 } 313 314 if (!matchp) { 315 di->di_printf("und%s\t%08x\n", insn_condition(insn), insn); 316 return(loc + INSN_SIZE); 317 } 318 319 /* If instruction forces condition code, don't print it. */ 320 if ((i_ptr->mask & 0xf0000000) == 0xf0000000) 321 di->di_printf("%s", i_ptr->name); 322 else 323 di->di_printf("%s%s", i_ptr->name, insn_condition(insn)); 324 325 f_ptr = i_ptr->format; 326 327 /* Insert tab if there are no instruction modifiers */ 328 329 if (*(f_ptr) < 'A' || *(f_ptr) > 'Z') { 330 ++fmt; 331 di->di_printf("\t"); 332 } 333 334 while (*f_ptr) { 335 switch (*f_ptr) { 336 /* 2 - print Operand 2 of a data processing instruction */ 337 case '2': 338 if (insn & 0x02000000) { 339 int rotate= ((insn >> 7) & 0x1e); 340 341 di->di_printf("#0x%08x", 342 (insn & 0xff) << (32 - rotate) | 343 (insn & 0xff) >> rotate); 344 } else { 345 disasm_register_shift(di, insn); 346 } 347 break; 348 /* d - destination register (bits 12-15) */ 349 case 'd': 350 di->di_printf("r%d", ((insn >> 12) & 0x0f)); 351 break; 352 /* D - insert 'p' if Rd is R15 */ 353 case 'D': 354 if (((insn >> 12) & 0x0f) == 15) 355 di->di_printf("p"); 356 break; 357 /* n - n register (bits 16-19) */ 358 case 'n': 359 di->di_printf("r%d", ((insn >> 16) & 0x0f)); 360 break; 361 /* s - s register (bits 8-11) */ 362 case 's': 363 di->di_printf("r%d", ((insn >> 8) & 0x0f)); 364 break; 365 /* o - indirect register rn (bits 16-19) (used by swap) */ 366 case 'o': 367 di->di_printf("[r%d]", ((insn >> 16) & 0x0f)); 368 break; 369 /* m - m register (bits 0-4) */ 370 case 'm': 371 di->di_printf("r%d", ((insn >> 0) & 0x0f)); 372 break; 373 /* a - address operand of ldr/str instruction */ 374 case 'a': 375 disasm_insn_ldrstr(di, insn, loc); 376 break; 377 /* e - address operand of ldrh/strh instruction */ 378 case 'e': 379 disasm_insn_ldrhstrh(di, insn, loc); 380 break; 381 /* l - register list for ldm/stm instruction */ 382 case 'l': 383 disasm_print_reglist(di, insn); 384 break; 385 /* f - 1st fp operand (register) (bits 12-14) */ 386 case 'f': 387 di->di_printf("f%d", (insn >> 12) & 7); 388 break; 389 /* g - 2nd fp operand (register) (bits 16-18) */ 390 case 'g': 391 di->di_printf("f%d", (insn >> 16) & 7); 392 break; 393 /* h - 3rd fp operand (register/immediate) (bits 0-4) */ 394 case 'h': 395 if (insn & (1 << 3)) 396 di->di_printf("#%s", insn_fpaimm(insn)); 397 else 398 di->di_printf("f%d", insn & 7); 399 break; 400 /* b - branch address */ 401 case 'b': 402 branch = ((insn << 2) & 0x03ffffff); 403 if (branch & 0x02000000) 404 branch |= 0xfc000000; 405 di->di_printaddr(loc + 8 + branch); 406 break; 407 /* t - blx address */ 408 case 't': 409 branch = ((insn << 2) & 0x03ffffff) | 410 (insn >> 23 & 0x00000002); 411 if (branch & 0x02000000) 412 branch |= 0xfc000000; 413 di->di_printaddr(loc + 8 + branch); 414 break; 415 /* X - block transfer type */ 416 case 'X': 417 di->di_printf("%s", insn_blktrans(insn)); 418 break; 419 /* Y - block transfer type (r13 base) */ 420 case 'Y': 421 di->di_printf("%s", insn_stkblktrans(insn)); 422 break; 423 /* c - comment field bits(0-23) */ 424 case 'c': 425 di->di_printf("0x%08x", (insn & 0x00ffffff)); 426 break; 427 /* k - breakpoint comment (bits 0-3, 8-19) */ 428 case 'k': 429 di->di_printf("0x%04x", 430 (insn & 0x000fff00) >> 4 | (insn & 0x0000000f)); 431 break; 432 /* p - saved or current status register */ 433 case 'p': 434 if (insn & 0x00400000) 435 di->di_printf("spsr"); 436 else 437 di->di_printf("cpsr"); 438 break; 439 /* F - PSR transfer fields */ 440 case 'F': 441 di->di_printf("_"); 442 if (insn & (1 << 16)) 443 di->di_printf("c"); 444 if (insn & (1 << 17)) 445 di->di_printf("x"); 446 if (insn & (1 << 18)) 447 di->di_printf("s"); 448 if (insn & (1 << 19)) 449 di->di_printf("f"); 450 break; 451 /* B - byte transfer flag */ 452 case 'B': 453 if (insn & 0x00400000) 454 di->di_printf("b"); 455 break; 456 /* L - co-processor transfer size */ 457 case 'L': 458 if (insn & (1 << 22)) 459 di->di_printf("l"); 460 break; 461 /* S - set status flag */ 462 case 'S': 463 if (insn & 0x00100000) 464 di->di_printf("s"); 465 break; 466 /* P - fp precision */ 467 case 'P': 468 di->di_printf("%s", insn_fpaprec(insn)); 469 break; 470 /* Q - fp precision (for ldf/stf) */ 471 case 'Q': 472 break; 473 /* R - fp rounding */ 474 case 'R': 475 di->di_printf("%s", insn_fparnd(insn)); 476 break; 477 /* W - writeback flag */ 478 case 'W': 479 if (insn & (1 << 21)) 480 di->di_printf("!"); 481 break; 482 /* # - co-processor number */ 483 case '#': 484 di->di_printf("p%d", (insn >> 8) & 0x0f); 485 break; 486 /* v - co-processor data transfer registers+addressing mode */ 487 case 'v': 488 disasm_insn_ldcstc(di, insn, loc); 489 break; 490 /* x - instruction in hex */ 491 case 'x': 492 di->di_printf("0x%08x", insn); 493 break; 494 /* y - co-processor data processing registers */ 495 case 'y': 496 di->di_printf("%d, ", (insn >> 20) & 0x0f); 497 498 di->di_printf("c%d, c%d, c%d", (insn >> 12) & 0x0f, 499 (insn >> 16) & 0x0f, insn & 0x0f); 500 501 di->di_printf(", %d", (insn >> 5) & 0x07); 502 break; 503 /* z - co-processor register transfer registers */ 504 case 'z': 505 di->di_printf("%d, ", (insn >> 21) & 0x07); 506 di->di_printf("r%d, c%d, c%d, %d", 507 (insn >> 12) & 0x0f, (insn >> 16) & 0x0f, 508 insn & 0x0f, (insn >> 5) & 0x07); 509 510 /* if (((insn >> 5) & 0x07) != 0) 511 di->di_printf(", %d", (insn >> 5) & 0x07);*/ 512 break; 513 default: 514 di->di_printf("[%c - unknown]", *f_ptr); 515 break; 516 } 517 if (*(f_ptr+1) >= 'A' && *(f_ptr+1) <= 'Z') 518 ++f_ptr; 519 else if (*(++f_ptr)) { 520 ++fmt; 521 if (fmt == 1) 522 di->di_printf("\t"); 523 else 524 di->di_printf(", "); 525 } 526 }; 527 528 di->di_printf("\n"); 529 530 return(loc + INSN_SIZE); 531 } 532 533 534 static void 535 disasm_register_shift(const disasm_interface_t *di, u_int insn) 536 { 537 di->di_printf("r%d", (insn & 0x0f)); 538 if ((insn & 0x00000ff0) == 0) 539 ; 540 else if ((insn & 0x00000ff0) == 0x00000060) 541 di->di_printf(", rrx"); 542 else { 543 if (insn & 0x10) 544 di->di_printf(", %s r%d", op2_shift(insn), 545 (insn >> 8) & 0x0f); 546 else 547 di->di_printf(", %s #%d", op2_shift(insn), 548 (insn >> 7) & 0x1f); 549 } 550 } 551 552 553 static void 554 disasm_print_reglist(const disasm_interface_t *di, u_int insn) 555 { 556 int loop; 557 int start; 558 int comma; 559 560 di->di_printf("{"); 561 start = -1; 562 comma = 0; 563 564 for (loop = 0; loop < 17; ++loop) { 565 if (start != -1) { 566 if (loop == 16 || !(insn & (1 << loop))) { 567 if (comma) 568 di->di_printf(", "); 569 else 570 comma = 1; 571 if (start == loop - 1) 572 di->di_printf("r%d", start); 573 else 574 di->di_printf("r%d-r%d", start, loop - 1); 575 start = -1; 576 } 577 } else { 578 if (insn & (1 << loop)) 579 start = loop; 580 } 581 } 582 di->di_printf("}"); 583 584 if (insn & (1 << 22)) 585 di->di_printf("^"); 586 } 587 588 static void 589 disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, u_int loc) 590 { 591 int offset; 592 593 offset = insn & 0xfff; 594 if ((insn & 0x032f0000) == 0x010f0000) { 595 /* rA = pc, immediate index */ 596 if (insn & 0x00800000) 597 loc += offset; 598 else 599 loc -= offset; 600 di->di_printaddr(loc + 8); 601 } else { 602 di->di_printf("[r%d", (insn >> 16) & 0x0f); 603 if ((insn & 0x03000fff) != 0x01000000) { 604 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); 605 if (!(insn & 0x00800000)) 606 di->di_printf("-"); 607 if (insn & (1 << 25)) 608 disasm_register_shift(di, insn); 609 else 610 di->di_printf("#0x%03x", offset); 611 } 612 if (insn & (1 << 24)) 613 di->di_printf("]"); 614 } 615 } 616 617 static void 618 disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, u_int loc) 619 { 620 int offset; 621 622 offset = ((insn & 0xf00) >> 4) | (insn & 0xf); 623 if ((insn & 0x004f0000) == 0x004f0000) { 624 /* rA = pc, immediate index */ 625 if (insn & 0x00800000) 626 loc += offset; 627 else 628 loc -= offset; 629 di->di_printaddr(loc + 8); 630 } else { 631 di->di_printf("[r%d", (insn >> 16) & 0x0f); 632 if ((insn & 0x01400f0f) != 0x01400000) { 633 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); 634 if (!(insn & 0x00800000)) 635 di->di_printf("-"); 636 if (insn & (1 << 22)) 637 di->di_printf("#0x%02x", offset); 638 else 639 di->di_printf("r%d", (insn & 0x0f)); 640 } 641 if (insn & (1 << 24)) 642 di->di_printf("]"); 643 } 644 } 645 646 static void 647 disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, u_int loc) 648 { 649 if (((insn >> 8) & 0xf) == 1) 650 di->di_printf("f%d, ", (insn >> 12) & 0x07); 651 else 652 di->di_printf("c%d, ", (insn >> 12) & 0x0f); 653 654 di->di_printf("[r%d", (insn >> 16) & 0x0f); 655 656 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); 657 658 if (!(insn & (1 << 23))) 659 di->di_printf("-"); 660 661 di->di_printf("#0x%03x", (insn & 0xff) << 2); 662 663 if (insn & (1 << 24)) 664 di->di_printf("]"); 665 666 if (insn & (1 << 21)) 667 di->di_printf("!"); 668 } 669 670 static u_int 671 disassemble_readword(u_int address) 672 { 673 return(*((u_int *)address)); 674 } 675 676 static void 677 disassemble_printaddr(u_int address) 678 { 679 printf("0x%08x", address); 680 } 681 682 static const disasm_interface_t disassemble_di = { 683 disassemble_readword, disassemble_printaddr, db_printf 684 }; 685 686 void 687 disassemble(u_int address) 688 { 689 690 (void)disasm(&disassemble_di, address, 0); 691 } 692 693 /* End of disassem.c */
Cache object: 1477076b02f30c97617199b15a39842d
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