The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/arm/arm/disassem.c

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    1 /*      $NetBSD: disassem.c,v 1.14 2003/03/27 16:58:36 mycroft Exp $    */
    2 
    3 /*-
    4  * SPDX-License-Identifier: BSD-4-Clause
    5  *
    6  * Copyright (c) 1996 Mark Brinicombe.
    7  * Copyright (c) 1996 Brini.
    8  *
    9  * All rights reserved.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *      This product includes software developed by Brini.
   22  * 4. The name of the company nor the name of the author may be used to
   23  *    endorse or promote products derived from this software without specific
   24  *    prior written permission.
   25  *
   26  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
   27  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
   28  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   29  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
   30  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   31  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
   32  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   36  * SUCH DAMAGE.
   37  *
   38  * RiscBSD kernel project
   39  *
   40  * db_disasm.c
   41  *
   42  * Kernel disassembler
   43  *
   44  * Created      : 10/02/96
   45  *
   46  * Structured after the sparc/sparc/db_disasm.c by David S. Miller &
   47  * Paul Kranenburg
   48  *
   49  * This code is not complete. Not all instructions are disassembled.
   50  */
   51 
   52 #include <sys/cdefs.h>
   53 __FBSDID("$FreeBSD$");
   54 #include <sys/param.h>
   55 
   56 #include <sys/systm.h>
   57 #include <machine/disassem.h>
   58 #include <machine/armreg.h>
   59 #include <ddb/ddb.h>
   60 
   61 /*
   62  * General instruction format
   63  *
   64  *      insn[cc][mod]   [operands]
   65  *
   66  * Those fields with an uppercase format code indicate that the field
   67  * follows directly after the instruction before the separator i.e.
   68  * they modify the instruction rather than just being an operand to
   69  * the instruction. The only exception is the writeback flag which
   70  * follows a operand.
   71  *
   72  *
   73  * 2 - print Operand 2 of a data processing instruction
   74  * d - destination register (bits 12-15)
   75  * n - n register (bits 16-19)
   76  * s - s register (bits 8-11)
   77  * o - indirect register rn (bits 16-19) (used by swap)
   78  * m - m register (bits 0-3)
   79  * a - address operand of ldr/str instruction
   80  * l - register list for ldm/stm instruction
   81  * f - 1st fp operand (register) (bits 12-14)
   82  * g - 2nd fp operand (register) (bits 16-18)
   83  * h - 3rd fp operand (register/immediate) (bits 0-4)
   84  * b - branch address
   85  * t - thumb branch address (bits 24, 0-23)
   86  * k - breakpoint comment (bits 0-3, 8-19)
   87  * X - block transfer type
   88  * Y - block transfer type (r13 base)
   89  * c - comment field bits(0-23)
   90  * p - saved or current status register
   91  * F - PSR transfer fields
   92  * D - destination-is-r15 (P) flag on TST, TEQ, CMP, CMN
   93  * L - co-processor transfer size
   94  * S - set status flag
   95  * P - fp precision
   96  * Q - fp precision (for ldf/stf)
   97  * R - fp rounding
   98  * v - co-processor data transfer registers + addressing mode
   99  * W - writeback flag
  100  * x - instruction in hex
  101  * # - co-processor number
  102  * y - co-processor data processing registers
  103  * z - co-processor register transfer registers
  104  */
  105 
  106 struct arm32_insn {
  107         u_int mask;
  108         u_int pattern;
  109         char* name;
  110         char* format;
  111 };
  112 
  113 static const struct arm32_insn arm32_i[] = {
  114     { 0x0fffffff, 0x0ff00000, "imb",    "c" },          /* Before swi */
  115     { 0x0fffffff, 0x0ff00001, "imbrange",       "c" },  /* Before swi */
  116     { 0x0f000000, 0x0f000000, "swi",    "c" },
  117     { 0xfe000000, 0xfa000000, "blx",    "t" },          /* Before b and bl */
  118     { 0x0f000000, 0x0a000000, "b",      "b" },
  119     { 0x0f000000, 0x0b000000, "bl",     "b" },
  120     { 0x0fe000f0, 0x00000090, "mul",    "Snms" },
  121     { 0x0fe000f0, 0x00200090, "mla",    "Snmsd" },
  122     { 0x0fe000f0, 0x00800090, "umull",  "Sdnms" },
  123     { 0x0fe000f0, 0x00c00090, "smull",  "Sdnms" },
  124     { 0x0fe000f0, 0x00a00090, "umlal",  "Sdnms" },
  125     { 0x0fe000f0, 0x00e00090, "smlal",  "Sdnms" },
  126     { 0x0d700000, 0x04200000, "strt",   "daW" },
  127     { 0x0d700000, 0x04300000, "ldrt",   "daW" },
  128     { 0x0d700000, 0x04600000, "strbt",  "daW" },
  129     { 0x0d700000, 0x04700000, "ldrbt",  "daW" },
  130     { 0x0c500000, 0x04000000, "str",    "daW" },
  131     { 0x0c500000, 0x04100000, "ldr",    "daW" },
  132     { 0x0c500000, 0x04400000, "strb",   "daW" },
  133     { 0x0c500000, 0x04500000, "ldrb",   "daW" },
  134     { 0x0fff0ff0, 0x06bf0fb0, "rev16",  "dm" },
  135     { 0xffffffff, 0xf57ff01f, "clrex",  "c" },
  136     { 0x0ff00ff0, 0x01800f90, "strex",  "dmo" },
  137     { 0x0ff00fff, 0x01900f9f, "ldrex",  "do" },
  138     { 0x0ff00ff0, 0x01a00f90, "strexd", "dmo" },
  139     { 0x0ff00fff, 0x01b00f9f, "ldrexd", "do" },
  140     { 0x0ff00ff0, 0x01c00f90, "strexb", "dmo" },
  141     { 0x0ff00fff, 0x01d00f9f, "ldrexb", "do" },
  142     { 0x0ff00ff0, 0x01e00f90, "strexh", "dmo" },
  143     { 0x0ff00fff, 0x01f00f9f, "ldrexh", "do" },
  144     { 0x0e1f0000, 0x080d0000, "stm",    "YnWl" },/* separate out r13 base */
  145     { 0x0e1f0000, 0x081d0000, "ldm",    "YnWl" },/* separate out r13 base */
  146     { 0x0e100000, 0x08000000, "stm",    "XnWl" },
  147     { 0x0e100000, 0x08100000, "ldm",    "XnWl" },
  148     { 0x0e1000f0, 0x00100090, "ldrb",   "de" },
  149     { 0x0e1000f0, 0x00000090, "strb",   "de" },
  150     { 0x0e1000f0, 0x001000d0, "ldrsb",  "de" },
  151     { 0x0e1000f0, 0x001000b0, "ldrh",   "de" },
  152     { 0x0e1000f0, 0x000000b0, "strh",   "de" },
  153     { 0x0e1000f0, 0x001000f0, "ldrsh",  "de" },
  154     { 0x0f200090, 0x00200090, "und",    "x" },  /* Before data processing */
  155     { 0x0e1000d0, 0x000000d0, "und",    "x" },  /* Before data processing */
  156     { 0x0ff00ff0, 0x01000090, "swp",    "dmo" },
  157     { 0x0ff00ff0, 0x01400090, "swpb",   "dmo" },
  158     { 0x0fbf0fff, 0x010f0000, "mrs",    "dp" }, /* Before data processing */
  159     { 0x0fb0fff0, 0x0120f000, "msr",    "pFm" },/* Before data processing */
  160     { 0x0fb0f000, 0x0320f000, "msr",    "pF2" },/* Before data processing */
  161     { 0x0ffffff0, 0x012fff10, "bx",     "m" },
  162     { 0x0fff0ff0, 0x016f0f10, "clz",    "dm" },
  163     { 0x0ffffff0, 0x012fff30, "blx",    "m" },
  164     { 0xfff000f0, 0xe1200070, "bkpt",   "k" },
  165     { 0x0de00000, 0x00000000, "and",    "Sdn2" },
  166     { 0x0de00000, 0x00200000, "eor",    "Sdn2" },
  167     { 0x0de00000, 0x00400000, "sub",    "Sdn2" },
  168     { 0x0de00000, 0x00600000, "rsb",    "Sdn2" },
  169     { 0x0de00000, 0x00800000, "add",    "Sdn2" },
  170     { 0x0de00000, 0x00a00000, "adc",    "Sdn2" },
  171     { 0x0de00000, 0x00c00000, "sbc",    "Sdn2" },
  172     { 0x0de00000, 0x00e00000, "rsc",    "Sdn2" },
  173     { 0x0df00000, 0x01100000, "tst",    "Dn2" },
  174     { 0x0df00000, 0x01300000, "teq",    "Dn2" },
  175     { 0x0de00000, 0x01400000, "cmp",    "Dn2" },
  176     { 0x0de00000, 0x01600000, "cmn",    "Dn2" },
  177     { 0x0de00000, 0x01800000, "orr",    "Sdn2" },
  178     { 0x0de00000, 0x01a00000, "mov",    "Sd2" },
  179     { 0x0de00000, 0x01c00000, "bic",    "Sdn2" },
  180     { 0x0de00000, 0x01e00000, "mvn",    "Sd2" },
  181     { 0x0ff08f10, 0x0e000100, "adf",    "PRfgh" },
  182     { 0x0ff08f10, 0x0e100100, "muf",    "PRfgh" },
  183     { 0x0ff08f10, 0x0e200100, "suf",    "PRfgh" },
  184     { 0x0ff08f10, 0x0e300100, "rsf",    "PRfgh" },
  185     { 0x0ff08f10, 0x0e400100, "dvf",    "PRfgh" },
  186     { 0x0ff08f10, 0x0e500100, "rdf",    "PRfgh" },
  187     { 0x0ff08f10, 0x0e600100, "pow",    "PRfgh" },
  188     { 0x0ff08f10, 0x0e700100, "rpw",    "PRfgh" },
  189     { 0x0ff08f10, 0x0e800100, "rmf",    "PRfgh" },
  190     { 0x0ff08f10, 0x0e900100, "fml",    "PRfgh" },
  191     { 0x0ff08f10, 0x0ea00100, "fdv",    "PRfgh" },
  192     { 0x0ff08f10, 0x0eb00100, "frd",    "PRfgh" },
  193     { 0x0ff08f10, 0x0ec00100, "pol",    "PRfgh" },
  194     { 0x0f008f10, 0x0e000100, "fpbop",  "PRfgh" },
  195     { 0x0ff08f10, 0x0e008100, "mvf",    "PRfh" },
  196     { 0x0ff08f10, 0x0e108100, "mnf",    "PRfh" },
  197     { 0x0ff08f10, 0x0e208100, "abs",    "PRfh" },
  198     { 0x0ff08f10, 0x0e308100, "rnd",    "PRfh" },
  199     { 0x0ff08f10, 0x0e408100, "sqt",    "PRfh" },
  200     { 0x0ff08f10, 0x0e508100, "log",    "PRfh" },
  201     { 0x0ff08f10, 0x0e608100, "lgn",    "PRfh" },
  202     { 0x0ff08f10, 0x0e708100, "exp",    "PRfh" },
  203     { 0x0ff08f10, 0x0e808100, "sin",    "PRfh" },
  204     { 0x0ff08f10, 0x0e908100, "cos",    "PRfh" },
  205     { 0x0ff08f10, 0x0ea08100, "tan",    "PRfh" },
  206     { 0x0ff08f10, 0x0eb08100, "asn",    "PRfh" },
  207     { 0x0ff08f10, 0x0ec08100, "acs",    "PRfh" },
  208     { 0x0ff08f10, 0x0ed08100, "atn",    "PRfh" },
  209     { 0x0f008f10, 0x0e008100, "fpuop",  "PRfh" },
  210     { 0x0e100f00, 0x0c000100, "stf",    "QLv" },
  211     { 0x0e100f00, 0x0c100100, "ldf",    "QLv" },
  212     { 0x0ff00f10, 0x0e000110, "flt",    "PRgd" },
  213     { 0x0ff00f10, 0x0e100110, "fix",    "PRdh" },
  214     { 0x0ff00f10, 0x0e200110, "wfs",    "d" },
  215     { 0x0ff00f10, 0x0e300110, "rfs",    "d" },
  216     { 0x0ff00f10, 0x0e400110, "wfc",    "d" },
  217     { 0x0ff00f10, 0x0e500110, "rfc",    "d" },
  218     { 0x0ff0ff10, 0x0e90f110, "cmf",    "PRgh" },
  219     { 0x0ff0ff10, 0x0eb0f110, "cnf",    "PRgh" },
  220     { 0x0ff0ff10, 0x0ed0f110, "cmfe",   "PRgh" },
  221     { 0x0ff0ff10, 0x0ef0f110, "cnfe",   "PRgh" },
  222     { 0xff100010, 0xfe000010, "mcr2",   "#z" },
  223     { 0x0f100010, 0x0e000010, "mcr",    "#z" },
  224     { 0xff100010, 0xfe100010, "mrc2",   "#z" },
  225     { 0x0f100010, 0x0e100010, "mrc",    "#z" },
  226     { 0xff000010, 0xfe000000, "cdp2",   "#y" },
  227     { 0x0f000010, 0x0e000000, "cdp",    "#y" },
  228     { 0xfe100090, 0xfc100000, "ldc2",   "L#v" },
  229     { 0x0e100090, 0x0c100000, "ldc",    "L#v" },
  230     { 0xfe100090, 0xfc000000, "stc2",   "L#v" },
  231     { 0x0e100090, 0x0c000000, "stc",    "L#v" },
  232     { 0x00000000, 0x00000000, NULL,     NULL }
  233 };
  234 
  235 static char const arm32_insn_conditions[][4] = {
  236         "eq", "ne", "cs", "cc",
  237         "mi", "pl", "vs", "vc",
  238         "hi", "ls", "ge", "lt",
  239         "gt", "le", "",   "nv"
  240 };
  241 
  242 static char const insn_block_transfers[][4] = {
  243         "da", "ia", "db", "ib"
  244 };
  245 
  246 static char const insn_stack_block_transfers[][4] = {
  247         "ed", "ea", "fd", "fa"
  248 };
  249 
  250 static char const op_shifts[][4] = {
  251         "lsl", "lsr", "asr", "ror"
  252 };
  253 
  254 static char const insn_fpa_rounding[][2] = {
  255         "", "p", "m", "z"
  256 };
  257 
  258 static char const insn_fpa_precision[][2] = {
  259         "s", "d", "e", "p"
  260 };
  261 
  262 static char const insn_fpaconstants[][8] = {
  263         "0.0", "1.0", "2.0", "3.0",
  264         "4.0", "5.0", "0.5", "10.0"
  265 };
  266 
  267 #define insn_condition(x)       arm32_insn_conditions[(x >> 28) & 0x0f]
  268 #define insn_blktrans(x)        insn_block_transfers[(x >> 23) & 3]
  269 #define insn_stkblktrans(x)     insn_stack_block_transfers[(x >> 23) & 3]
  270 #define op2_shift(x)            op_shifts[(x >> 5) & 3]
  271 #define insn_fparnd(x)          insn_fpa_rounding[(x >> 5) & 0x03]
  272 #define insn_fpaprec(x)         insn_fpa_precision[(((x >> 18) & 2)|(x >> 7)) & 1]
  273 #define insn_fpaprect(x)        insn_fpa_precision[(((x >> 21) & 2)|(x >> 15)) & 1]
  274 #define insn_fpaimm(x)          insn_fpaconstants[x & 0x07]
  275 
  276 /* Local prototypes */
  277 static void disasm_register_shift(const disasm_interface_t *di, u_int insn);
  278 static void disasm_print_reglist(const disasm_interface_t *di, u_int insn);
  279 static void disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn,
  280     u_int loc);
  281 static void disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn,
  282     u_int loc);
  283 static void disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn,
  284     u_int loc);
  285 static u_int disassemble_readword(u_int address);
  286 static void disassemble_printaddr(u_int address);
  287 
  288 vm_offset_t
  289 disasm(const disasm_interface_t *di, vm_offset_t loc, int altfmt)
  290 {
  291         const struct arm32_insn *i_ptr = arm32_i;
  292 
  293         u_int insn;
  294         int matchp;
  295         int branch;
  296         char* f_ptr;
  297         int fmt;
  298 
  299         fmt = 0;
  300         matchp = 0;
  301         insn = di->di_readword(loc);
  302 
  303 /*      di->di_printf("loc=%08x insn=%08x : ", loc, insn);*/
  304 
  305         while (i_ptr->name) {
  306                 if ((insn & i_ptr->mask) ==  i_ptr->pattern) {
  307                         matchp = 1;
  308                         break;
  309                 }
  310                 i_ptr++;
  311         }
  312 
  313         if (!matchp) {
  314                 di->di_printf("und%s\t%08x\n", insn_condition(insn), insn);
  315                 return(loc + INSN_SIZE);
  316         }
  317 
  318         /* If instruction forces condition code, don't print it. */
  319         if ((i_ptr->mask & 0xf0000000) == 0xf0000000)
  320                 di->di_printf("%s", i_ptr->name);
  321         else
  322                 di->di_printf("%s%s", i_ptr->name, insn_condition(insn));
  323 
  324         f_ptr = i_ptr->format;
  325 
  326         /* Insert tab if there are no instruction modifiers */
  327 
  328         if (*(f_ptr) < 'A' || *(f_ptr) > 'Z') {
  329                 ++fmt;
  330                 di->di_printf("\t");
  331         }
  332 
  333         while (*f_ptr) {
  334                 switch (*f_ptr) {
  335                 /* 2 - print Operand 2 of a data processing instruction */
  336                 case '2':
  337                         if (insn & 0x02000000) {
  338                                 int rotate= ((insn >> 7) & 0x1e);
  339 
  340                                 di->di_printf("#0x%08x",
  341                                               (insn & 0xff) << (32 - rotate) |
  342                                               (insn & 0xff) >> rotate);
  343                         } else {
  344                                 disasm_register_shift(di, insn);
  345                         }
  346                         break;
  347                 /* d - destination register (bits 12-15) */
  348                 case 'd':
  349                         di->di_printf("r%d", ((insn >> 12) & 0x0f));
  350                         break;
  351                 /* D - insert 'p' if Rd is R15 */
  352                 case 'D':
  353                         if (((insn >> 12) & 0x0f) == 15)
  354                                 di->di_printf("p");
  355                         break;
  356                 /* n - n register (bits 16-19) */
  357                 case 'n':
  358                         di->di_printf("r%d", ((insn >> 16) & 0x0f));
  359                         break;
  360                 /* s - s register (bits 8-11) */
  361                 case 's':
  362                         di->di_printf("r%d", ((insn >> 8) & 0x0f));
  363                         break;
  364                 /* o - indirect register rn (bits 16-19) (used by swap) */
  365                 case 'o':
  366                         di->di_printf("[r%d]", ((insn >> 16) & 0x0f));
  367                         break;
  368                 /* m - m register (bits 0-4) */
  369                 case 'm':
  370                         di->di_printf("r%d", ((insn >> 0) & 0x0f));
  371                         break;
  372                 /* a - address operand of ldr/str instruction */
  373                 case 'a':
  374                         disasm_insn_ldrstr(di, insn, loc);
  375                         break;
  376                 /* e - address operand of ldrh/strh instruction */
  377                 case 'e':
  378                         disasm_insn_ldrhstrh(di, insn, loc);
  379                         break;
  380                 /* l - register list for ldm/stm instruction */
  381                 case 'l':
  382                         disasm_print_reglist(di, insn);
  383                         break;
  384                 /* f - 1st fp operand (register) (bits 12-14) */
  385                 case 'f':
  386                         di->di_printf("f%d", (insn >> 12) & 7);
  387                         break;
  388                 /* g - 2nd fp operand (register) (bits 16-18) */
  389                 case 'g':
  390                         di->di_printf("f%d", (insn >> 16) & 7);
  391                         break;
  392                 /* h - 3rd fp operand (register/immediate) (bits 0-4) */
  393                 case 'h':
  394                         if (insn & (1 << 3))
  395                                 di->di_printf("#%s", insn_fpaimm(insn));
  396                         else
  397                                 di->di_printf("f%d", insn & 7);
  398                         break;
  399                 /* b - branch address */
  400                 case 'b':
  401                         branch = ((insn << 2) & 0x03ffffff);
  402                         if (branch & 0x02000000)
  403                                 branch |= 0xfc000000;
  404                         di->di_printaddr(loc + 8 + branch);
  405                         break;
  406                 /* t - blx address */
  407                 case 't':
  408                         branch = ((insn << 2) & 0x03ffffff) |
  409                             (insn >> 23 & 0x00000002);
  410                         if (branch & 0x02000000)
  411                                 branch |= 0xfc000000;
  412                         di->di_printaddr(loc + 8 + branch);
  413                         break;
  414                 /* X - block transfer type */
  415                 case 'X':
  416                         di->di_printf("%s", insn_blktrans(insn));
  417                         break;
  418                 /* Y - block transfer type (r13 base) */
  419                 case 'Y':
  420                         di->di_printf("%s", insn_stkblktrans(insn));
  421                         break;
  422                 /* c - comment field bits(0-23) */
  423                 case 'c':
  424                         di->di_printf("0x%08x", (insn & 0x00ffffff));
  425                         break;
  426                 /* k - breakpoint comment (bits 0-3, 8-19) */
  427                 case 'k':
  428                         di->di_printf("0x%04x",
  429                             (insn & 0x000fff00) >> 4 | (insn & 0x0000000f));
  430                         break;
  431                 /* p - saved or current status register */
  432                 case 'p':
  433                         if (insn & 0x00400000)
  434                                 di->di_printf("spsr");
  435                         else
  436                                 di->di_printf("cpsr");
  437                         break;
  438                 /* F - PSR transfer fields */
  439                 case 'F':
  440                         di->di_printf("_");
  441                         if (insn & (1 << 16))
  442                                 di->di_printf("c");
  443                         if (insn & (1 << 17))
  444                                 di->di_printf("x");
  445                         if (insn & (1 << 18))
  446                                 di->di_printf("s");
  447                         if (insn & (1 << 19))
  448                                 di->di_printf("f");
  449                         break;
  450                 /* B - byte transfer flag */
  451                 case 'B':
  452                         if (insn & 0x00400000)
  453                                 di->di_printf("b");
  454                         break;
  455                 /* L - co-processor transfer size */
  456                 case 'L':
  457                         if (insn & (1 << 22))
  458                                 di->di_printf("l");
  459                         break;
  460                 /* S - set status flag */
  461                 case 'S':
  462                         if (insn & 0x00100000)
  463                                 di->di_printf("s");
  464                         break;
  465                 /* P - fp precision */
  466                 case 'P':
  467                         di->di_printf("%s", insn_fpaprec(insn));
  468                         break;
  469                 /* Q - fp precision (for ldf/stf) */
  470                 case 'Q':
  471                         break;
  472                 /* R - fp rounding */
  473                 case 'R':
  474                         di->di_printf("%s", insn_fparnd(insn));
  475                         break;
  476                 /* W - writeback flag */
  477                 case 'W':
  478                         if (insn & (1 << 21))
  479                                 di->di_printf("!");
  480                         break;
  481                 /* # - co-processor number */
  482                 case '#':
  483                         di->di_printf("p%d", (insn >> 8) & 0x0f);
  484                         break;
  485                 /* v - co-processor data transfer registers+addressing mode */
  486                 case 'v':
  487                         disasm_insn_ldcstc(di, insn, loc);
  488                         break;
  489                 /* x - instruction in hex */
  490                 case 'x':
  491                         di->di_printf("0x%08x", insn);
  492                         break;
  493                 /* y - co-processor data processing registers */
  494                 case 'y':
  495                         di->di_printf("%d, ", (insn >> 20) & 0x0f);
  496 
  497                         di->di_printf("c%d, c%d, c%d", (insn >> 12) & 0x0f,
  498                             (insn >> 16) & 0x0f, insn & 0x0f);
  499 
  500                         di->di_printf(", %d", (insn >> 5) & 0x07);
  501                         break;
  502                 /* z - co-processor register transfer registers */
  503                 case 'z':
  504                         di->di_printf("%d, ", (insn >> 21) & 0x07);
  505                         di->di_printf("r%d, c%d, c%d, %d",
  506                             (insn >> 12) & 0x0f, (insn >> 16) & 0x0f,
  507                             insn & 0x0f, (insn >> 5) & 0x07);
  508 
  509 /*                      if (((insn >> 5) & 0x07) != 0)
  510                                 di->di_printf(", %d", (insn >> 5) & 0x07);*/
  511                         break;
  512                 default:
  513                         di->di_printf("[%c - unknown]", *f_ptr);
  514                         break;
  515                 }
  516                 if (*(f_ptr+1) >= 'A' && *(f_ptr+1) <= 'Z')
  517                         ++f_ptr;
  518                 else if (*(++f_ptr)) {
  519                         ++fmt;
  520                         if (fmt == 1)
  521                                 di->di_printf("\t");
  522                         else
  523                                 di->di_printf(", ");
  524                 }
  525         }
  526 
  527         di->di_printf("\n");
  528 
  529         return(loc + INSN_SIZE);
  530 }
  531 
  532 static void
  533 disasm_register_shift(const disasm_interface_t *di, u_int insn)
  534 {
  535         di->di_printf("r%d", (insn & 0x0f));
  536         if ((insn & 0x00000ff0) == 0)
  537                 ;
  538         else if ((insn & 0x00000ff0) == 0x00000060)
  539                 di->di_printf(", rrx");
  540         else {
  541                 if (insn & 0x10)
  542                         di->di_printf(", %s r%d", op2_shift(insn),
  543                             (insn >> 8) & 0x0f);
  544                 else
  545                         di->di_printf(", %s #%d", op2_shift(insn),
  546                             (insn >> 7) & 0x1f);
  547         }
  548 }
  549 
  550 static void
  551 disasm_print_reglist(const disasm_interface_t *di, u_int insn)
  552 {
  553         int loop;
  554         int start;
  555         int comma;
  556 
  557         di->di_printf("{");
  558         start = -1;
  559         comma = 0;
  560 
  561         for (loop = 0; loop < 17; ++loop) {
  562                 if (start != -1) {
  563                         if (loop == 16 || !(insn & (1 << loop))) {
  564                                 if (comma)
  565                                         di->di_printf(", ");
  566                                 else
  567                                         comma = 1;
  568                                 if (start == loop - 1)
  569                                         di->di_printf("r%d", start);
  570                                 else
  571                                         di->di_printf("r%d-r%d", start, loop - 1);
  572                                 start = -1;
  573                         }
  574                 } else {
  575                         if (insn & (1 << loop))
  576                                 start = loop;
  577                 }
  578         }
  579         di->di_printf("}");
  580 
  581         if (insn & (1 << 22))
  582                 di->di_printf("^");
  583 }
  584 
  585 static void
  586 disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, u_int loc)
  587 {
  588         int offset;
  589 
  590         offset = insn & 0xfff;
  591         if ((insn & 0x032f0000) == 0x010f0000) {
  592                 /* rA = pc, immediate index */
  593                 if (insn & 0x00800000)
  594                         loc += offset;
  595                 else
  596                         loc -= offset;
  597                 di->di_printaddr(loc + 8);
  598         } else {
  599                 di->di_printf("[r%d", (insn >> 16) & 0x0f);
  600                 if ((insn & 0x03000fff) != 0x01000000) {
  601                         di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]");
  602                         if (!(insn & 0x00800000))
  603                                 di->di_printf("-");
  604                         if (insn & (1 << 25))
  605                                 disasm_register_shift(di, insn);
  606                         else
  607                                 di->di_printf("#0x%03x", offset);
  608                 }
  609                 if (insn & (1 << 24))
  610                         di->di_printf("]");
  611         }
  612 }
  613 
  614 static void
  615 disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, u_int loc)
  616 {
  617         int offset;
  618 
  619         offset = ((insn & 0xf00) >> 4) | (insn & 0xf);
  620         if ((insn & 0x004f0000) == 0x004f0000) {
  621                 /* rA = pc, immediate index */
  622                 if (insn & 0x00800000)
  623                         loc += offset;
  624                 else
  625                         loc -= offset;
  626                 di->di_printaddr(loc + 8);
  627         } else {
  628                 di->di_printf("[r%d", (insn >> 16) & 0x0f);
  629                 if ((insn & 0x01400f0f) != 0x01400000) {
  630                         di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]");
  631                         if (!(insn & 0x00800000))
  632                                 di->di_printf("-");
  633                         if (insn & (1 << 22))
  634                                 di->di_printf("#0x%02x", offset);
  635                         else
  636                                 di->di_printf("r%d", (insn & 0x0f));
  637                 }
  638                 if (insn & (1 << 24))
  639                         di->di_printf("]");
  640         }
  641 }
  642 
  643 static void
  644 disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, u_int loc)
  645 {
  646         if (((insn >> 8) & 0xf) == 1)
  647                 di->di_printf("f%d, ", (insn >> 12) & 0x07);
  648         else
  649                 di->di_printf("c%d, ", (insn >> 12) & 0x0f);
  650 
  651         di->di_printf("[r%d", (insn >> 16) & 0x0f);
  652 
  653         di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]");
  654 
  655         if (!(insn & (1 << 23)))
  656                 di->di_printf("-");
  657 
  658         di->di_printf("#0x%03x", (insn & 0xff) << 2);
  659 
  660         if (insn & (1 << 24))
  661                 di->di_printf("]");
  662 
  663         if (insn & (1 << 21))
  664                 di->di_printf("!");
  665 }
  666 
  667 static u_int
  668 disassemble_readword(u_int address)
  669 {
  670         return(*((u_int *)address));
  671 }
  672 
  673 static void
  674 disassemble_printaddr(u_int address)
  675 {
  676         printf("0x%08x", address);
  677 }
  678 
  679 static const disasm_interface_t disassemble_di = {
  680         disassemble_readword, disassemble_printaddr, db_printf
  681 };
  682 
  683 void
  684 disassemble(u_int address)
  685 {
  686 
  687         (void)disasm(&disassemble_di, address, 0);
  688 }
  689 
  690 /* End of disassem.c */

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