The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/arm/arm/disassem.c

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    1 /*      $NetBSD: disassem.c,v 1.14 2003/03/27 16:58:36 mycroft Exp $    */
    2 
    3 /*-
    4  * Copyright (c) 1996 Mark Brinicombe.
    5  * Copyright (c) 1996 Brini.
    6  *
    7  * All rights reserved.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 3. All advertising materials mentioning features or use of this software
   18  *    must display the following acknowledgement:
   19  *      This product includes software developed by Brini.
   20  * 4. The name of the company nor the name of the author may be used to
   21  *    endorse or promote products derived from this software without specific
   22  *    prior written permission.
   23  *
   24  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
   25  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
   26  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   27  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
   28  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   29  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
   30  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   34  * SUCH DAMAGE.
   35  *
   36  * RiscBSD kernel project
   37  *
   38  * db_disasm.c
   39  *
   40  * Kernel disassembler
   41  *
   42  * Created      : 10/02/96
   43  *
   44  * Structured after the sparc/sparc/db_disasm.c by David S. Miller &
   45  * Paul Kranenburg
   46  *
   47  * This code is not complete. Not all instructions are disassembled.
   48  */
   49 
   50 #include <sys/cdefs.h>
   51 __FBSDID("$FreeBSD: releng/9.0/sys/arm/arm/disassem.c 139735 2005-01-05 21:58:49Z imp $");
   52 #include <sys/param.h>
   53 
   54 
   55 #include <sys/systm.h>
   56 #include <machine/disassem.h>
   57 #include <machine/armreg.h>
   58 #include <ddb/ddb.h>
   59 
   60 /*
   61  * General instruction format
   62  *
   63  *      insn[cc][mod]   [operands]
   64  *
   65  * Those fields with an uppercase format code indicate that the field
   66  * follows directly after the instruction before the separator i.e.
   67  * they modify the instruction rather than just being an operand to
   68  * the instruction. The only exception is the writeback flag which
   69  * follows a operand.
   70  *
   71  *
   72  * 2 - print Operand 2 of a data processing instruction
   73  * d - destination register (bits 12-15)
   74  * n - n register (bits 16-19)
   75  * s - s register (bits 8-11)
   76  * o - indirect register rn (bits 16-19) (used by swap)
   77  * m - m register (bits 0-3)
   78  * a - address operand of ldr/str instruction
   79  * l - register list for ldm/stm instruction
   80  * f - 1st fp operand (register) (bits 12-14)
   81  * g - 2nd fp operand (register) (bits 16-18)
   82  * h - 3rd fp operand (register/immediate) (bits 0-4)
   83  * b - branch address
   84  * t - thumb branch address (bits 24, 0-23)
   85  * k - breakpoint comment (bits 0-3, 8-19)
   86  * X - block transfer type
   87  * Y - block transfer type (r13 base)
   88  * c - comment field bits(0-23)
   89  * p - saved or current status register
   90  * F - PSR transfer fields
   91  * D - destination-is-r15 (P) flag on TST, TEQ, CMP, CMN
   92  * L - co-processor transfer size
   93  * S - set status flag
   94  * P - fp precision
   95  * Q - fp precision (for ldf/stf)
   96  * R - fp rounding
   97  * v - co-processor data transfer registers + addressing mode
   98  * W - writeback flag
   99  * x - instruction in hex
  100  * # - co-processor number
  101  * y - co-processor data processing registers
  102  * z - co-processor register transfer registers
  103  */
  104 
  105 struct arm32_insn {
  106         u_int mask;
  107         u_int pattern;
  108         char* name;
  109         char* format;
  110 };
  111 
  112 static const struct arm32_insn arm32_i[] = {
  113     { 0x0fffffff, 0x0ff00000, "imb",    "c" },          /* Before swi */
  114     { 0x0fffffff, 0x0ff00001, "imbrange",       "c" },  /* Before swi */
  115     { 0x0f000000, 0x0f000000, "swi",    "c" },
  116     { 0xfe000000, 0xfa000000, "blx",    "t" },          /* Before b and bl */
  117     { 0x0f000000, 0x0a000000, "b",      "b" },
  118     { 0x0f000000, 0x0b000000, "bl",     "b" },
  119     { 0x0fe000f0, 0x00000090, "mul",    "Snms" },
  120     { 0x0fe000f0, 0x00200090, "mla",    "Snmsd" },
  121     { 0x0fe000f0, 0x00800090, "umull",  "Sdnms" },
  122     { 0x0fe000f0, 0x00c00090, "smull",  "Sdnms" },
  123     { 0x0fe000f0, 0x00a00090, "umlal",  "Sdnms" },
  124     { 0x0fe000f0, 0x00e00090, "smlal",  "Sdnms" },
  125     { 0x0d700000, 0x04200000, "strt",   "daW" },
  126     { 0x0d700000, 0x04300000, "ldrt",   "daW" },
  127     { 0x0d700000, 0x04600000, "strbt",  "daW" },
  128     { 0x0d700000, 0x04700000, "ldrbt",  "daW" },
  129     { 0x0c500000, 0x04000000, "str",    "daW" },
  130     { 0x0c500000, 0x04100000, "ldr",    "daW" },
  131     { 0x0c500000, 0x04400000, "strb",   "daW" },
  132     { 0x0c500000, 0x04500000, "ldrb",   "daW" },
  133     { 0x0e1f0000, 0x080d0000, "stm",    "YnWl" },/* separate out r13 base */
  134     { 0x0e1f0000, 0x081d0000, "ldm",    "YnWl" },/* separate out r13 base */    
  135     { 0x0e100000, 0x08000000, "stm",    "XnWl" },
  136     { 0x0e100000, 0x08100000, "ldm",    "XnWl" },    
  137     { 0x0e1000f0, 0x00100090, "ldrb",   "de" },
  138     { 0x0e1000f0, 0x00000090, "strb",   "de" },
  139     { 0x0e1000f0, 0x001000d0, "ldrsb",  "de" },
  140     { 0x0e1000f0, 0x001000b0, "ldrh",   "de" },
  141     { 0x0e1000f0, 0x000000b0, "strh",   "de" },
  142     { 0x0e1000f0, 0x001000f0, "ldrsh",  "de" },
  143     { 0x0f200090, 0x00200090, "und",    "x" },  /* Before data processing */
  144     { 0x0e1000d0, 0x000000d0, "und",    "x" },  /* Before data processing */
  145     { 0x0ff00ff0, 0x01000090, "swp",    "dmo" },
  146     { 0x0ff00ff0, 0x01400090, "swpb",   "dmo" },
  147     { 0x0fbf0fff, 0x010f0000, "mrs",    "dp" }, /* Before data processing */
  148     { 0x0fb0fff0, 0x0120f000, "msr",    "pFm" },/* Before data processing */
  149     { 0x0fb0f000, 0x0320f000, "msr",    "pF2" },/* Before data processing */
  150     { 0x0ffffff0, 0x012fff10, "bx",     "m" },
  151     { 0x0fff0ff0, 0x016f0f10, "clz",    "dm" },
  152     { 0x0ffffff0, 0x012fff30, "blx",    "m" },
  153     { 0xfff000f0, 0xe1200070, "bkpt",   "k" },
  154     { 0x0de00000, 0x00000000, "and",    "Sdn2" },
  155     { 0x0de00000, 0x00200000, "eor",    "Sdn2" },
  156     { 0x0de00000, 0x00400000, "sub",    "Sdn2" },
  157     { 0x0de00000, 0x00600000, "rsb",    "Sdn2" },
  158     { 0x0de00000, 0x00800000, "add",    "Sdn2" },
  159     { 0x0de00000, 0x00a00000, "adc",    "Sdn2" },
  160     { 0x0de00000, 0x00c00000, "sbc",    "Sdn2" },
  161     { 0x0de00000, 0x00e00000, "rsc",    "Sdn2" },
  162     { 0x0df00000, 0x01100000, "tst",    "Dn2" },
  163     { 0x0df00000, 0x01300000, "teq",    "Dn2" },
  164     { 0x0de00000, 0x01400000, "cmp",    "Dn2" },
  165     { 0x0de00000, 0x01600000, "cmn",    "Dn2" },
  166     { 0x0de00000, 0x01800000, "orr",    "Sdn2" },
  167     { 0x0de00000, 0x01a00000, "mov",    "Sd2" },
  168     { 0x0de00000, 0x01c00000, "bic",    "Sdn2" },
  169     { 0x0de00000, 0x01e00000, "mvn",    "Sd2" },
  170     { 0x0ff08f10, 0x0e000100, "adf",    "PRfgh" },
  171     { 0x0ff08f10, 0x0e100100, "muf",    "PRfgh" },
  172     { 0x0ff08f10, 0x0e200100, "suf",    "PRfgh" },
  173     { 0x0ff08f10, 0x0e300100, "rsf",    "PRfgh" },
  174     { 0x0ff08f10, 0x0e400100, "dvf",    "PRfgh" },
  175     { 0x0ff08f10, 0x0e500100, "rdf",    "PRfgh" },
  176     { 0x0ff08f10, 0x0e600100, "pow",    "PRfgh" },
  177     { 0x0ff08f10, 0x0e700100, "rpw",    "PRfgh" },
  178     { 0x0ff08f10, 0x0e800100, "rmf",    "PRfgh" },
  179     { 0x0ff08f10, 0x0e900100, "fml",    "PRfgh" },
  180     { 0x0ff08f10, 0x0ea00100, "fdv",    "PRfgh" },
  181     { 0x0ff08f10, 0x0eb00100, "frd",    "PRfgh" },
  182     { 0x0ff08f10, 0x0ec00100, "pol",    "PRfgh" },
  183     { 0x0f008f10, 0x0e000100, "fpbop",  "PRfgh" },
  184     { 0x0ff08f10, 0x0e008100, "mvf",    "PRfh" },
  185     { 0x0ff08f10, 0x0e108100, "mnf",    "PRfh" },
  186     { 0x0ff08f10, 0x0e208100, "abs",    "PRfh" },
  187     { 0x0ff08f10, 0x0e308100, "rnd",    "PRfh" },
  188     { 0x0ff08f10, 0x0e408100, "sqt",    "PRfh" },
  189     { 0x0ff08f10, 0x0e508100, "log",    "PRfh" },
  190     { 0x0ff08f10, 0x0e608100, "lgn",    "PRfh" },
  191     { 0x0ff08f10, 0x0e708100, "exp",    "PRfh" },
  192     { 0x0ff08f10, 0x0e808100, "sin",    "PRfh" },
  193     { 0x0ff08f10, 0x0e908100, "cos",    "PRfh" },
  194     { 0x0ff08f10, 0x0ea08100, "tan",    "PRfh" },
  195     { 0x0ff08f10, 0x0eb08100, "asn",    "PRfh" },
  196     { 0x0ff08f10, 0x0ec08100, "acs",    "PRfh" },
  197     { 0x0ff08f10, 0x0ed08100, "atn",    "PRfh" },
  198     { 0x0f008f10, 0x0e008100, "fpuop",  "PRfh" },
  199     { 0x0e100f00, 0x0c000100, "stf",    "QLv" },
  200     { 0x0e100f00, 0x0c100100, "ldf",    "QLv" },
  201     { 0x0ff00f10, 0x0e000110, "flt",    "PRgd" },
  202     { 0x0ff00f10, 0x0e100110, "fix",    "PRdh" },
  203     { 0x0ff00f10, 0x0e200110, "wfs",    "d" },
  204     { 0x0ff00f10, 0x0e300110, "rfs",    "d" },
  205     { 0x0ff00f10, 0x0e400110, "wfc",    "d" },
  206     { 0x0ff00f10, 0x0e500110, "rfc",    "d" },
  207     { 0x0ff0ff10, 0x0e90f110, "cmf",    "PRgh" },
  208     { 0x0ff0ff10, 0x0eb0f110, "cnf",    "PRgh" },
  209     { 0x0ff0ff10, 0x0ed0f110, "cmfe",   "PRgh" },
  210     { 0x0ff0ff10, 0x0ef0f110, "cnfe",   "PRgh" },
  211     { 0xff100010, 0xfe000010, "mcr2",   "#z" },
  212     { 0x0f100010, 0x0e000010, "mcr",    "#z" },
  213     { 0xff100010, 0xfe100010, "mrc2",   "#z" },
  214     { 0x0f100010, 0x0e100010, "mrc",    "#z" },
  215     { 0xff000010, 0xfe000000, "cdp2",   "#y" },
  216     { 0x0f000010, 0x0e000000, "cdp",    "#y" },
  217     { 0xfe100090, 0xfc100000, "ldc2",   "L#v" },
  218     { 0x0e100090, 0x0c100000, "ldc",    "L#v" },
  219     { 0xfe100090, 0xfc000000, "stc2",   "L#v" },
  220     { 0x0e100090, 0x0c000000, "stc",    "L#v" },
  221     { 0x00000000, 0x00000000, NULL,     NULL }
  222 };
  223 
  224 static char const arm32_insn_conditions[][4] = {
  225         "eq", "ne", "cs", "cc",
  226         "mi", "pl", "vs", "vc",
  227         "hi", "ls", "ge", "lt",
  228         "gt", "le", "",   "nv"
  229 };
  230 
  231 static char const insn_block_transfers[][4] = {
  232         "da", "ia", "db", "ib"
  233 };
  234 
  235 static char const insn_stack_block_transfers[][4] = {
  236         "ed", "ea", "fd", "fa"
  237 };
  238 
  239 static char const op_shifts[][4] = {
  240         "lsl", "lsr", "asr", "ror"
  241 };
  242 
  243 static char const insn_fpa_rounding[][2] = {
  244         "", "p", "m", "z"
  245 };
  246 
  247 static char const insn_fpa_precision[][2] = {
  248         "s", "d", "e", "p"
  249 };
  250 
  251 static char const insn_fpaconstants[][8] = {
  252         "0.0", "1.0", "2.0", "3.0",
  253         "4.0", "5.0", "0.5", "10.0"
  254 };
  255 
  256 #define insn_condition(x)       arm32_insn_conditions[(x >> 28) & 0x0f]
  257 #define insn_blktrans(x)        insn_block_transfers[(x >> 23) & 3]
  258 #define insn_stkblktrans(x)     insn_stack_block_transfers[(x >> 23) & 3]
  259 #define op2_shift(x)            op_shifts[(x >> 5) & 3]
  260 #define insn_fparnd(x)          insn_fpa_rounding[(x >> 5) & 0x03]
  261 #define insn_fpaprec(x)         insn_fpa_precision[(((x >> 18) & 2)|(x >> 7)) & 1]
  262 #define insn_fpaprect(x)        insn_fpa_precision[(((x >> 21) & 2)|(x >> 15)) & 1]
  263 #define insn_fpaimm(x)          insn_fpaconstants[x & 0x07]
  264 
  265 /* Local prototypes */
  266 static void disasm_register_shift(const disasm_interface_t *di, u_int insn);
  267 static void disasm_print_reglist(const disasm_interface_t *di, u_int insn);
  268 static void disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn,
  269     u_int loc);
  270 static void disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn,
  271     u_int loc);
  272 static void disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn,
  273     u_int loc);
  274 static u_int disassemble_readword(u_int address);
  275 static void disassemble_printaddr(u_int address);
  276 
  277 vm_offset_t
  278 disasm(const disasm_interface_t *di, vm_offset_t loc, int altfmt)
  279 {
  280         struct arm32_insn *i_ptr = (struct arm32_insn *)&arm32_i;
  281 
  282         u_int insn;
  283         int matchp;
  284         int branch;
  285         char* f_ptr;
  286         int fmt;
  287 
  288         fmt = 0;
  289         matchp = 0;
  290         insn = di->di_readword(loc);
  291 
  292 /*      di->di_printf("loc=%08x insn=%08x : ", loc, insn);*/
  293 
  294         while (i_ptr->name) {
  295                 if ((insn & i_ptr->mask) ==  i_ptr->pattern) {
  296                         matchp = 1;
  297                         break;
  298                 }
  299                 i_ptr++;
  300         }
  301 
  302         if (!matchp) {
  303                 di->di_printf("und%s\t%08x\n", insn_condition(insn), insn);
  304                 return(loc + INSN_SIZE);
  305         }
  306 
  307         /* If instruction forces condition code, don't print it. */
  308         if ((i_ptr->mask & 0xf0000000) == 0xf0000000)
  309                 di->di_printf("%s", i_ptr->name);
  310         else
  311                 di->di_printf("%s%s", i_ptr->name, insn_condition(insn));
  312 
  313         f_ptr = i_ptr->format;
  314 
  315         /* Insert tab if there are no instruction modifiers */
  316 
  317         if (*(f_ptr) < 'A' || *(f_ptr) > 'Z') {
  318                 ++fmt;
  319                 di->di_printf("\t");
  320         }
  321 
  322         while (*f_ptr) {
  323                 switch (*f_ptr) {
  324                 /* 2 - print Operand 2 of a data processing instruction */
  325                 case '2':
  326                         if (insn & 0x02000000) {
  327                                 int rotate= ((insn >> 7) & 0x1e);
  328 
  329                                 di->di_printf("#0x%08x",
  330                                               (insn & 0xff) << (32 - rotate) |
  331                                               (insn & 0xff) >> rotate);
  332                         } else {  
  333                                 disasm_register_shift(di, insn);
  334                         }
  335                         break;
  336                 /* d - destination register (bits 12-15) */
  337                 case 'd':
  338                         di->di_printf("r%d", ((insn >> 12) & 0x0f));
  339                         break;
  340                 /* D - insert 'p' if Rd is R15 */
  341                 case 'D':
  342                         if (((insn >> 12) & 0x0f) == 15)
  343                                 di->di_printf("p");
  344                         break;
  345                 /* n - n register (bits 16-19) */
  346                 case 'n':
  347                         di->di_printf("r%d", ((insn >> 16) & 0x0f));
  348                         break;
  349                 /* s - s register (bits 8-11) */
  350                 case 's':
  351                         di->di_printf("r%d", ((insn >> 8) & 0x0f));
  352                         break;
  353                 /* o - indirect register rn (bits 16-19) (used by swap) */
  354                 case 'o':
  355                         di->di_printf("[r%d]", ((insn >> 16) & 0x0f));
  356                         break;
  357                 /* m - m register (bits 0-4) */
  358                 case 'm':
  359                         di->di_printf("r%d", ((insn >> 0) & 0x0f));
  360                         break;
  361                 /* a - address operand of ldr/str instruction */
  362                 case 'a':
  363                         disasm_insn_ldrstr(di, insn, loc);
  364                         break;
  365                 /* e - address operand of ldrh/strh instruction */
  366                 case 'e':
  367                         disasm_insn_ldrhstrh(di, insn, loc);
  368                         break;
  369                 /* l - register list for ldm/stm instruction */
  370                 case 'l':
  371                         disasm_print_reglist(di, insn);
  372                         break;
  373                 /* f - 1st fp operand (register) (bits 12-14) */
  374                 case 'f':
  375                         di->di_printf("f%d", (insn >> 12) & 7);
  376                         break;
  377                 /* g - 2nd fp operand (register) (bits 16-18) */
  378                 case 'g':
  379                         di->di_printf("f%d", (insn >> 16) & 7);
  380                         break;
  381                 /* h - 3rd fp operand (register/immediate) (bits 0-4) */
  382                 case 'h':
  383                         if (insn & (1 << 3))
  384                                 di->di_printf("#%s", insn_fpaimm(insn));
  385                         else
  386                                 di->di_printf("f%d", insn & 7);
  387                         break;
  388                 /* b - branch address */
  389                 case 'b':
  390                         branch = ((insn << 2) & 0x03ffffff);
  391                         if (branch & 0x02000000)
  392                                 branch |= 0xfc000000;
  393                         di->di_printaddr(loc + 8 + branch);
  394                         break;
  395                 /* t - blx address */
  396                 case 't':
  397                         branch = ((insn << 2) & 0x03ffffff) |
  398                             (insn >> 23 & 0x00000002);
  399                         if (branch & 0x02000000)
  400                                 branch |= 0xfc000000;
  401                         di->di_printaddr(loc + 8 + branch);
  402                         break;
  403                 /* X - block transfer type */
  404                 case 'X':
  405                         di->di_printf("%s", insn_blktrans(insn));
  406                         break;
  407                 /* Y - block transfer type (r13 base) */
  408                 case 'Y':
  409                         di->di_printf("%s", insn_stkblktrans(insn));
  410                         break;
  411                 /* c - comment field bits(0-23) */
  412                 case 'c':
  413                         di->di_printf("0x%08x", (insn & 0x00ffffff));
  414                         break;
  415                 /* k - breakpoint comment (bits 0-3, 8-19) */
  416                 case 'k':
  417                         di->di_printf("0x%04x",
  418                             (insn & 0x000fff00) >> 4 | (insn & 0x0000000f));
  419                         break;
  420                 /* p - saved or current status register */
  421                 case 'p':
  422                         if (insn & 0x00400000)
  423                                 di->di_printf("spsr");
  424                         else
  425                                 di->di_printf("cpsr");
  426                         break;
  427                 /* F - PSR transfer fields */
  428                 case 'F':
  429                         di->di_printf("_");
  430                         if (insn & (1 << 16))
  431                                 di->di_printf("c");
  432                         if (insn & (1 << 17))
  433                                 di->di_printf("x");
  434                         if (insn & (1 << 18))
  435                                 di->di_printf("s");
  436                         if (insn & (1 << 19))
  437                                 di->di_printf("f");
  438                         break;
  439                 /* B - byte transfer flag */
  440                 case 'B':
  441                         if (insn & 0x00400000)
  442                                 di->di_printf("b");
  443                         break;
  444                 /* L - co-processor transfer size */
  445                 case 'L':
  446                         if (insn & (1 << 22))
  447                                 di->di_printf("l");
  448                         break;
  449                 /* S - set status flag */
  450                 case 'S':
  451                         if (insn & 0x00100000)
  452                                 di->di_printf("s");
  453                         break;
  454                 /* P - fp precision */
  455                 case 'P':
  456                         di->di_printf("%s", insn_fpaprec(insn));
  457                         break;
  458                 /* Q - fp precision (for ldf/stf) */
  459                 case 'Q':
  460                         break;
  461                 /* R - fp rounding */
  462                 case 'R':
  463                         di->di_printf("%s", insn_fparnd(insn));
  464                         break;
  465                 /* W - writeback flag */
  466                 case 'W':
  467                         if (insn & (1 << 21))
  468                                 di->di_printf("!");
  469                         break;
  470                 /* # - co-processor number */
  471                 case '#':
  472                         di->di_printf("p%d", (insn >> 8) & 0x0f);
  473                         break;
  474                 /* v - co-processor data transfer registers+addressing mode */
  475                 case 'v':
  476                         disasm_insn_ldcstc(di, insn, loc);
  477                         break;
  478                 /* x - instruction in hex */
  479                 case 'x':
  480                         di->di_printf("0x%08x", insn);
  481                         break;
  482                 /* y - co-processor data processing registers */
  483                 case 'y':
  484                         di->di_printf("%d, ", (insn >> 20) & 0x0f);
  485 
  486                         di->di_printf("c%d, c%d, c%d", (insn >> 12) & 0x0f,
  487                             (insn >> 16) & 0x0f, insn & 0x0f);
  488 
  489                         di->di_printf(", %d", (insn >> 5) & 0x07);
  490                         break;
  491                 /* z - co-processor register transfer registers */
  492                 case 'z':
  493                         di->di_printf("%d, ", (insn >> 21) & 0x07);
  494                         di->di_printf("r%d, c%d, c%d, %d",
  495                             (insn >> 12) & 0x0f, (insn >> 16) & 0x0f,
  496                             insn & 0x0f, (insn >> 5) & 0x07);
  497 
  498 /*                      if (((insn >> 5) & 0x07) != 0)
  499                                 di->di_printf(", %d", (insn >> 5) & 0x07);*/
  500                         break;
  501                 default:
  502                         di->di_printf("[%c - unknown]", *f_ptr);
  503                         break;
  504                 }
  505                 if (*(f_ptr+1) >= 'A' && *(f_ptr+1) <= 'Z')
  506                         ++f_ptr;
  507                 else if (*(++f_ptr)) {
  508                         ++fmt;
  509                         if (fmt == 1)
  510                                 di->di_printf("\t");
  511                         else
  512                                 di->di_printf(", ");
  513                 }
  514         };
  515 
  516         di->di_printf("\n");
  517 
  518         return(loc + INSN_SIZE);
  519 }
  520 
  521 
  522 static void
  523 disasm_register_shift(const disasm_interface_t *di, u_int insn)
  524 {
  525         di->di_printf("r%d", (insn & 0x0f));
  526         if ((insn & 0x00000ff0) == 0)
  527                 ;
  528         else if ((insn & 0x00000ff0) == 0x00000060)
  529                 di->di_printf(", rrx");
  530         else {
  531                 if (insn & 0x10)
  532                         di->di_printf(", %s r%d", op2_shift(insn),
  533                             (insn >> 8) & 0x0f);
  534                 else
  535                         di->di_printf(", %s #%d", op2_shift(insn),
  536                             (insn >> 7) & 0x1f);
  537         }
  538 }
  539 
  540 
  541 static void
  542 disasm_print_reglist(const disasm_interface_t *di, u_int insn)
  543 {
  544         int loop;
  545         int start;
  546         int comma;
  547 
  548         di->di_printf("{");
  549         start = -1;
  550         comma = 0;
  551 
  552         for (loop = 0; loop < 17; ++loop) {
  553                 if (start != -1) {
  554                         if (loop == 16 || !(insn & (1 << loop))) {
  555                                 if (comma)
  556                                         di->di_printf(", ");
  557                                 else
  558                                         comma = 1;
  559                                 if (start == loop - 1)
  560                                         di->di_printf("r%d", start);
  561                                 else
  562                                         di->di_printf("r%d-r%d", start, loop - 1);
  563                                 start = -1;
  564                         }
  565                 } else {
  566                         if (insn & (1 << loop))
  567                                 start = loop;
  568                 }
  569         }
  570         di->di_printf("}");
  571 
  572         if (insn & (1 << 22))
  573                 di->di_printf("^");
  574 }
  575 
  576 static void
  577 disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, u_int loc)
  578 {
  579         int offset;
  580 
  581         offset = insn & 0xfff;
  582         if ((insn & 0x032f0000) == 0x010f0000) {
  583                 /* rA = pc, immediate index */
  584                 if (insn & 0x00800000)
  585                         loc += offset;
  586                 else
  587                         loc -= offset;
  588                 di->di_printaddr(loc + 8);
  589         } else {
  590                 di->di_printf("[r%d", (insn >> 16) & 0x0f);
  591                 if ((insn & 0x03000fff) != 0x01000000) {
  592                         di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]");
  593                         if (!(insn & 0x00800000))
  594                                 di->di_printf("-");
  595                         if (insn & (1 << 25))
  596                                 disasm_register_shift(di, insn);
  597                         else
  598                                 di->di_printf("#0x%03x", offset);
  599                 }
  600                 if (insn & (1 << 24))
  601                         di->di_printf("]");
  602         }
  603 }
  604 
  605 static void
  606 disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, u_int loc)
  607 {
  608         int offset;
  609 
  610         offset = ((insn & 0xf00) >> 4) | (insn & 0xf);
  611         if ((insn & 0x004f0000) == 0x004f0000) {
  612                 /* rA = pc, immediate index */
  613                 if (insn & 0x00800000)
  614                         loc += offset;
  615                 else
  616                         loc -= offset;
  617                 di->di_printaddr(loc + 8);
  618         } else {
  619                 di->di_printf("[r%d", (insn >> 16) & 0x0f);
  620                 if ((insn & 0x01400f0f) != 0x01400000) {
  621                         di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]");
  622                         if (!(insn & 0x00800000))
  623                                 di->di_printf("-");
  624                         if (insn & (1 << 22))
  625                                 di->di_printf("#0x%02x", offset);
  626                         else
  627                                 di->di_printf("r%d", (insn & 0x0f));
  628                 }
  629                 if (insn & (1 << 24))
  630                         di->di_printf("]");
  631         }
  632 }
  633 
  634 static void
  635 disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, u_int loc)
  636 {
  637         if (((insn >> 8) & 0xf) == 1)
  638                 di->di_printf("f%d, ", (insn >> 12) & 0x07);
  639         else
  640                 di->di_printf("c%d, ", (insn >> 12) & 0x0f);
  641 
  642         di->di_printf("[r%d", (insn >> 16) & 0x0f);
  643 
  644         di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]");
  645 
  646         if (!(insn & (1 << 23)))
  647                 di->di_printf("-");
  648 
  649         di->di_printf("#0x%03x", (insn & 0xff) << 2);
  650 
  651         if (insn & (1 << 24))
  652                 di->di_printf("]");
  653 
  654         if (insn & (1 << 21))
  655                 di->di_printf("!");
  656 }
  657 
  658 static u_int
  659 disassemble_readword(u_int address)
  660 {
  661         return(*((u_int *)address));
  662 }
  663 
  664 static void
  665 disassemble_printaddr(u_int address)
  666 {
  667         printf("0x%08x", address);
  668 }
  669 
  670 static const disasm_interface_t disassemble_di = {
  671         disassemble_readword, disassemble_printaddr, db_printf
  672 };
  673 
  674 void
  675 disassemble(u_int address)
  676 {
  677 
  678         (void)disasm(&disassemble_di, address, 0);
  679 }
  680 
  681 /* End of disassem.c */

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