Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/arm/elf_trampoline.c
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1 /*- 2 * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25 #include <sys/cdefs.h> 26 __FBSDID("$FreeBSD$"); 27 #include <machine/asm.h> 28 #include <sys/types.h> 29 #include <sys/elf32.h> 30 #include <sys/param.h> 31 #include <sys/inflate.h> 32 #include <machine/elf.h> 33 #include <machine/pte.h> 34 #include <machine/cpufunc.h> 35 #include <machine/armreg.h> 36 37 #include <stdlib.h> 38 39 #include "opt_global.h" 40 #include "opt_kernname.h" 41 42 extern char kernel_start[]; 43 extern char kernel_end[]; 44 45 extern void *_end; 46 47 void __start(void); 48 49 #define GZ_HEAD 0xa 50 51 #ifdef CPU_ARM7TDMI 52 #define cpu_idcache_wbinv_all arm7tdmi_cache_flushID 53 #elif defined(CPU_ARM8) 54 #define cpu_idcache_wbinv_all arm8_cache_purgeID 55 #elif defined(CPU_ARM9) 56 #define cpu_idcache_wbinv_all arm9_idcache_wbinv_all 57 #elif defined(CPU_ARM10) 58 #define cpu_idcache_wbinv_all arm10_idcache_wbinv_all 59 #elif defined(CPU_SA110) || defined(CPU_SA1110) || defined(CPU_SA1100) || \ 60 defined(CPU_IXP12X0) 61 #define cpu_idcache_wbinv_all sa1_cache_purgeID 62 #elif defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 63 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) 64 #define cpu_idcache_wbinv_all xscale_cache_purgeID 65 #endif 66 67 68 int arm_picache_size; 69 int arm_picache_line_size; 70 int arm_picache_ways; 71 72 int arm_pdcache_size; /* and unified */ 73 int arm_pdcache_line_size = 32; 74 int arm_pdcache_ways; 75 76 int arm_pcache_type; 77 int arm_pcache_unified; 78 79 int arm_dcache_align; 80 int arm_dcache_align_mask; 81 82 /* Additional cache information local to this file. Log2 of some of the 83 above numbers. */ 84 static int arm_dcache_l2_nsets; 85 static int arm_dcache_l2_assoc; 86 static int arm_dcache_l2_linesize; 87 88 89 int block_userspace_access = 0; 90 extern int arm9_dcache_sets_inc; 91 extern int arm9_dcache_sets_max; 92 extern int arm9_dcache_index_max; 93 extern int arm9_dcache_index_inc; 94 95 static __inline void * 96 memcpy(void *dst, const void *src, int len) 97 { 98 const char *s = src; 99 char *d = dst; 100 101 while (len) { 102 if (0 && len >= 4 && !((vm_offset_t)d & 3) && 103 !((vm_offset_t)s & 3)) { 104 *(uint32_t *)d = *(uint32_t *)s; 105 s += 4; 106 d += 4; 107 len -= 4; 108 } else { 109 *d++ = *s++; 110 len--; 111 } 112 } 113 return (dst); 114 } 115 116 static __inline void 117 bzero(void *addr, int count) 118 { 119 char *tmp = (char *)addr; 120 121 while (count > 0) { 122 if (count >= 4 && !((vm_offset_t)tmp & 3)) { 123 *(uint32_t *)tmp = 0; 124 tmp += 4; 125 count -= 4; 126 } else { 127 *tmp = 0; 128 tmp++; 129 count--; 130 } 131 } 132 } 133 134 static void arm9_setup(void); 135 136 void 137 _start(void) 138 { 139 int physaddr = KERNPHYSADDR; 140 int tmp1; 141 unsigned int sp = ((unsigned int)&_end & ~3) + 4; 142 #if defined(FLASHADDR) && defined(LOADERRAMADDR) 143 unsigned int pc; 144 145 __asm __volatile("adr %0, _start\n" 146 : "=r" (pc)); 147 if ((FLASHADDR > LOADERRAMADDR && pc >= FLASHADDR) || 148 (FLASHADDR < LOADERRAMADDR && pc < LOADERRAMADDR)) { 149 /* 150 * We're running from flash, so just copy the whole thing 151 * from flash to memory. 152 * This is far from optimal, we could do the relocation or 153 * the unzipping directly from flash to memory to avoid this 154 * needless copy, but it would require to know the flash 155 * physical address. 156 */ 157 unsigned int target_addr; 158 unsigned int tmp_sp; 159 160 target_addr = (unsigned int)&_start - PHYSADDR + LOADERRAMADDR; 161 tmp_sp = target_addr + 0x100000 + 162 (unsigned int)&_end - (unsigned int)&_start; 163 memcpy((char *)target_addr, (char *)pc, 164 (unsigned int)&_end - (unsigned int)&_start); 165 /* Temporary set the sp and jump to the new location. */ 166 __asm __volatile( 167 "mov sp, %1\n" 168 "mov pc, %0\n" 169 : : "r" (target_addr), "r" (tmp_sp)); 170 171 } 172 #endif 173 #ifdef KZIP 174 sp += KERNSIZE + 0x100; 175 sp &= ~(L1_TABLE_SIZE - 1); 176 sp += 2 * L1_TABLE_SIZE; 177 #endif 178 sp += 1024 * 1024; /* Should be enough for a stack */ 179 180 __asm __volatile("adr %0, 2f\n" 181 "bic %0, %0, #0xff000000\n" 182 "and %1, %1, #0xff000000\n" 183 "orr %0, %0, %1\n" 184 "mrc p15, 0, %1, c1, c0, 0\n" 185 "bic %1, %1, #1\n" /* Disable MMU */ 186 "orr %1, %1, #(4 | 8)\n" /* Add DC enable, 187 WBUF enable */ 188 "orr %1, %1, #0x1000\n" /* Add IC enable */ 189 "orr %1, %1, #(0x800)\n" /* BPRD enable */ 190 191 "mcr p15, 0, %1, c1, c0, 0\n" 192 "nop\n" 193 "nop\n" 194 "nop\n" 195 "mov pc, %0\n" 196 "2: nop\n" 197 "mov sp, %2\n" 198 : "=r" (tmp1), "+r" (physaddr), "+r" (sp)); 199 #ifndef KZIP 200 #ifdef CPU_ARM9 201 /* So that idcache_wbinv works; */ 202 if ((cpufunc_id() & 0x0000f000) == 0x00009000) 203 arm9_setup(); 204 #endif 205 cpu_idcache_wbinv_all(); 206 #endif 207 __start(); 208 } 209 210 static void 211 get_cachetype_cp15() 212 { 213 u_int ctype, isize, dsize; 214 u_int multiplier; 215 216 __asm __volatile("mrc p15, 0, %0, c0, c0, 1" 217 : "=r" (ctype)); 218 219 /* 220 * ...and thus spake the ARM ARM: 221 * 222 * If an <opcode2> value corresponding to an unimplemented or 223 * reserved ID register is encountered, the System Control 224 * processor returns the value of the main ID register. 225 */ 226 if (ctype == cpufunc_id()) 227 goto out; 228 229 if ((ctype & CPU_CT_S) == 0) 230 arm_pcache_unified = 1; 231 232 /* 233 * If you want to know how this code works, go read the ARM ARM. 234 */ 235 236 arm_pcache_type = CPU_CT_CTYPE(ctype); 237 if (arm_pcache_unified == 0) { 238 isize = CPU_CT_ISIZE(ctype); 239 multiplier = (isize & CPU_CT_xSIZE_M) ? 3 : 2; 240 arm_picache_line_size = 1U << (CPU_CT_xSIZE_LEN(isize) + 3); 241 if (CPU_CT_xSIZE_ASSOC(isize) == 0) { 242 if (isize & CPU_CT_xSIZE_M) 243 arm_picache_line_size = 0; /* not present */ 244 else 245 arm_picache_ways = 1; 246 } else { 247 arm_picache_ways = multiplier << 248 (CPU_CT_xSIZE_ASSOC(isize) - 1); 249 } 250 arm_picache_size = multiplier << (CPU_CT_xSIZE_SIZE(isize) + 8); 251 } 252 253 dsize = CPU_CT_DSIZE(ctype); 254 multiplier = (dsize & CPU_CT_xSIZE_M) ? 3 : 2; 255 arm_pdcache_line_size = 1U << (CPU_CT_xSIZE_LEN(dsize) + 3); 256 if (CPU_CT_xSIZE_ASSOC(dsize) == 0) { 257 if (dsize & CPU_CT_xSIZE_M) 258 arm_pdcache_line_size = 0; /* not present */ 259 else 260 arm_pdcache_ways = 1; 261 } else { 262 arm_pdcache_ways = multiplier << 263 (CPU_CT_xSIZE_ASSOC(dsize) - 1); 264 } 265 arm_pdcache_size = multiplier << (CPU_CT_xSIZE_SIZE(dsize) + 8); 266 267 arm_dcache_align = arm_pdcache_line_size; 268 269 arm_dcache_l2_assoc = CPU_CT_xSIZE_ASSOC(dsize) + multiplier - 2; 270 arm_dcache_l2_linesize = CPU_CT_xSIZE_LEN(dsize) + 3; 271 arm_dcache_l2_nsets = 6 + CPU_CT_xSIZE_SIZE(dsize) - 272 CPU_CT_xSIZE_ASSOC(dsize) - CPU_CT_xSIZE_LEN(dsize); 273 out: 274 arm_dcache_align_mask = arm_dcache_align - 1; 275 } 276 277 static void 278 arm9_setup(void) 279 { 280 281 get_cachetype_cp15(); 282 arm9_dcache_sets_inc = 1U << arm_dcache_l2_linesize; 283 arm9_dcache_sets_max = (1U << (arm_dcache_l2_linesize + 284 arm_dcache_l2_nsets)) - arm9_dcache_sets_inc; 285 arm9_dcache_index_inc = 1U << (32 - arm_dcache_l2_assoc); 286 arm9_dcache_index_max = 0U - arm9_dcache_index_inc; 287 } 288 289 290 #ifdef KZIP 291 static unsigned char *orig_input, *i_input, *i_output; 292 293 294 static u_int memcnt; /* Memory allocated: blocks */ 295 static size_t memtot; /* Memory allocated: bytes */ 296 /* 297 * Library functions required by inflate(). 298 */ 299 300 #define MEMSIZ 0x8000 301 302 /* 303 * Allocate memory block. 304 */ 305 unsigned char * 306 kzipmalloc(int size) 307 { 308 void *ptr; 309 static u_char mem[MEMSIZ]; 310 311 if (memtot + size > MEMSIZ) 312 return NULL; 313 ptr = mem + memtot; 314 memtot += size; 315 memcnt++; 316 return ptr; 317 } 318 319 /* 320 * Free allocated memory block. 321 */ 322 void 323 kzipfree(void *ptr) 324 { 325 memcnt--; 326 if (!memcnt) 327 memtot = 0; 328 } 329 330 void 331 putstr(char *dummy) 332 { 333 } 334 335 static int 336 input(void *dummy) 337 { 338 if ((size_t)(i_input - orig_input) >= KERNCOMPSIZE) { 339 return (GZ_EOF); 340 } 341 return *i_input++; 342 } 343 344 static int 345 output(void *dummy, unsigned char *ptr, unsigned long len) 346 { 347 348 349 memcpy(i_output, ptr, len); 350 i_output += len; 351 return (0); 352 } 353 354 static void * 355 inflate_kernel(void *kernel, void *startaddr) 356 { 357 struct inflate infl; 358 char slide[GZ_WSIZE]; 359 360 orig_input = kernel; 361 memcnt = memtot = 0; 362 i_input = (char *)kernel + GZ_HEAD; 363 if (((char *)kernel)[3] & 0x18) { 364 while (*i_input) 365 i_input++; 366 i_input++; 367 } 368 i_output = startaddr; 369 bzero(&infl, sizeof(infl)); 370 infl.gz_input = input; 371 infl.gz_output = output; 372 infl.gz_slide = slide; 373 inflate(&infl); 374 return ((char *)(((vm_offset_t)i_output & ~3) + 4)); 375 } 376 377 #endif 378 379 void * 380 load_kernel(unsigned int kstart, unsigned int curaddr,unsigned int func_end, 381 int d) 382 { 383 Elf32_Ehdr *eh; 384 Elf32_Phdr phdr[64] /* XXX */, *php; 385 Elf32_Shdr shdr[64] /* XXX */; 386 int i,j; 387 void *entry_point; 388 int symtabindex = -1; 389 int symstrindex = -1; 390 vm_offset_t lastaddr = 0; 391 Elf_Addr ssym = 0, esym = 0; 392 Elf_Dyn *dp; 393 394 eh = (Elf32_Ehdr *)kstart; 395 ssym = esym = 0; 396 entry_point = (void*)eh->e_entry; 397 memcpy(phdr, (void *)(kstart + eh->e_phoff ), 398 eh->e_phnum * sizeof(phdr[0])); 399 400 /* Determine lastaddr. */ 401 for (i = 0; i < eh->e_phnum; i++) { 402 if (lastaddr < (phdr[i].p_vaddr - KERNVIRTADDR + curaddr 403 + phdr[i].p_memsz)) 404 lastaddr = phdr[i].p_vaddr - KERNVIRTADDR + 405 curaddr + phdr[i].p_memsz; 406 } 407 408 /* Save the symbol tables, as there're about to be scratched. */ 409 memcpy(shdr, (void *)(kstart + eh->e_shoff), 410 sizeof(*shdr) * eh->e_shnum); 411 if (eh->e_shnum * eh->e_shentsize != 0 && 412 eh->e_shoff != 0) { 413 for (i = 0; i < eh->e_shnum; i++) { 414 if (shdr[i].sh_type == SHT_SYMTAB) { 415 for (j = 0; j < eh->e_phnum; j++) { 416 if (phdr[j].p_type == PT_LOAD && 417 shdr[i].sh_offset >= 418 phdr[j].p_offset && 419 (shdr[i].sh_offset + 420 shdr[i].sh_size <= 421 phdr[j].p_offset + 422 phdr[j].p_filesz)) { 423 shdr[i].sh_offset = 0; 424 shdr[i].sh_size = 0; 425 j = eh->e_phnum; 426 } 427 } 428 if (shdr[i].sh_offset != 0 && 429 shdr[i].sh_size != 0) { 430 symtabindex = i; 431 symstrindex = shdr[i].sh_link; 432 } 433 } 434 } 435 func_end = roundup(func_end, sizeof(long)); 436 if (symtabindex >= 0 && symstrindex >= 0) { 437 ssym = lastaddr; 438 if (d) { 439 memcpy((void *)func_end, (void *)( 440 shdr[symtabindex].sh_offset + kstart), 441 shdr[symtabindex].sh_size); 442 memcpy((void *)(func_end + 443 shdr[symtabindex].sh_size), 444 (void *)(shdr[symstrindex].sh_offset + 445 kstart), shdr[symstrindex].sh_size); 446 } else { 447 lastaddr += shdr[symtabindex].sh_size; 448 lastaddr = roundup(lastaddr, 449 sizeof(shdr[symtabindex].sh_size)); 450 lastaddr += sizeof(shdr[symstrindex].sh_size); 451 lastaddr += shdr[symstrindex].sh_size; 452 lastaddr = roundup(lastaddr, 453 sizeof(shdr[symstrindex].sh_size)); 454 } 455 456 } 457 } 458 if (!d) 459 return ((void *)lastaddr); 460 461 j = eh->e_phnum; 462 for (i = 0; i < j; i++) { 463 volatile char c; 464 465 if (phdr[i].p_type != PT_LOAD) 466 continue; 467 memcpy((void *)(phdr[i].p_vaddr - KERNVIRTADDR + curaddr), 468 (void*)(kstart + phdr[i].p_offset), phdr[i].p_filesz); 469 /* Clean space from oversized segments, eg: bss. */ 470 if (phdr[i].p_filesz < phdr[i].p_memsz) 471 bzero((void *)(phdr[i].p_vaddr - KERNVIRTADDR + 472 curaddr + phdr[i].p_filesz), phdr[i].p_memsz - 473 phdr[i].p_filesz); 474 } 475 /* Now grab the symbol tables. */ 476 if (symtabindex >= 0 && symstrindex >= 0) { 477 *(Elf_Size *)lastaddr = 478 shdr[symtabindex].sh_size; 479 lastaddr += sizeof(shdr[symtabindex].sh_size); 480 memcpy((void*)lastaddr, 481 (void *)func_end, 482 shdr[symtabindex].sh_size); 483 lastaddr += shdr[symtabindex].sh_size; 484 lastaddr = roundup(lastaddr, 485 sizeof(shdr[symtabindex].sh_size)); 486 *(Elf_Size *)lastaddr = 487 shdr[symstrindex].sh_size; 488 lastaddr += sizeof(shdr[symstrindex].sh_size); 489 memcpy((void*)lastaddr, 490 (void*)(func_end + 491 shdr[symtabindex].sh_size), 492 shdr[symstrindex].sh_size); 493 lastaddr += shdr[symstrindex].sh_size; 494 lastaddr = roundup(lastaddr, 495 sizeof(shdr[symstrindex].sh_size)); 496 *(Elf_Addr *)curaddr = MAGIC_TRAMP_NUMBER; 497 *((Elf_Addr *)curaddr + 1) = ssym - curaddr + KERNVIRTADDR; 498 *((Elf_Addr *)curaddr + 2) = lastaddr - curaddr + KERNVIRTADDR; 499 } else 500 *(Elf_Addr *)curaddr = 0; 501 /* Invalidate the instruction cache. */ 502 __asm __volatile("mcr p15, 0, %0, c7, c5, 0\n" 503 "mcr p15, 0, %0, c7, c10, 4\n" 504 : : "r" (curaddr)); 505 __asm __volatile("mrc p15, 0, %0, c1, c0, 0\n" 506 "bic %0, %0, #1\n" /* MMU_ENABLE */ 507 "mcr p15, 0, %0, c1, c0, 0\n" 508 : "=r" (ssym)); 509 /* Jump to the entry point. */ 510 ((void(*)(void))(entry_point - KERNVIRTADDR + curaddr))(); 511 __asm __volatile(".globl func_end\n" 512 "func_end:"); 513 514 } 515 516 extern char func_end[]; 517 518 519 #define PMAP_DOMAIN_KERNEL 15 /* 520 * Just define it instead of including the 521 * whole VM headers set. 522 */ 523 int __hack; 524 static __inline void 525 setup_pagetables(unsigned int pt_addr, vm_paddr_t physstart, vm_paddr_t physend, 526 int write_back) 527 { 528 unsigned int *pd = (unsigned int *)pt_addr; 529 vm_paddr_t addr; 530 int domain = (DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT; 531 int tmp; 532 533 bzero(pd, L1_TABLE_SIZE); 534 for (addr = physstart; addr < physend; addr += L1_S_SIZE) { 535 pd[addr >> L1_S_SHIFT] = L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)| 536 L1_S_DOM(PMAP_DOMAIN_KERNEL) | addr; 537 if (write_back) 538 pd[addr >> L1_S_SHIFT] |= L1_S_B; 539 } 540 /* XXX: See below */ 541 if (0xfff00000 < physstart || 0xfff00000 > physend) 542 pd[0xfff00000 >> L1_S_SHIFT] = L1_TYPE_S|L1_S_AP(AP_KRW)| 543 L1_S_DOM(PMAP_DOMAIN_KERNEL)|physstart; 544 __asm __volatile("mcr p15, 0, %1, c2, c0, 0\n" /* set TTB */ 545 "mcr p15, 0, %1, c8, c7, 0\n" /* Flush TTB */ 546 "mcr p15, 0, %2, c3, c0, 0\n" /* Set DAR */ 547 "mrc p15, 0, %0, c1, c0, 0\n" 548 "orr %0, %0, #1\n" /* MMU_ENABLE */ 549 "mcr p15, 0, %0, c1, c0, 0\n" 550 "mrc p15, 0, %0, c2, c0, 0\n" /* CPWAIT */ 551 "mov r0, r0\n" 552 "sub pc, pc, #4\n" : 553 "=r" (tmp) : "r" (pd), "r" (domain)); 554 555 /* 556 * XXX: This is the most stupid workaround I've ever wrote. 557 * For some reason, the KB9202 won't boot the kernel unless 558 * we access an address which is not in the 559 * 0x20000000 - 0x20ffffff range. I hope I'll understand 560 * what's going on later. 561 */ 562 __hack = *(volatile int *)0xfffff21c; 563 } 564 565 void 566 __start(void) 567 { 568 void *curaddr; 569 void *dst, *altdst; 570 char *kernel = (char *)&kernel_start; 571 int sp; 572 int pt_addr; 573 574 __asm __volatile("mov %0, pc" : 575 "=r" (curaddr)); 576 curaddr = (void*)((unsigned int)curaddr & 0xfff00000); 577 #ifdef KZIP 578 if (*kernel == 0x1f && kernel[1] == 0x8b) { 579 pt_addr = (((int)&_end + KERNSIZE + 0x100) & 580 ~(L1_TABLE_SIZE - 1)) + L1_TABLE_SIZE; 581 582 #ifdef CPU_ARM9 583 /* So that idcache_wbinv works; */ 584 if ((cpufunc_id() & 0x0000f000) == 0x00009000) 585 arm9_setup(); 586 #endif 587 setup_pagetables(pt_addr, (vm_paddr_t)curaddr, 588 (vm_paddr_t)curaddr + 0x10000000, 1); 589 /* Gzipped kernel */ 590 dst = inflate_kernel(kernel, &_end); 591 kernel = (char *)&_end; 592 altdst = 4 + load_kernel((unsigned int)kernel, 593 (unsigned int)curaddr, 594 (unsigned int)&func_end , 0); 595 if (altdst > dst) 596 dst = altdst; 597 cpu_idcache_wbinv_all(); 598 __asm __volatile("mrc p15, 0, %0, c1, c0, 0\n" 599 "bic %0, %0, #1\n" /* MMU_ENABLE */ 600 "mcr p15, 0, %0, c1, c0, 0\n" 601 : "=r" (pt_addr)); 602 } else 603 #endif 604 dst = 4 + load_kernel((unsigned int)&kernel_start, 605 (unsigned int)curaddr, 606 (unsigned int)&func_end, 0); 607 dst = (void *)(((vm_offset_t)dst & ~3)); 608 pt_addr = ((unsigned int)dst &~(L1_TABLE_SIZE - 1)) + L1_TABLE_SIZE; 609 setup_pagetables(pt_addr, (vm_paddr_t)curaddr, 610 (vm_paddr_t)curaddr + 0x10000000, 0); 611 sp = pt_addr + L1_TABLE_SIZE + 8192; 612 sp = sp &~3; 613 dst = (void *)(sp + 4); 614 memcpy((void *)dst, (void *)&load_kernel, (unsigned int)&func_end - 615 (unsigned int)&load_kernel); 616 do_call(dst, kernel, dst + (unsigned int)(&func_end) - 617 (unsigned int)(&load_kernel), sp); 618 }
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