The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/arm/exception.S

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    1 /*      $NetBSD: exception.S,v 1.13 2003/10/31 16:30:15 scw Exp $       */
    2 
    3 /*-
    4  * Copyright (c) 1994-1997 Mark Brinicombe.
    5  * Copyright (c) 1994 Brini.
    6  * All rights reserved.
    7  *
    8  * This code is derived from software written for Brini by Mark Brinicombe
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *      This product includes software developed by Brini.
   21  * 4. The name of the company nor the name of the author may be used to
   22  *    endorse or promote products derived from this software without specific
   23  *    prior written permission.
   24  *
   25  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
   26  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
   27  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   28  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
   29  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   30  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
   31  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   32  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   33  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   34  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   35  * SUCH DAMAGE.
   36  *
   37  * RiscBSD kernel project
   38  *
   39  * exception.S
   40  *
   41  * Low level handlers for exception vectors
   42  *
   43  * Created      : 24/09/94
   44  *
   45  * Based on kate/display/abort.s
   46  *
   47  */
   48 
   49 #include "assym.s"
   50 
   51 #include <machine/asm.h>
   52 #include <machine/armreg.h>
   53 #include <machine/asmacros.h>
   54 __FBSDID("$FreeBSD: releng/10.0/sys/arm/arm/exception.S 253985 2013-08-06 10:03:44Z andrew $");
   55 
   56         .text   
   57         .align  0
   58 
   59 AST_LOCALS
   60 
   61 /*
   62  * reset_entry:
   63  *
   64  *      Handler for Reset exception.
   65  */
   66 ASENTRY_NP(reset_entry)
   67         adr     r0, Lreset_panicmsg
   68         bl      _C_LABEL(panic)
   69         /* NOTREACHED */
   70 Lreset_panicmsg:
   71         .asciz  "Reset vector called, LR = 0x%08x"
   72         .balign 4
   73 END(reset_entry)
   74 
   75 /*
   76  * swi_entry
   77  *
   78  *      Handler for the Software Interrupt exception.
   79  */
   80 ASENTRY_NP(swi_entry)
   81         STOP_UNWINDING                  /* Don't unwind past here */
   82 
   83         PUSHFRAME
   84 
   85         mov     r0, sp                  /* Pass the frame to any function */
   86         bl      _C_LABEL(swi_handler)   /* It's a SWI ! */
   87 
   88         DO_AST
   89         PULLFRAME
   90         movs    pc, lr                  /* Exit */
   91 END(swi_entry)
   92 
   93 /*
   94  * prefetch_abort_entry:
   95  *
   96  *      Handler for the Prefetch Abort exception.
   97  */
   98 ASENTRY_NP(prefetch_abort_entry)
   99 #ifdef __XSCALE__
  100         nop                             /* Make absolutely sure any pending */
  101         nop                             /* imprecise aborts have occurred. */
  102 #endif
  103         sub     lr, lr, #0x00000004     /* Adjust the lr */
  104 
  105         PUSHFRAMEINSVC
  106         ldr     r1, Lprefetch_abort_handler_address
  107         adr     lr, exception_exit
  108         mov     r0, sp                  /* pass the stack pointer as r0 */
  109         ldr     pc, [r1]
  110 
  111 Lprefetch_abort_handler_address:
  112         .word   _C_LABEL(prefetch_abort_handler_address)
  113 
  114         .data
  115         .global _C_LABEL(prefetch_abort_handler_address)
  116 
  117 _C_LABEL(prefetch_abort_handler_address):
  118         .word   abortprefetch
  119 
  120         .text
  121 abortprefetch:
  122         adr     r0, abortprefetchmsg
  123         b       _C_LABEL(panic)
  124 
  125 abortprefetchmsg:
  126         .asciz  "abortprefetch"
  127         .align  0
  128 END(prefetch_abort_entry)
  129 
  130 /*
  131  * data_abort_entry:
  132  *
  133  *      Handler for the Data Abort exception.
  134  */
  135 ASENTRY_NP(data_abort_entry)
  136 #ifdef __XSCALE__
  137         nop                             /* Make absolutely sure any pending */
  138         nop                             /* imprecise aborts have occurred. */
  139 #endif
  140 
  141         sub     lr, lr, #0x00000008     /* Adjust the lr */
  142         PUSHFRAMEINSVC                  /* Push trap frame and switch */
  143                                         /* to SVC32 mode */
  144         ldr     r1, Ldata_abort_handler_address
  145         adr     lr, exception_exit
  146         mov     r0, sp                  /* pass the stack pointer as r0 */
  147         ldr     pc, [r1]
  148 Ldata_abort_handler_address:
  149         .word   _C_LABEL(data_abort_handler_address)
  150 
  151         .data
  152         .global _C_LABEL(data_abort_handler_address)
  153 _C_LABEL(data_abort_handler_address):
  154         .word   abortdata
  155 
  156         .text
  157 abortdata:
  158         adr     r0, abortdatamsg
  159         b       _C_LABEL(panic)
  160 
  161 abortdatamsg:
  162         .asciz  "abortdata"
  163         .align  0
  164 END(data_abort_entry)
  165 
  166 /*
  167  * address_exception_entry:
  168  *
  169  *      Handler for the Address Exception exception.
  170  *
  171  *      NOTE: This exception isn't really used on arm32.  We
  172  *      print a warning message to the console and then treat
  173  *      it like a Data Abort.
  174  */
  175 ASENTRY_NP(address_exception_entry)
  176         mrs     r1, cpsr_all
  177         mrs     r2, spsr_all
  178         mov     r3, lr
  179         adr     r0, Laddress_exception_msg
  180         bl      _C_LABEL(printf)        /* XXX CLOBBERS LR!! */
  181         b       data_abort_entry
  182 Laddress_exception_msg:
  183         .asciz  "Address Exception CPSR=0x%08x SPSR=0x%08x LR=0x%08x\n"
  184         .balign 4
  185 END(address_exception_entry)
  186 
  187 /*
  188  * General exception exit handler
  189  * (Placed here to be within range of all the references to it)
  190  *
  191  * It exits straight away if not returning to USR mode.
  192  * This loops around delivering any pending ASTs.
  193  * Interrupts are disabled at suitable points to avoid ASTs
  194  * being posted between testing and exit to user mode.
  195  *
  196  * This function uses PULLFRAMEFROMSVCANDEXIT and DO_AST and can
  197  * only be called if the exception handler used PUSHFRAMEINSVC.
  198  *
  199  * For EABI, don't try to unwind any further than this.  This is a
  200  * stopgap measure to avoid getting stuck in a loop in the unwinder,
  201  * which happens because we don't yet provide the proper unwind info
  202  * here that describes which registers are being restored.
  203  */
  204 
  205 ASENTRY_NP(exception_exit)
  206         UNWINDSVCFRAME
  207         DO_AST
  208         PULLFRAMEFROMSVCANDEXIT
  209 END(exception_exit)
  210 
  211 /*
  212  * undefined_entry:
  213  *
  214  *      Handler for the Undefined Instruction exception.
  215  *
  216  *      We indirect the undefined vector via the handler address
  217  *      in the data area.  Entry to the undefined handler must
  218  *      look like direct entry from the vector.
  219  */
  220 ASENTRY_NP(undefined_entry)
  221         stmfd   sp!, {r0, r1}
  222         ldr     r0, Lundefined_handler_indirection
  223         ldr     r1, [sp], #0x0004
  224         str     r1, [r0, #0x0000]
  225         ldr     r1, [sp], #0x0004
  226         str     r1, [r0, #0x0004]
  227         ldmia   r0, {r0, r1, pc}
  228 
  229 
  230 Lundefined_handler_indirection:
  231         .word   Lundefined_handler_indirection_data
  232 END(undefined_entry)
  233 
  234 /*
  235  * assembly bounce code for calling the kernel
  236  * undefined instruction handler. This uses
  237  * a standard trap frame and is called in SVC mode.
  238  */
  239 
  240 ENTRY_NP(undefinedinstruction_bounce)
  241         PUSHFRAMEINSVC
  242 
  243         mov     r0, sp
  244         adr     lr, exception_exit
  245         b       _C_LABEL(undefinedinstruction)
  246 
  247         .data
  248         .align  0
  249 
  250 /*
  251  * Indirection data
  252  * 2 words use for preserving r0 and r1
  253  * 3rd word contains the undefined handler address.
  254  */
  255 
  256 Lundefined_handler_indirection_data:
  257         .word   0
  258         .word   0
  259 
  260         .global _C_LABEL(undefined_handler_address)
  261 _C_LABEL(undefined_handler_address):
  262         .word   _C_LABEL(undefinedinstruction_bounce)
  263 END(undefinedinstruction_bounce)

Cache object: a9d7b5d9664c37ba2a9de821212d2497


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