Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/arm/exception.S
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1 /* $NetBSD: exception.S,v 1.13 2003/10/31 16:30:15 scw Exp $ */ 2 3 /*- 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * exception.S 40 * 41 * Low level handlers for exception vectors 42 * 43 * Created : 24/09/94 44 * 45 * Based on kate/display/abort.s 46 * 47 */ 48 49 #include "assym.s" 50 51 #include <machine/asm.h> 52 #include <machine/armreg.h> 53 #include <machine/asmacros.h> 54 __FBSDID("$FreeBSD$"); 55 56 .text 57 .align 2 58 59 /* 60 * ASM macros for pushing and pulling trapframes from the stack 61 * 62 * These macros are used to handle the irqframe and trapframe structures 63 * defined above. 64 */ 65 66 /* 67 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 68 * Since the current mode is used, the SVC lr field is not defined. 69 * 70 * NOTE: r13 and r14 are stored separately as a work around for the 71 * SA110 rev 2 STM^ bug 72 */ 73 #ifdef ARM_TP_ADDRESS 74 #define PUSHFRAME \ 75 sub sp, sp, #4; /* Align the stack */ \ 76 str lr, [sp, #-4]!; /* Push the return address */ \ 77 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ 78 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 79 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 80 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 81 mov r0, r0; /* NOP for previous instruction */ \ 82 mrs r0, spsr; /* Put the SPSR on the stack */ \ 83 str r0, [sp, #-4]!; \ 84 ldr r0, =ARM_RAS_START; \ 85 mov r1, #0; \ 86 str r1, [r0]; \ 87 mov r1, #0xffffffff; \ 88 str r1, [r0, #4]; 89 #else 90 #define PUSHFRAME \ 91 sub sp, sp, #4; /* Align the stack */ \ 92 str lr, [sp, #-4]!; /* Push the return address */ \ 93 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ 94 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 95 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 96 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 97 mov r0, r0; /* NOP for previous instruction */ \ 98 mrs r0, spsr; /* Put the SPSR on the stack */ \ 99 str r0, [sp, #-4]!; 100 #endif 101 102 /* 103 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 104 * Since the current mode is used, the SVC lr field is ignored. 105 */ 106 107 #ifdef ARM_TP_ADDRESS 108 #define PULLFRAME \ 109 ldr r0, [sp], #4; /* Get the SPSR from stack */ \ 110 msr spsr_fsxc, r0; \ 111 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 112 mov r0, r0; /* NOP for previous instruction */ \ 113 add sp, sp, #(4*17); /* Adjust the stack pointer */ \ 114 ldr lr, [sp], #4; /* Pull the return address */ \ 115 add sp, sp, #4 /* Align the stack */ 116 #else 117 #define PULLFRAME \ 118 ldr r0, [sp], #4 ; /* Get the SPSR from stack */ \ 119 msr spsr_fsxc, r0; \ 120 clrex; \ 121 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 122 mov r0, r0; /* NOP for previous instruction */ \ 123 add sp, sp, #(4*17); /* Adjust the stack pointer */ \ 124 ldr lr, [sp], #4; /* Pull the return address */ \ 125 add sp, sp, #4 /* Align the stack */ 126 #endif 127 128 /* 129 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 130 * This should only be used if the processor is not currently in SVC32 131 * mode. The processor mode is switched to SVC mode and the trap frame is 132 * stored. The SVC lr field is used to store the previous value of 133 * lr in SVC mode. 134 * 135 * NOTE: r13 and r14 are stored separately as a work around for the 136 * SA110 rev 2 STM^ bug 137 */ 138 #ifdef ARM_TP_ADDRESS 139 #define PUSHFRAMEINSVC \ 140 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 141 mov r0, lr; /* Save xxx32 r14 */ \ 142 mov r1, sp; /* Save xxx32 sp */ \ 143 mrs r3, spsr; /* Save xxx32 spsr */ \ 144 mrs r2, cpsr; /* Get the CPSR */ \ 145 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \ 146 orr r2, r2, #(PSR_SVC32_MODE); \ 147 msr cpsr_c, r2; /* Punch into SVC mode */ \ 148 mov r2, sp; /* Save SVC sp */ \ 149 bic sp, sp, #7; /* Align sp to an 8-byte addrress */ \ 150 sub sp, sp, #4; /* Pad trapframe to keep alignment */ \ 151 str r0, [sp, #-4]!; /* Push return address */ \ 152 str lr, [sp, #-4]!; /* Push SVC lr */ \ 153 str r2, [sp, #-4]!; /* Push SVC sp */ \ 154 msr spsr_fsxc, r3; /* Restore correct spsr */ \ 155 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 156 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ 157 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 158 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 159 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 160 mov r0, r0; /* NOP for previous instruction */ \ 161 ldr r5, =ARM_RAS_START; /* Check if there's any RAS */ \ 162 ldr r4, [r5, #4]; /* reset it to point at the */ \ 163 cmp r4, #0xffffffff; /* end of memory if necessary; */ \ 164 movne r1, #0xffffffff; /* leave value in r4 for later */ \ 165 strne r1, [r5, #4]; /* comparision against PC. */ \ 166 ldr r3, [r5]; /* Retrieve global RAS_START */ \ 167 cmp r3, #0; /* and reset it if non-zero. */ \ 168 movne r1, #0; /* If non-zero RAS_START and */ \ 169 strne r1, [r5]; /* PC was lower than RAS_END, */ \ 170 ldrne r1, [r0, #16]; /* adjust the saved PC so that */ \ 171 cmpne r4, r1; /* execution later resumes at */ \ 172 strhi r3, [r0, #16]; /* the RAS_START location. */ \ 173 mrs r0, spsr; \ 174 str r0, [sp, #-4]! 175 #else 176 #define PUSHFRAMEINSVC \ 177 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 178 mov r0, lr; /* Save xxx32 r14 */ \ 179 mov r1, sp; /* Save xxx32 sp */ \ 180 mrs r3, spsr; /* Save xxx32 spsr */ \ 181 mrs r2, cpsr; /* Get the CPSR */ \ 182 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \ 183 orr r2, r2, #(PSR_SVC32_MODE); \ 184 msr cpsr_c, r2; /* Punch into SVC mode */ \ 185 mov r2, sp; /* Save SVC sp */ \ 186 bic sp, sp, #7; /* Align sp to an 8-byte addrress */ \ 187 sub sp, sp, #4; /* Pad trapframe to keep alignment */ \ 188 str r0, [sp, #-4]!; /* Push return address */ \ 189 str lr, [sp, #-4]!; /* Push SVC lr */ \ 190 str r2, [sp, #-4]!; /* Push SVC sp */ \ 191 msr spsr_fsxc, r3; /* Restore correct spsr */ \ 192 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 193 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ 194 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 195 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 196 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 197 mov r0, r0; /* NOP for previous instruction */ \ 198 mrs r0, spsr; /* Put the SPSR on the stack */ \ 199 str r0, [sp, #-4]! 200 #endif 201 202 /* 203 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 204 * in SVC32 mode and restore the saved processor mode and PC. 205 * This should be used when the SVC lr register needs to be restored on 206 * exit. 207 */ 208 209 #ifdef ARM_TP_ADDRESS 210 #define PULLFRAMEFROMSVCANDEXIT \ 211 ldr r0, [sp], #4; /* Get the SPSR from stack */ \ 212 msr spsr_fsxc, r0; /* restore SPSR */ \ 213 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 214 mov r0, r0; /* NOP for previous instruction */ \ 215 add sp, sp, #(4*15); /* Adjust the stack pointer */ \ 216 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 217 #else 218 #define PULLFRAMEFROMSVCANDEXIT \ 219 ldr r0, [sp], #4; /* Get the SPSR from stack */ \ 220 msr spsr_fsxc, r0; /* restore SPSR */ \ 221 clrex; \ 222 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 223 mov r0, r0; /* NOP for previous instruction */ \ 224 add sp, sp, #(4*15); /* Adjust the stack pointer */ \ 225 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 226 #endif 227 228 #if defined(__ARM_EABI__) 229 /* 230 * Unwind hints so we can unwind past functions that use 231 * PULLFRAMEFROMSVCANDEXIT. They are run in reverse order. 232 * As the last thing we do is restore the stack pointer 233 * we can ignore the padding at the end of struct trapframe. 234 */ 235 #define UNWINDSVCFRAME \ 236 .save {r13-r15}; /* Restore sp, lr, pc */ \ 237 .pad #(2*4); /* Skip user sp and lr */ \ 238 .save {r0-r12}; /* Restore r0-r12 */ \ 239 .pad #(4) /* Skip spsr */ 240 #else 241 #define UNWINDSVCFRAME 242 #endif 243 244 #define DO_AST \ 245 ldr r0, [sp]; /* Get the SPSR from stack */ \ 246 mrs r4, cpsr; /* save CPSR */ \ 247 orr r1, r4, #(PSR_I|PSR_F); \ 248 msr cpsr_c, r1; /* Disable interrupts */ \ 249 and r0, r0, #(PSR_MODE); /* Returning to USR mode? */ \ 250 teq r0, #(PSR_USR32_MODE); \ 251 bne 2f; /* Nope, get out now */ \ 252 bic r4, r4, #(PSR_I|PSR_F); \ 253 1: GET_CURTHREAD_PTR(r5); \ 254 ldr r1, [r5, #(TD_FLAGS)]; \ 255 and r1, r1, #(TDF_ASTPENDING|TDF_NEEDRESCHED); \ 256 teq r1, #0; \ 257 beq 2f; /* Nope. Just bail */ \ 258 msr cpsr_c, r4; /* Restore interrupts */ \ 259 mov r0, sp; \ 260 bl _C_LABEL(ast); /* ast(frame) */ \ 261 orr r0, r4, #(PSR_I|PSR_F); \ 262 msr cpsr_c, r0; \ 263 b 1b; \ 264 2: 265 266 267 /* 268 * Entry point for a Software Interrupt (SWI). 269 * 270 * The hardware switches to svc32 mode on a swi, so we're already on the 271 * right stack; just build a trapframe and call the handler. 272 */ 273 ASENTRY_NP(swi_entry) 274 PUSHFRAME /* Build the trapframe on the */ 275 mov r0, sp /* scv32 stack, pass it to the */ 276 bl _C_LABEL(swi_handler) /* swi handler. */ 277 /* 278 * The fork_trampoline() code in swtch.S aranges for the MI fork_exit() 279 * to return to swi_exit here, to return to userland. The net effect is 280 * that a newly created thread appears to return from a SWI just like 281 * the parent thread that created it. 282 */ 283 ASEENTRY_NP(swi_exit) 284 DO_AST /* Handle pending signals. */ 285 PULLFRAME /* Deallocate trapframe. */ 286 movs pc, lr /* Return to userland. */ 287 STOP_UNWINDING /* Don't unwind into user mode. */ 288 EEND(swi_exit) 289 END(swi_entry) 290 291 /* 292 * Standard exception exit handler. 293 * 294 * This is used to return from all exceptions except SWI. It uses DO_AST and 295 * PULLFRAMEFROMSVCANDEXIT and can only be called if the exception entry code 296 * used PUSHFRAMEINSVC. 297 * 298 * If the return is to user mode, this uses DO_AST to deliver any pending 299 * signals and/or handle TDF_NEEDRESCHED first. 300 */ 301 ASENTRY_NP(exception_exit) 302 DO_AST /* Handle pending signals. */ 303 PULLFRAMEFROMSVCANDEXIT /* Return. */ 304 UNWINDSVCFRAME /* Special unwinding for exceptions. */ 305 END(exception_exit) 306 307 /* 308 * Entry point for a Prefetch Abort exception. 309 * 310 * The hardware switches to the abort mode stack; we switch to svc32 before 311 * calling the handler, then return directly to the original mode/stack 312 * on exit (without transitioning back through the abort mode stack). 313 */ 314 ASENTRY_NP(prefetch_abort_entry) 315 #ifdef __XSCALE__ 316 nop /* Make absolutely sure any pending */ 317 nop /* imprecise aborts have occurred. */ 318 #endif 319 sub lr, lr, #4 /* Adjust the lr. Transition to scv32 */ 320 PUSHFRAMEINSVC /* mode stack, build trapframe there. */ 321 adr lr, exception_exit /* Return from handler via standard */ 322 mov r0, sp /* exception exit routine. Pass the */ 323 mov r1, #1 /* Type flag */ 324 b _C_LABEL(abort_handler) 325 END(prefetch_abort_entry) 326 327 /* 328 * Entry point for a Data Abort exception. 329 * 330 * The hardware switches to the abort mode stack; we switch to svc32 before 331 * calling the handler, then return directly to the original mode/stack 332 * on exit (without transitioning back through the abort mode stack). 333 */ 334 ASENTRY_NP(data_abort_entry) 335 #ifdef __XSCALE__ 336 nop /* Make absolutely sure any pending */ 337 nop /* imprecise aborts have occurred. */ 338 #endif 339 sub lr, lr, #8 /* Adjust the lr. Transition to scv32 */ 340 PUSHFRAMEINSVC /* mode stack, build trapframe there. */ 341 adr lr, exception_exit /* Exception exit routine */ 342 mov r0, sp /* Trapframe to the handler */ 343 mov r1, #0 /* Type flag */ 344 b _C_LABEL(abort_handler) 345 END(data_abort_entry) 346 347 /* 348 * Entry point for an Undefined Instruction exception. 349 * 350 * The hardware switches to the undefined mode stack; we switch to svc32 before 351 * calling the handler, then return directly to the original mode/stack 352 * on exit (without transitioning back through the undefined mode stack). 353 */ 354 ASENTRY_NP(undefined_entry) 355 sub lr, lr, #4 /* Adjust the lr. Transition to scv32 */ 356 PUSHFRAMEINSVC /* mode stack, build trapframe there. */ 357 adr lr, exception_exit /* Return from handler via standard */ 358 mov r0, sp /* exception exit routine. Pass the */ 359 b undefinedinstruction /* trapframe to the handler. */ 360 END(undefined_entry) 361 362 /* 363 * Entry point for a normal IRQ. 364 * 365 * The hardware switches to the IRQ mode stack; we switch to svc32 before 366 * calling the handler, then return directly to the original mode/stack 367 * on exit (without transitioning back through the IRQ mode stack). 368 */ 369 ASENTRY_NP(irq_entry) 370 sub lr, lr, #4 /* Adjust the lr. Transition to scv32 */ 371 PUSHFRAMEINSVC /* mode stack, build trapframe there. */ 372 adr lr, exception_exit /* Return from handler via standard */ 373 mov r0, sp /* exception exit routine. Pass the */ 374 b _C_LABEL(arm_irq_handler)/* trapframe to the handler. */ 375 END(irq_entry) 376 377 /* 378 * Entry point for an FIQ interrupt. 379 * 380 * We don't currently support FIQ handlers very much. Something can 381 * install itself in the FIQ vector using code (that may or may not work 382 * these days) in fiq.c. If nobody does that and an FIQ happens, this 383 * default handler just disables FIQs and otherwise ignores it. 384 */ 385 ASENTRY_NP(fiq_entry) 386 mrs r8, cpsr /* FIQ handling isn't supported, */ 387 bic r8, #(PSR_F) /* just disable FIQ and return. */ 388 msr cpsr_c, r8 /* The r8 we trash here is the */ 389 subs pc, lr, #4 /* banked FIQ-mode r8. */ 390 END(fiq_entry) 391 392 /* 393 * Entry point for an Address Exception exception. 394 * This is an arm26 exception that should never happen. 395 */ 396 ASENTRY_NP(addr_exception_entry) 397 mov r3, lr 398 mrs r2, spsr 399 mrs r1, cpsr 400 adr r0, Laddr_exception_msg 401 b _C_LABEL(panic) 402 Laddr_exception_msg: 403 .asciz "Address Exception CPSR=0x%08x SPSR=0x%08x LR=0x%08x\n" 404 .balign 4 405 END(addr_exception_entry) 406 407 /* 408 * Entry point for the system Reset vector. 409 * This should never happen, so panic. 410 */ 411 ASENTRY_NP(reset_entry) 412 mov r1, lr 413 adr r0, Lreset_panicmsg 414 b _C_LABEL(panic) 415 /* NOTREACHED */ 416 Lreset_panicmsg: 417 .asciz "Reset vector called, LR = 0x%08x" 418 .balign 4 419 END(reset_entry) 420 421 /* 422 * page0 and page0_data -- An image of the ARM vectors which is copied to 423 * the ARM vectors page (high or low) as part of CPU initialization. The 424 * code that does the copy assumes that page0_data holds one 32-bit word 425 * of data for each of the predefined ARM vectors. It also assumes that 426 * page0_data follows the vectors in page0, but other stuff can appear 427 * between the two. We currently leave room between the two for some fiq 428 * handler code to be copied in. 429 */ 430 .global _C_LABEL(page0), _C_LABEL(page0_data) 431 432 _C_LABEL(page0): 433 ldr pc, .Lreset_entry 434 ldr pc, .Lundefined_entry 435 ldr pc, .Lswi_entry 436 ldr pc, .Lprefetch_abort_entry 437 ldr pc, .Ldata_abort_entry 438 ldr pc, .Laddr_exception_entry 439 ldr pc, .Lirq_entry 440 .fiqv: ldr pc, .Lfiq_entry 441 .space 256 /* room for some fiq handler code */ 442 443 _C_LABEL(page0_data): 444 .Lreset_entry: .word reset_entry 445 .Lundefined_entry: .word undefined_entry 446 .Lswi_entry: .word swi_entry 447 .Lprefetch_abort_entry: .word prefetch_abort_entry 448 .Ldata_abort_entry: .word data_abort_entry 449 .Laddr_exception_entry: .word addr_exception_entry 450 .Lirq_entry: .word irq_entry 451 .Lfiq_entry: .word fiq_entry 452 453 /* 454 * These items are used by the code in fiq.c to install what it calls the 455 * "null" handler. It's actually our default vector entry that just jumps 456 * to the default handler which just disables FIQs and returns. 457 */ 458 .global _C_LABEL(fiq_nullhandler_code), _C_LABEL(fiq_nullhandler_size) 459 460 _C_LABEL(fiq_nullhandler_code): 461 .word .fiqv 462 _C_LABEL(fiq_nullhandler_size): 463 .word 4 464 465
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