Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/arm/exception.S
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1 /* $NetBSD: exception.S,v 1.13 2003/10/31 16:30:15 scw Exp $ */ 2 3 /*- 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * exception.S 40 * 41 * Low level handlers for exception vectors 42 * 43 * Created : 24/09/94 44 * 45 * Based on kate/display/abort.s 46 * 47 */ 48 49 #include "assym.inc" 50 51 #include <machine/asm.h> 52 #include <machine/armreg.h> 53 #include <machine/asmacros.h> 54 #include <machine/trap.h> 55 56 __FBSDID("$FreeBSD$"); 57 58 #ifdef KDTRACE_HOOKS 59 .bss 60 .align 4 61 .global _C_LABEL(dtrace_invop_jump_addr) 62 _C_LABEL(dtrace_invop_jump_addr): 63 .word 0 64 .word 0 65 #endif 66 67 .text 68 .align 2 69 70 /* 71 * ASM macros for pushing and pulling trapframes from the stack 72 * 73 * These macros are used to handle the irqframe and trapframe structures 74 * defined above. 75 */ 76 77 /* 78 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 79 * Since the current mode is used, the SVC lr field is not defined. 80 */ 81 #define PUSHFRAME \ 82 sub sp, sp, #4; /* Align the stack */ \ 83 str lr, [sp, #-4]!; /* Push the return address */ \ 84 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ 85 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 86 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 87 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 88 mov r0, r0; /* NOP for previous instruction */ \ 89 mrs r0, spsr; /* Put the SPSR on the stack */ \ 90 str r0, [sp, #-4]!; 91 92 /* 93 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 94 * Since the current mode is used, the SVC lr field is ignored. 95 */ 96 97 #define PULLFRAME \ 98 ldr r0, [sp], #4 ; /* Get the SPSR from stack */ \ 99 msr spsr_fsxc, r0; \ 100 clrex; \ 101 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 102 mov r0, r0; /* NOP for previous instruction */ \ 103 add sp, sp, #(4*17); /* Adjust the stack pointer */ \ 104 ldr lr, [sp], #4; /* Pull the return address */ \ 105 add sp, sp, #4 /* Align the stack */ 106 107 /* 108 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 109 * This should only be used if the processor is not currently in SVC32 110 * mode. The processor mode is switched to SVC mode and the trap frame is 111 * stored. The SVC lr field is used to store the previous value of 112 * lr in SVC mode. 113 */ 114 #define PUSHFRAMEINSVC \ 115 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 116 mov r0, lr; /* Save xxx32 r14 */ \ 117 mov r1, sp; /* Save xxx32 sp */ \ 118 mrs r3, spsr; /* Save xxx32 spsr */ \ 119 mrs r2, cpsr; /* Get the CPSR */ \ 120 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \ 121 orr r2, r2, #(PSR_SVC32_MODE); \ 122 msr cpsr_c, r2; /* Punch into SVC mode */ \ 123 mov r2, sp; /* Save SVC sp */ \ 124 bic sp, sp, #7; /* Align sp to an 8-byte addrress */ \ 125 sub sp, sp, #(4 * 17); /* Pad trapframe to keep alignment */ \ 126 /* and for dtrace to emulate push/pop */ \ 127 str r0, [sp, #-4]!; /* Push return address */ \ 128 str lr, [sp, #-4]!; /* Push SVC lr */ \ 129 str r2, [sp, #-4]!; /* Push SVC sp */ \ 130 msr spsr_fsxc, r3; /* Restore correct spsr */ \ 131 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 132 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ 133 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 134 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 135 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 136 mov r0, r0; /* NOP for previous instruction */ \ 137 mrs r0, spsr; /* Put the SPSR on the stack */ \ 138 str r0, [sp, #-4]! 139 140 /* 141 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 142 * in SVC32 mode and restore the saved processor mode and PC. 143 * This should be used when the SVC lr register needs to be restored on 144 * exit. 145 */ 146 147 #define PULLFRAMEFROMSVCANDEXIT \ 148 ldr r0, [sp], #4; /* Get the SPSR from stack */ \ 149 msr spsr_fsxc, r0; /* restore SPSR */ \ 150 clrex; \ 151 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 152 mov r0, r0; /* NOP for previous instruction */ \ 153 add sp, sp, #(4*15); /* Adjust the stack pointer */ \ 154 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 155 156 /* 157 * Unwind hints so we can unwind past functions that use 158 * PULLFRAMEFROMSVCANDEXIT. They are run in reverse order. 159 * As the last thing we do is restore the stack pointer 160 * we can ignore the padding at the end of struct trapframe. 161 */ 162 #define UNWINDSVCFRAME \ 163 .save {r13-r15}; /* Restore sp, lr, pc */ \ 164 .pad #(2*4); /* Skip user sp and lr */ \ 165 .save {r0-r12}; /* Restore r0-r12 */ \ 166 .pad #(4) /* Skip spsr */ 167 168 #define DO_AST \ 169 ldr r0, [sp]; /* Get the SPSR from stack */ \ 170 mrs r4, cpsr; /* save CPSR */ \ 171 orr r1, r4, #(PSR_I|PSR_F); \ 172 msr cpsr_c, r1; /* Disable interrupts */ \ 173 and r0, r0, #(PSR_MODE); /* Returning to USR mode? */ \ 174 teq r0, #(PSR_USR32_MODE); \ 175 bne 2f; /* Nope, get out now */ \ 176 bic r4, r4, #(PSR_I|PSR_F); \ 177 1: GET_CURTHREAD_PTR(r5); \ 178 ldr r1, [r5, #(TD_FLAGS)]; \ 179 and r1, r1, #(TDF_ASTPENDING|TDF_NEEDRESCHED); \ 180 teq r1, #0; \ 181 beq 2f; /* Nope. Just bail */ \ 182 msr cpsr_c, r4; /* Restore interrupts */ \ 183 mov r0, sp; \ 184 bl _C_LABEL(ast); /* ast(frame) */ \ 185 orr r0, r4, #(PSR_I|PSR_F); \ 186 msr cpsr_c, r0; \ 187 b 1b; \ 188 2: 189 190 191 /* 192 * Entry point for a Software Interrupt (SWI). 193 * 194 * The hardware switches to svc32 mode on a swi, so we're already on the 195 * right stack; just build a trapframe and call the handler. 196 */ 197 ASENTRY_NP(swi_entry) 198 PUSHFRAME /* Build the trapframe on the */ 199 mov r0, sp /* scv32 stack, pass it to the */ 200 bl _C_LABEL(swi_handler) /* swi handler. */ 201 /* 202 * The fork_trampoline() code in swtch.S aranges for the MI fork_exit() 203 * to return to swi_exit here, to return to userland. The net effect is 204 * that a newly created thread appears to return from a SWI just like 205 * the parent thread that created it. 206 */ 207 ASEENTRY_NP(swi_exit) 208 DO_AST /* Handle pending signals. */ 209 PULLFRAME /* Deallocate trapframe. */ 210 movs pc, lr /* Return to userland. */ 211 STOP_UNWINDING /* Don't unwind into user mode. */ 212 EEND(swi_exit) 213 END(swi_entry) 214 215 /* 216 * Standard exception exit handler. 217 * 218 * This is used to return from all exceptions except SWI. It uses DO_AST and 219 * PULLFRAMEFROMSVCANDEXIT and can only be called if the exception entry code 220 * used PUSHFRAMEINSVC. 221 * 222 * If the return is to user mode, this uses DO_AST to deliver any pending 223 * signals and/or handle TDF_NEEDRESCHED first. 224 */ 225 ASENTRY_NP(exception_exit) 226 DO_AST /* Handle pending signals. */ 227 PULLFRAMEFROMSVCANDEXIT /* Return. */ 228 UNWINDSVCFRAME /* Special unwinding for exceptions. */ 229 END(exception_exit) 230 231 /* 232 * Entry point for a Prefetch Abort exception. 233 * 234 * The hardware switches to the abort mode stack; we switch to svc32 before 235 * calling the handler, then return directly to the original mode/stack 236 * on exit (without transitioning back through the abort mode stack). 237 */ 238 ASENTRY_NP(prefetch_abort_entry) 239 #ifdef __XSCALE__ 240 nop /* Make absolutely sure any pending */ 241 nop /* imprecise aborts have occurred. */ 242 #endif 243 sub lr, lr, #4 /* Adjust the lr. Transition to scv32 */ 244 PUSHFRAMEINSVC /* mode stack, build trapframe there. */ 245 adr lr, exception_exit /* Return from handler via standard */ 246 mov r0, sp /* exception exit routine. Pass the */ 247 mov r1, #1 /* Type flag */ 248 b _C_LABEL(abort_handler) 249 END(prefetch_abort_entry) 250 251 /* 252 * Entry point for a Data Abort exception. 253 * 254 * The hardware switches to the abort mode stack; we switch to svc32 before 255 * calling the handler, then return directly to the original mode/stack 256 * on exit (without transitioning back through the abort mode stack). 257 */ 258 ASENTRY_NP(data_abort_entry) 259 #ifdef __XSCALE__ 260 nop /* Make absolutely sure any pending */ 261 nop /* imprecise aborts have occurred. */ 262 #endif 263 sub lr, lr, #8 /* Adjust the lr. Transition to scv32 */ 264 PUSHFRAMEINSVC /* mode stack, build trapframe there. */ 265 adr lr, exception_exit /* Exception exit routine */ 266 mov r0, sp /* Trapframe to the handler */ 267 mov r1, #0 /* Type flag */ 268 b _C_LABEL(abort_handler) 269 END(data_abort_entry) 270 271 /* 272 * Entry point for an Undefined Instruction exception. 273 * 274 * The hardware switches to the undefined mode stack; we switch to svc32 before 275 * calling the handler, then return directly to the original mode/stack 276 * on exit (without transitioning back through the undefined mode stack). 277 */ 278 ASENTRY_NP(undefined_entry) 279 PUSHFRAMEINSVC /* mode stack, build trapframe there. */ 280 mov r4, r0 /* R0 contains SPSR */ 281 adr lr, exception_exit /* Return from handler via standard */ 282 mov r0, sp /* exception exit routine. pass frame */ 283 284 ldr r2, [sp, #(TF_PC)] /* load pc */ 285 #if __ARM_ARCH >= 7 286 tst r4, #(PSR_T) /* test if PSR_T */ 287 subne r2, r2, #(THUMB_INSN_SIZE) 288 subeq r2, r2, #(INSN_SIZE) 289 #else 290 sub r2, r2, #(INSN_SIZE) /* fix pc */ 291 #endif 292 str r2, [sp, #TF_PC] /* store pc */ 293 294 #ifdef KDTRACE_HOOKS 295 /* Check if dtrace is enabled */ 296 ldr r1, =_C_LABEL(dtrace_invop_jump_addr) 297 ldr r3, [r1] 298 cmp r3, #0 299 beq undefinedinstruction 300 301 and r4, r4, #(PSR_MODE) /* Mask out unneeded bits */ 302 cmp r4, #(PSR_USR32_MODE) /* Check if we came from usermode */ 303 beq undefinedinstruction 304 305 ldr r4, [r2] /* load instrution */ 306 ldr r1, =FBT_BREAKPOINT /* load fbt inv op */ 307 cmp r1, r4 308 bne undefinedinstruction 309 310 bx r3 /* call invop_jump_addr */ 311 #endif 312 b undefinedinstruction /* call stadnard handler */ 313 END(undefined_entry) 314 315 /* 316 * Entry point for a normal IRQ. 317 * 318 * The hardware switches to the IRQ mode stack; we switch to svc32 before 319 * calling the handler, then return directly to the original mode/stack 320 * on exit (without transitioning back through the IRQ mode stack). 321 */ 322 ASENTRY_NP(irq_entry) 323 sub lr, lr, #4 /* Adjust the lr. Transition to scv32 */ 324 PUSHFRAMEINSVC /* mode stack, build trapframe there. */ 325 adr lr, exception_exit /* Return from handler via standard */ 326 mov r0, sp /* exception exit routine. Pass the */ 327 b _C_LABEL(intr_irq_handler)/* trapframe to the handler. */ 328 END(irq_entry) 329 330 /* 331 * Entry point for an FIQ interrupt. 332 * 333 * We don't currently support FIQ handlers very much. Something can 334 * install itself in the FIQ vector using code (that may or may not work 335 * these days) in fiq.c. If nobody does that and an FIQ happens, this 336 * default handler just disables FIQs and otherwise ignores it. 337 */ 338 ASENTRY_NP(fiq_entry) 339 mrs r8, cpsr /* FIQ handling isn't supported, */ 340 bic r8, #(PSR_F) /* just disable FIQ and return. */ 341 msr cpsr_c, r8 /* The r8 we trash here is the */ 342 subs pc, lr, #4 /* banked FIQ-mode r8. */ 343 END(fiq_entry) 344 345 /* 346 * Entry point for an Address Exception exception. 347 * This is an arm26 exception that should never happen. 348 */ 349 ASENTRY_NP(addr_exception_entry) 350 mov r3, lr 351 mrs r2, spsr 352 mrs r1, cpsr 353 adr r0, Laddr_exception_msg 354 b _C_LABEL(panic) 355 Laddr_exception_msg: 356 .asciz "Address Exception CPSR=0x%08x SPSR=0x%08x LR=0x%08x\n" 357 .balign 4 358 END(addr_exception_entry) 359 360 /* 361 * Entry point for the system Reset vector. 362 * This should never happen, so panic. 363 */ 364 ASENTRY_NP(reset_entry) 365 mov r1, lr 366 adr r0, Lreset_panicmsg 367 b _C_LABEL(panic) 368 /* NOTREACHED */ 369 Lreset_panicmsg: 370 .asciz "Reset vector called, LR = 0x%08x" 371 .balign 4 372 END(reset_entry) 373 374 /* 375 * page0 and page0_data -- An image of the ARM vectors which is copied to 376 * the ARM vectors page (high or low) as part of CPU initialization. The 377 * code that does the copy assumes that page0_data holds one 32-bit word 378 * of data for each of the predefined ARM vectors. It also assumes that 379 * page0_data follows the vectors in page0, but other stuff can appear 380 * between the two. We currently leave room between the two for some fiq 381 * handler code to be copied in. 382 */ 383 .global _C_LABEL(page0), _C_LABEL(page0_data) 384 385 _C_LABEL(page0): 386 ldr pc, .Lreset_entry 387 ldr pc, .Lundefined_entry 388 ldr pc, .Lswi_entry 389 ldr pc, .Lprefetch_abort_entry 390 ldr pc, .Ldata_abort_entry 391 ldr pc, .Laddr_exception_entry 392 ldr pc, .Lirq_entry 393 .fiqv: ldr pc, .Lfiq_entry 394 .space 256 /* room for some fiq handler code */ 395 396 _C_LABEL(page0_data): 397 .Lreset_entry: .word reset_entry 398 .Lundefined_entry: .word undefined_entry 399 .Lswi_entry: .word swi_entry 400 .Lprefetch_abort_entry: .word prefetch_abort_entry 401 .Ldata_abort_entry: .word data_abort_entry 402 .Laddr_exception_entry: .word addr_exception_entry 403 .Lirq_entry: .word irq_entry 404 .Lfiq_entry: .word fiq_entry 405 406 /* 407 * These items are used by the code in fiq.c to install what it calls the 408 * "null" handler. It's actually our default vector entry that just jumps 409 * to the default handler which just disables FIQs and returns. 410 */ 411 .global _C_LABEL(fiq_nullhandler_code), _C_LABEL(fiq_nullhandler_size) 412 413 _C_LABEL(fiq_nullhandler_code): 414 .word .fiqv 415 _C_LABEL(fiq_nullhandler_size): 416 .word 4 417 418
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